CN107658235B - Method for rapidly measuring characteristic dimension of T/Y-shaped gate in FET production and manufacturing process - Google Patents
Method for rapidly measuring characteristic dimension of T/Y-shaped gate in FET production and manufacturing process Download PDFInfo
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- CN107658235B CN107658235B CN201710914431.2A CN201710914431A CN107658235B CN 107658235 B CN107658235 B CN 107658235B CN 201710914431 A CN201710914431 A CN 201710914431A CN 107658235 B CN107658235 B CN 107658235B
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- H01—ELECTRIC ELEMENTS
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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Abstract
The invention discloses a method for quickly measuring the characteristic dimension of a T/Y-shaped gate in the production and manufacturing process of an FET (field effect transistor), which comprises a normal capacitance range establishing step and a quick measuring step; the rapid measurement step comprises: in the FET production and manufacture, when the metal deposition process of the T/Y-shaped gate is just finished, two leads with the tail ends connected with probes are connected from a capacitance meter; one probe is pricked on the surface of the T/Y-shaped grid to form ohmic connection, and the other probe is pricked on the surface of the source electrode/drain electrode to form ohmic contact; measuring the capacitance values of the grid electrode and the source electrode or the grid electrode and the drain electrode of the FET semi-finished product; and comparing with the normal range of the capacitance value obtained in the normal capacitance range establishing step. The invention is suitable for the rapid measurement of the characteristic dimension of the T/Y-shaped gate in the FET production and manufacturing process.
Description
Technical Field
The invention relates to the field of compound semiconductor production, in particular to a method for quickly measuring the characteristic dimension of a T/Y-shaped gate in the production and manufacturing process of an FET.
Background
The gradual maturity of the production process of compound semiconductors such as GaAs, GaN, InP or SiC has led to their increasing application in the communication industries such as radar, base station, photoelectricity, etc. In order to improve the operating frequency and efficiency, the "T" type gate (or "Y" type gate) process is widely used. Therefore, how to measure the gate length feature size becomes one of the hot spots of interest for engineers.
During the process, the gate length feature size is typically measured in two ways: (1) the first measurement method is to prepare the cross section of the gate by FIB or observe the cross section of the gate by direct fragmentation, but this means damage to the device and even the whole wafer, and moreover, the damage to the wafer or the FIB greatly increases the production cost; (2) the second way is to measure the characteristic dimension of the gate trench by CD-SEM or AFM to determine the characteristic dimension of the "T" type gate length (or "Y" type gate), but if the waiting time is long during the test, the material in the gate trench just etched to be opened is oxidized, which has a great influence on the yield and reliability of the produced FET.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a method for quickly measuring the characteristic dimension of a T/Y-shaped gate in the production and manufacturing process of an FET (field effect transistor). the method is used for quickly detecting the characteristic dimension after the metal deposition process of the gate is completed in the production and manufacturing process, so that a wafer is not damaged, and the detection time is shortened, so that substances in a gate groove which is just etched and opened are prevented from being oxidized.
The purpose of the invention is realized by the following technical scheme: a method for rapidly measuring the characteristic dimension of a T/Y-shaped gate in the production and manufacturing process of an FET comprises a normal capacitance range establishing step and a rapid measuring step, wherein the normal capacitance range establishing step comprises the following substeps:
s11: under each specification model, respectively selecting a plurality of FETs (field effect transistors) which are manufactured by adopting a normal process and comprise T/Y-shaped grids;
s12: respectively measuring the capacitance values of the T/Y-shaped grid electrode and the source electrode or the T/Y-shaped grid electrode and the drain electrode;
s13: establishing a normal range of the capacitance value under each specification model;
the rapid measurement step comprises the following substeps:
s21: in the FET production manufacturing, when the metal deposition process of the T/Y type gate is just completed, the flow proceeds to step S22;
s22: two leads with the tail ends connected with the probes are connected from the capacitance meter;
s23: one probe is pricked on the surface of the T/Y-shaped grid to form ohmic connection, and the other probe is pricked on the surface of the source electrode/drain electrode to form ohmic contact;
s24: measuring the capacitance values of the grid electrode and the source electrode or the grid electrode and the drain electrode of the FET semi-finished product through a capacitance meter;
s25: comparing the specification model of the FET and the capacitance value obtained in step S24 with the normal range of the capacitance value obtained in the normal capacitance range establishing step: if the capacitance value obtained in step S24 is out of the normal range, it indicates that there is a process problem in the manufactured T/Y gate, otherwise there is no problem.
Further, in step S25, when it is detected that there is a process problem in the manufactured T/Y gate, the FET semi-finished product is not subjected to the subsequent process treatment.
Further, the material of the FET includes GaAs, GaN, InP, or SiC compound semiconductor.
Further, the characteristic dimension includes a gate width and a gate length.
Furthermore, the range of the grid width is 1um ~100mm, the range of the grid length is 0.05um ~5 um.
Furthermore, the probe is a small-signal probe with a shielding wire, and the diameter of the needle point is 0.1-0.2 μm.
Furthermore, the lead is a semi-rigid tungsten lead, the probe is made of tungsten made of the same material as the lead, and the shielding wire is made of gold-plated copper wire and is isolated from the tungsten lead by a Teflon material.
Furthermore, the semi-rigid tungsten wire is 50 ohms, the diameter of the semi-rigid tungsten wire is 0.008 inches, and the diameter of the probe is 0.1-0.2 μm.
Furthermore, the measurement frequency of the capacitance meter is 1MHz, the measurement precision is 10aF, and the measurement range is 50 aF-10 nF.
Further, step S21 and step S23 are replaced with:
s21: in the FET production manufacturing, when the entire FET production process is completed, the flow proceeds to step S22;
s23: one probe is pricked on the grid electrode pin to form ohmic connection, and the other probe is pricked on the source electrode pin or the drain electrode pin to form ohmic contact; the grid pin is connected with the grid of the FET through a metal interconnection line, the source pin is connected with the source of the FET through the metal interconnection line, and the drain pin is connected with the drain of the FET through the metal interconnection line.
The invention has the beneficial effects that:
(1) the invention is suitable for the rapid measurement of the characteristic dimension of the T/Y-shaped gate in the production and manufacturing process of the FET, and particularly, the rapid detection is carried out after the metal deposition process of the gate is completed in the production and manufacturing process, so that the wafer is not damaged, and the detection time is reduced, thereby preventing substances in the gate groove which is just etched and opened from being oxidized. The method has the characteristics of convenience, no damage, good compatibility, low cost, easy operation and the like.
Specifically, the time required by CD-SEM and AFM tests is generally 10 minutes or more, the CD-SEM and AFM tests belong to large-scale precision equipment, and the price of one piece of equipment is generally more than one million RMB; the method only needs the capacitance meter and the probe, the cost can be generally controlled within 10 ten thousand RMB, and the testing time can be within 5 minutes. In addition, the method of the present invention is directed to T-shaped (or Y-shaped) grating, if the grating is already done and the grating length is measured again, even CD-SEM or AFM cannot directly measure, because the shape of the upper width and the lower width cannot measure the grating length from the upper side, and only by destructively cleaving the wafer or cutting a cross section through FIB, the cost of one wafer is at least 10 tens of thousands of rmb, FIB sampling takes more than half an hour, and FIB equipment is expensive, typically more than 100 tens of thousands of dollars.
(2) When the process problem of the manufactured T/Y-shaped gate is detected after the metal deposition process of the gate is finished, the subsequent process treatment is not carried out on the FET semi-finished product, and the subsequent production cost is saved.
(3) The gate characteristic dimension of the FET can be detected after the whole FET is produced, and the influence on the gate characteristic dimension caused by other problems is avoided.
Drawings
FIG. 1 is a flow chart of the method of the present invention;
FIG. 2 is a schematic sectional view of measurement according to example 1 of the present invention;
FIG. 3 is a schematic plan view of measurement according to example 2 of the present invention;
in the figure, 1-gate, 2-source/drain, 3-capacitance table, 4-wire, 5-probe, 6-FET, 7-gate pin, 8-source pin, 9-drain pin, 10-metal interconnect.
Detailed Description
The technical scheme of the invention is further described in detail by combining the attached drawings:
embodiment 1 is applied to the FET manufacturing process, and can avoid the problem caused by the metal deposition process of the T/Y gate, but still waste resources in the subsequent production.
As shown in FIG. 1, a method for rapidly measuring the characteristic dimension of a T/Y-shaped gate in the manufacturing process of an FET comprises a normal capacitance range establishing step and a rapid measuring step, wherein the normal capacitance range establishing step is prior to the rapid measuring step.
The normal capacitance range establishing step comprises the following substeps:
s11: under each specification model, a plurality of FETs 6 which are manufactured by a normal process and comprise a T/Y-shaped grid 1 are respectively selected;
s12: respectively measuring the capacitance values of the T/Y type grid electrode 1 and the source electrode 2, or the T/Y type grid electrode 1 and the drain electrode 2; wherein the measuring mode can be that the transverse section of the gate is prepared by FIB or the transverse section of the gate is observed by direct splitting, or the characteristic dimension of the gate groove is measured by CD-SEM or AFM to determine the characteristic dimension of the T-shaped gate length, or the measuring mode is carried out by a capacitance table 3;
s13: and establishing a normal range of the capacitance value under each specification model.
The rapid measurement step comprises the following substeps:
s21: in the FET6 production manufacturing, when the metal deposition process of the T/Y type gate is just completed, the flow proceeds to step S22;
s22: two leads 4 with the tail ends connected with probes 5 are connected from the capacitance meter 3;
s23: one probe 5 is pricked on the surface of the T/Y type grid 1 to form ohmic connection, and the other probe 5 is pricked on the surface of the source electrode 2/drain electrode 2 to form ohmic contact; the schematic diagram after connection is shown in fig. 2, which is a Y-shaped grid;
s24: the capacitance values of the gate 1 and the source 2, or the gate 1 and the drain 2 of the FET6 semi-finished product are measured by capacitance table 3;
s25: comparing the specification and model of the FET6 and the capacitance obtained in step S24 with the normal range of the capacitance obtained in the normal capacitance range establishing step: if the capacitance value obtained in the step S24 exceeds the normal range, it indicates that there is a process problem in the manufactured T/Y gate 1, and when it is detected that there is a process problem in the manufactured T/Y gate 1, the subsequent process treatment is not performed on the semi-finished product of the FET 6; otherwise, no problem exists, and the subsequent process treatment is continued on the FET6 semi-finished product.
Example 2 is applied after the FET6 manufacturing process, and is used for testing after the manufacturing process is completed. As shown in fig. 3, the completed FET6 has a Gate lead 7 (Gate Pad) connected to the Gate 1 of the FET6 via a metal interconnect 10, a Source lead 8 (Source Pad) connected to the Source 2 of the FET6 via the metal interconnect 10, and a Drain lead 9 (Drain Pad) connected to the Drain 2 of the FET6 via the metal interconnect 10.
As shown in fig. 1, a method for rapid measurement of T/Y gate feature size during FET6 manufacturing includes a normal capacitance range establishing step and a rapid measurement step, the normal capacitance range establishing step precedes the rapid measurement step. The normal capacitance range establishing step is similar to that in embodiment 1, and is not described herein again.
And the fast measuring step comprises the following substeps:
s21: in the FET6 production manufacturing, when the production process of the entire FET6 is completed, the flow proceeds to step S22;
s22: two leads 4 with the tail ends connected with probes 5 are connected from the capacitance meter 3;
s23: one of the probes 5 is pricked on the grid electrode pin 7 to form ohmic connection, and the other probe 5 is pricked on the source electrode pin 8 or the drain electrode pin 9 to form ohmic contact; the schematic diagram after connection is shown in fig. 3;
s24: the capacitance values of the gate 1 and the source 2, or the gate 1 and the drain 2 of the FET6 semi-finished product are measured by capacitance table 3;
s25: comparing the specification and model of the FET6 and the capacitance obtained in step S24 with the normal range of the capacitance obtained in the normal capacitance range establishing step: if the capacitance value obtained in the step S24 exceeds the normal range, it indicates that there is a process problem in the manufactured T/Y-type grid, and if it is detected that there is a process problem in the manufactured T/Y-type grid 1, it is regarded as a waste product, and a disposal process or the like may be performed; otherwise, the product can leave the factory without problems.
While in any of the above embodiments the FET6 material includes, but is not limited to, GaAs, GaN, InP or SiC compound semiconductors. The characteristic dimension include the bars wide and the bars long, the wide range of bars be 1um ~100mm, the range of bars long is 0.05um ~5 um. The probe 5 is a small-signal probe 5 with a shielding wire, and the diameter of the needle point is 0.1-0.2 μm. The lead 4 is a semi-rigid tungsten lead 4, the probe 5 is tungsten made of the same material as the lead 4, and the shielding wire is a gold-plated copper wire and is isolated from the tungsten lead 4 by a Teflon material. The semi-rigid tungsten wire 4 is 50 ohms. The semi-rigid tungsten wire 4 is 0.008 inch in diameter, and the probe 5 is 0.1-0.2 μm in diameter. The measurement frequency of the capacitance meter 3 is 1MHz, the measurement precision is 10aF, and the measurement range is 50 aF-10 nF.
While the present invention has been described by way of examples, and not by way of limitation, other variations of the disclosed embodiments, as would be readily apparent to one of skill in the art, are intended to be within the scope of the present invention, as defined by the claims.
Claims (10)
1. A method for rapidly measuring the characteristic dimension of a T/Y-shaped gate in the production and manufacturing process of an FET is characterized in that: the method comprises a normal capacitance range establishing step and a rapid measuring step, wherein the normal capacitance range establishing step comprises the following substeps:
s11: under each specification model, respectively selecting a plurality of FETs (field effect transistors) which are manufactured by adopting a normal process and comprise T/Y-shaped grids;
s12: respectively measuring a first capacitance value of a T/Y-shaped grid electrode and a source electrode of the FET or a second capacitance value of the T/Y-shaped grid electrode and a drain electrode of the FET;
s13: establishing a normal range of the first capacitance value or the second capacitance value under each specification type;
the rapid measurement step comprises the following substeps:
s21: in the FET production manufacturing, when the metal deposition process of the T/Y type gate is just completed, the flow proceeds to step S22;
s22: two leads with the tail ends connected with the probes are connected from the capacitance meter;
s23: one probe is pricked on the surface of the T/Y type grid electrode to form ohmic connection, and the other probe is pricked on the surface of the source electrode/drain electrode to form ohmic contact;
s24: measuring a third capacitance value of the grid electrode and the source electrode of the FET semi-finished product or a fourth capacitance value of the grid electrode and the drain electrode of the FET semi-finished product through a capacitance meter;
s25: comparing the specification type of the FET and the normal range of the third capacitance value obtained in the step of establishing the normal capacitance range with the first capacitance value obtained in the step of S24, or comparing the specification type of the FET and the normal range of the fourth capacitance value obtained in the step of establishing the normal capacitance range with the second capacitance value obtained in the step of S24: if the third capacitance value or the fourth capacitance value obtained in step S24 exceeds the normal range, it indicates that there is a process problem in the manufactured T/Y gate, otherwise there is no problem.
2. The method of claim 1, wherein the method comprises the steps of: in step S25, when it is detected that there is a process problem in the manufactured T/Y gate, the FET semi-finished product is not subjected to the subsequent process treatment.
3. The method of claim 1, wherein the method comprises the steps of: the material of the FET includes GaAs, GaN, InP or SiC compound semiconductor.
4. The method of claim 1, wherein the method comprises the steps of: the characteristic dimension comprises a gate width and a gate length.
5. The method of claim 4, wherein the method comprises the following steps: the range of the grid width is 1 um-100 mm, and the range of the grid length is 0.05 um-5 um.
6. The method of claim 5, wherein the method comprises the steps of: the probe is a small-signal probe with a shielding wire, and the diameter of the needle point is 0.1-0.2 mu m.
7. The method of claim 6, wherein the method comprises the steps of: the lead is a semi-rigid tungsten lead, the probe is tungsten made of the same material as the lead, and the shielding wire is a gold-plated copper wire and is isolated from the tungsten lead by a Teflon material.
8. The method of claim 7, wherein the step of measuring the T/Y gate feature size during the manufacturing process of FET comprises: the semi-rigid tungsten wire is 50 ohms; the diameter of the semi-rigid tungsten wire is 0.008 inch, and the diameter of the probe is 0.1-0.2 μm.
9. The method of claim 1, wherein the method comprises the steps of: the measurement frequency of the capacitance meter is 1MHz, the measurement precision is 10aF, and the measurement range is 50 aF-10 nF.
10. The method for rapidly measuring the characteristic dimension of the T/Y-shaped gate in the FET production and manufacturing process according to any one of claims 1 to 9, wherein the method comprises the following steps: step S21 and step S23 are replaced with:
s21: in the FET production manufacturing, when the entire FET production process is completed, the flow proceeds to step S22;
s23: one probe is pricked on the grid electrode pin to form ohmic connection, and the other probe is pricked on the source electrode pin or the drain electrode pin to form ohmic contact; the grid pin is connected with the grid of the FET through a metal interconnection line, the source pin is connected with the source of the FET through the metal interconnection line, and the drain pin is connected with the drain of the FET through the metal interconnection line.
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| KR20040033621A (en) * | 2002-10-15 | 2004-04-28 | 주식회사 하이닉스반도체 | Method for measuring critical dimension of semiconductor device |
| KR100499412B1 (en) * | 2003-05-15 | 2005-07-07 | 주식회사 하이닉스반도체 | Method for measuring CD using capacitance |
| CN105573273B (en) * | 2015-12-15 | 2018-08-14 | 上海华虹宏力半导体制造有限公司 | The method for improving performance of semiconductor device fluctuation |
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| CN101692426A (en) * | 2009-10-14 | 2010-04-07 | 上海宏力半导体制造有限公司 | Method for preparing vertical double-diffusion MOS transistor |
| CN101692462A (en) * | 2009-10-14 | 2010-04-07 | 上海宏力半导体制造有限公司 | Vertical double-diffusion MOS transistor structure |
| CN101719472A (en) * | 2009-11-18 | 2010-06-02 | 上海宏力半导体制造有限公司 | Method for preparing vertical double-diffusion MOS transistor |
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