CN107645768A

CN107645768A - A kind of method for synchronizing time and device for intra-office distribution

Info

Publication number: CN107645768A
Application number: CN201610575978.XA
Authority: CN
Inventors: 吕博; 胡昌军; 潘峰
Original assignee: China Academy of Telecommunications Research CATR
Current assignee: China Academy of Information and Communications Technology CAICT
Priority date: 2016-07-20
Filing date: 2016-07-20
Publication date: 2018-01-30
Anticipated expiration: 2036-07-20
Also published as: CN107645768B

Abstract

The invention provides a kind of method for synchronizing time and interface for intra-office distribution, technical scheme is：Master clock sends main EToD frames from the local timing interface of itself to from clock；First phase deviation between clock calculation and master clock, and by returning to master clock from EToD frames；Master clock calculates and from the second phase deviation between clock, and master clock is determined and from the phase deviation between clock according to first phase deviation and second phase deviation, the phase deviation is issued from clock by main EToD frames, so that phase adjustment is performed from clock according to the phase deviation, so as to realize the automatic compensation to transmission cable time delay.

Description

Time synchronization method and device for intra-office distribution

Technical Field

The present invention relates to the field of clock synchronization technologies, and in particular, to a time synchronization method and apparatus for intra-office distribution.

Background

With the emergence of the demand of high-precision time ground transmission of TD-SCDMA and TD-LTE systems, network equipment, base station equipment and the like are required to provide various types of high-precision time synchronization interfaces. The high-precision time synchronization interface can be divided into two types of an intra-office synchronization interface and an inter-office synchronization interface: the interoffice synchronization interface is generally applied to the transmission of time synchronization signals of network equipment in long-span and wide area networks, such as PTNs, OTNs, IPRANs and the like, and the current mature technology is PTP (1588v2), so that sub-microsecond time synchronization precision can be realized; the intra-office synchronization interface is generally applied to timing connection between different devices (such as a synchronization device and a transmission device, a transmission device and a timed device, and different types of transmission devices) in a communication station or timing distribution between a time distribution system and the timed device.

The local synchronization interface comprises 1PPS + ToD (Time of Day), NTP, IRIG-B and the like, wherein 1PPS + ToD is the most typical high-precision local synchronization interface. The 1PPS + ToD is divided into a 1PPS second pulse signal and a ToD time information, the rising edge of 1PPS is used for representing high-precision phase information of a part within seconds, the ToD information is used for representing time information of seconds, minutes, hours, days and the like, the two parts jointly form a 1PPS + ToD frame signal, and the time precision of hundreds of nanoseconds even dozens of nanoseconds can be achieved in a local area. At present, 1PPS + ToD is widely applied to a base station machine room of an operator and a transformer substation system of a power private network.

However, at present, 1PPS + ToD adopts a simplex mode, and cannot automatically compensate for the time delay of a transmission cable at a receiving end (a slave clock end), and when the length of an antenna feeder or the length of an intra-office relay cable is long, even if a certain inherent error still exists in the time delay through manual compensation, along with the improvement of the requirement on synchronization precision in future LTE-a, 5G, internet of things and quantum communication, the inherent error cannot be substantially eliminated by an existing 1PPS + ToD intra-office timing interface, so that the requirement on ultra-high precision time synchronization cannot be met.

Disclosure of Invention

In view of the above, the present invention provides a time synchronization method and apparatus for intra-office distribution, which can automatically compensate for transmission cable delay.

In order to achieve the purpose, the invention provides the following technical scheme:

a method for time synchronization for intra-office distribution, applied to a master clock, the method comprising:

the method comprises the steps that a main enhanced time of day EToD frame is sent to a slave clock by an internal timing interface of the slave clock;

receiving a slave EToD frame which is returned by a slave clock and carries a first phase deviation between the slave clock and a master clock at an internal timing interface of the master clock, and detecting and determining a second phase deviation between the master clock and the slave clock;

and calculating the phase deviation between the slave clock and the master clock according to the first phase deviation and the second phase deviation, generating a master EToD frame carrying the phase deviation, and transmitting the master EToD frame from the local timing interface of the master clock to the slave clock so that the slave clock performs time synchronization adjustment according to the master EToD frame.

Another time synchronization method for intra-office distribution is applied to a slave clock, and the method comprises the following steps:

receiving a master enhanced time of day (EToD) frame sent by a master clock at an intra-local timing interface of the slave clock, and detecting and determining a first phase deviation between the slave clock and the master clock;

the method comprises the steps that a slave EToD frame carrying first phase deviation is sent to a master clock from an internal timing interface of the slave clock, a master EToD frame carrying phase deviation between the slave clock and the master clock and returned by the master clock is received, and time synchronization adjustment is carried out according to the master EToD frame returned by the master clock.

A time synchronizing device for intra-office distribution, applied to a master clock, the device comprising: an EToD generation unit, an EToD analysis unit, an HPPS phase detection unit and an offset calculation unit;

the EToD generating unit is used for sending a master enhanced time of day EToD frame to the slave clock from the local timing interface of the master clock; the local timing interface is used for generating a master EToD frame carrying the phase deviation between the slave clock and the master clock calculated by the offset calculation unit, and sending the master EToD frame to the slave clock from the local timing interface of the master clock so as to enable the slave clock to perform time synchronization adjustment according to the master EToD frame;

the EToD analysis unit is used for receiving a slave EToD frame which is returned by the slave clock and carries the first phase deviation between the master clock and the slave clock by the local timing interface of the master clock after the EToD generation unit sends the master EToD frame to the slave clock from the local timing interface of the master clock;

the HPPS phase detection unit is configured to detect and determine a second phase deviation between the master clock and the slave clock when the EToD analysis unit receives, at the local timing interface of the master clock, a slave EToD frame carrying a first phase deviation between the master clock and the slave clock and returned by the slave clock;

the offset calculating unit is used for calculating the phase deviation between the slave clock and the master clock according to the first phase deviation and the second phase deviation.

Another time synchronization apparatus for intra-office distribution, applied to a slave clock, includes: an EToD analysis unit, an HPPS phase detection unit, an EToD generation unit and a synchronization adjustment unit;

the EToD analysis unit is used for receiving a master enhanced time of day EToD frame sent by a master clock at an intra-office timing interface of a slave clock; the EToD generation unit is used for receiving a master EToD frame which is returned by the master clock and carries the phase deviation between the slave clock and the master clock after sending a slave EToD frame carrying the first phase deviation to the master clock from the local timing interface of the slave clock;

the HPPS phase detection unit detects and determines a first phase deviation between a slave clock and a master clock when an internal timing interface of the slave clock receives a master EToD frame sent by the master clock;

the EToD generating unit is used for sending a slave EToD frame carrying a first phase deviation from an internal timing interface of a slave clock to a master clock;

and the synchronous adjusting unit is used for performing time synchronous adjustment according to the main EToD frame returned by the main clock.

According to the technical scheme, in the invention, the master clock obtains the first phase deviation between the slave clock and the master clock determined by the slave clock detection and the second phase deviation between the master clock and the slave clock determined by the master clock detection by transmitting the master EToD frame to the slave clock and receiving the slave EToD frame returned by the slave clock, calculates the actual phase deviation between the slave clock and the master clock according to the first phase deviation and the second phase deviation, and transmits the phase deviation to the slave clock so that the slave clock performs phase adjustment according to the phase deviation, thereby realizing automatic compensation of the transmission cable delay.

Drawings

FIG. 1 is a schematic diagram of a 1PPS + ToD time synchronization implementation process in the prior art;

FIG. 2 is a schematic diagram of signal transmission time distribution of an HPPS + EToD frame according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating an EToD frame structure according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a half-duplex communication process between a master clock and a slave clock according to an embodiment of the present invention;

FIG. 5 is a diagram of a half-duplex communication topology between a master clock end interface device and a slave clock end interface device in accordance with an embodiment of the present invention;

FIG. 6 is a flow chart of a method for time synchronization for local distribution according to an embodiment of the present invention;

FIG. 7 is a flow chart of a method for time synchronization for local distribution according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a time synchronizer for local distribution according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of a time synchronization apparatus for local distribution according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention are described in detail below with reference to the accompanying drawings according to embodiments.

Referring to fig. 1, fig. 1 is a schematic diagram of a 1PPS + ToD time synchronization implementation process in the prior art, including the following steps:

step 101, the master clock sends a 1PPS + ToD frame signal to the slave clock.

The 1PPS + ToD frame signal transmitted by the master clock reaches the slave clock after being transmitted by a certain length of cable (the transmission time delay of about 5ns is generated by 1 meter of cable). The 1PPS + ToD frame signal is composed of a 1PPS second pulse signal and ToD time information, wherein the 1PPS is derived from a reference signal of a local clock of the master clock, and the ToD time information is time information of the local clock of the master clock.

Step 102, the slave clock receives the 1PPS + ToD frame signal of the master clock, aligns the local 1PPS second pulse signal of the slave clock to the 1PPS second pulse signal of the master clock by using the phase calibration technology (phase adjustment), and performs time adjustment according to the ToD time information to complete time synchronization.

The slave clock has a 1PPS reference signal derived from the local clock of the slave clock, the 1PPS signals at two ends have a phase deviation before the slave clock is time-synchronized with the master clock, and the phase deviation can be represented by the rising edge of the 1PPS signal.

As can be seen from the time synchronization implementation process shown in fig. 1, the key to implement the time synchronization between the slave clock and the master clock is to detect and compensate the phase deviation from the master clock, however, in the prior art 1PPS + ToD technology, because the simplex communication method is adopted between the master clock and the slave clock, the phase deviation Δ phase detected by the slave clock should actually be composed of two parts, namely delay and offset, where delay denotes the fixed transmission delay generated by the transmission cable between the master clock and the slave clock, and offset is the inherent phase deviation between the master clock and the slave clock. Obviously, at the slave clock end, the phase offset that should be theoretically calibrated is offset, but the slave clock can only detect Δ phase, and cannot distinguish delay from offset, so that an error occurs in the time synchronization adjustment result.

The problem that the existing 1PPS + ToD technology cannot automatically compensate the transmission delay of the cable is solved. The invention changes the negotiation mode of the existing 1PPS + ToD technology: the original simplex communication mode that a 1PPS + ToD frame signal is generated once at the master clock end for 1 second and transmitted to the slave clock end is changed into a half-duplex communication mode that the master clock and the slave clock alternately transmit an HPPS + EToD frame signal in a time division multiplexing mode.

The following is a detailed description of the specific implementation principles of the present invention:

in the present invention, an HPPS + EToD interface, a master EToD frame (i.e. HPPS + EToD frame signal from the master clock to the slave clock), and a slave EToD frame (i.e. HPPS + EToD frame signal from the slave clock to the master clock) are defined.

HPPS + EToD interface

The HPPS represents a Half Second Pulse (Pulse per Half Second) signal, and similar to 1PPS, a rising edge is used as a right-time edge, the rising time is less than 50ns, the Pulse width is 20 ms-200 ms, and the sending period is 1 Second.

The EToD represents enhanced ToD information, which is enhancement and improvement of original ToD information, the EToD time information includes two parts, the first part of time information (referred to as first time information for short, actually takes a value of time information that an EToD frame sender sends the EToD frame) is similar to the ToD time information, and the second part of time information (referred to as second time information for short) represents a phase deviation between a master clock and a slave clock (detailed description is made later).

It is worth noting that the HPPS + EToD interface defined in the present invention adopts a half-duplex negotiation method between the master clock and the slave clock, and divides the HPPS + EToD frame signal into a master EToD frame and a slave EToD frame according to the difference of the transceiving ends.

In one embodiment of the present invention, the specific requirements of the HPPS + EToD interface are as follows:

the baud rate of the EToD frame defaults to 9600, no parity, 1 start bit (indicated by low), 1 stop bit (indicated by high), idle frame high, 8 data bits, should start transmitting the EToD frame 50ms after the HPPS rising edge (i.e., start time in fig. 2), and completes transmitting within 250 ms. The HPPS rising edge time marks the phase information.

The EToD frame is divided into a main EToD frame and a slave EToD frame, the sending frequency is 1 time per second, and the EToD frame is sent at a main time terminal and a slave clock terminal in sequence by adopting a half-duplex mode; as shown in fig. 2, the master clock completes transmission of the master EToD frame within the previous 500ms, and the slave clock completes transmission of the slave EToD frame within the next 500ms after receiving the master EToD frame.

For the HPPS second pulse, a rising edge is used as an on-time edge, the rising time is less than 50ns, and the pulse width is 20 ms-200 ms.

As shown in fig. 2, the HPPS + EToD frame signal (master EToD frame or slave EToD frame) is sent completely and is timed, and the time interval from the beginning of the next HPPS + EToD frame signal is the inversion protection time (the inversion protection time is 500ms — the start time — the EToD frame sending time is 200 ms). And completing the phase detection, time delay and phase deviation calculation, CRC check and other processing of the HPPS pulse signal within the inversion protection time. And after the reverse protection time, the transmission switching of the master EToD frame and the slave EToD frame is carried out, namely after the master EToD frame of the master clock is sent, the master EToD frame is changed into the slave clock to send the slave EToD frame after the reverse protection time, and conversely, after the slave EToD frame of the slave clock is sent, the slave EToD frame is changed into the master clock to send the master EToD frame after the reverse protection time.

It should be noted that the value of the baud rate of the EToD frame is limited by the length of the transmission cable and the length of the EToD frame, as long as the baud rate of the EToD frame can ensure that the transmission time of the EToD frame on the longest transmission cable in the office does not exceed the specified transmission time (transmission time) of the EToD frame.

When the physical interface where the HPPS + EToD interface is located sends the HPPS + EToD frame signal, the physical connector may adopt a 422 level mode, and the physical connector may adopt RJ45, whose sequence requirement is as shown in table one:

line sequence	Signal definition	Description of the invention
			1	NC	The default state is suspended (high resistance)
2	NC	The default state is suspended (high resistance)
			3	422_1_N	HPPS
4	GND	RS422 level GND
			5	GND	RS422 level GND
6	422_1_P	HPPS
			7	422_2_N	EToD time information
8	422_2_P	EToD time information

Watch 1

Two, a master EToD frame and a slave EToD frame.

In one embodiment of the invention, the EToD frames (including the master EToD frame and the slave EToD frame) are transmitted using complete 8-bit one-byte data, and the messages are classified using two levels of message type and message ID with checksum protection. For domains of more than one byte, following the Big Endian specification, bit0 represents the Least Significant Bit (LSB) of the byte, with bit0 being sent first for each byte sent.

The master EToD frame and the slave EToD frame adopt the same frame structure, and specifically, as shown in fig. 3, comprise four parts, namely a frame header, a message length, a payload field, and a checksum (FCS), wherein,

the frame header consists of two bytes, SYNC CHAR1 and SYNC CHAR 2. SYNC CHAR1 is represented by a fixed value of 0x43, representing the "C" character in ASCII code; SYNC CHAR2 is represented by a fixed value of 0x4D, representing the "M" character in the ASCII code.

The message header consists of two bytes of message CLASS and message ID. CLASS specifies the basic classification of an EToD frame, taking one byte. The message ID defines the number of a specific EToD frame, occupying one byte.

Message length, which takes two bytes, the effective range of message length calculation includes only the payload (payload) portion, and does not include the header, length itself, and checksum.

The payload field, which carries the message content (i.e., time information), is composed of a plurality of bytes, and is described in detail when the format of the EToD information is described later.

Checksum, initial value set to 0xFF, input data need not be inverted. The check algorithm may employ a right-shift algorithm. The output check data does not need to be inverted. When the check byte is sent, the least significant bit0 is sent first, and the sumThe data bytes are consistent. The check rule may be a CRC check rule of 1PPS + ToD technology in chinese row standard, for example, a polynomial g (x) x⁸+x⁵+x⁴+1 the checksum is calculated.

In the above frame structure, the EToD time information is composed of four parts, a message header, a message length, a payload, and a checksum (FCS), wherein,

in the message header of the primary EToD frame, CLASS takes a value of 0X01, and the message ID takes a value of 0X20, and the format of the content of the message carried in the load domain is specifically shown in table two:

watch two

In the second table, the second in week, the number of weeks, and the leaves represent time information of more than second, that is, the first part of the time information in the aforementioned EToD time information, and the ms, μ s, ns, and ps parts of the offset represent time information of less than second, that is, the second part of the time information in the aforementioned EToD time information, is a phase offset value, specifically, an actual phase offset (offset) between the slave clock and the master time frame in the master EToD frame.

The following is an example of a specific master EToD frame:

43 4D 01 20 00 10 00 02 BB 45 01 0E 11 00 00 06 11 0F 00 BC 11 FE 17

wherein:

0x 430 x4D frame header SYNC CHAR1, SYNC CHAR 2;

0x 010 x20 message header, this combination represents the EToD time information sent by the master clock;

a message length field of 0x000x 10, representing a message length of 16 bytes;

a load domain, wherein the specific message content of the load domain is divided into the following parts:

1)0x0A 0x 020 xBB 0x 45: the second in the GPS time week is 179013 seconds;

2)0x 010 x 0E: the GPS time cycle number is 270 cycles;

3)0x 11: leap Second is 17 seconds;

4)0x 00: the pulse per second state is "normal";

5)0x 000x 06: the ms portion of offset is +6 ms;

6)0x 110 x 0F: the μ s portion of offset is-271 μ s;

7)0x 000 xBC: the ns portion of offset is +188 ns;

8)0x 110 xFE: the ps portion of the offset is-510 ps;

0x17 CRC checksum.

From the ms, μ s, ns, ps part of the offset in the main EToD frame in the above example, it can be known that the offset is 6ms-271 μ s +188ns-510ps 5729187.49 ns.

From the message header of the EToD frame, CLASS takes a value of 0X01, and the message ID takes a value of 0X21, and the format of the message content carried by the payload field is specifically shown in table three:

watch III

In the third table, the ms, μ s, ns and ps parts of Δ phase represent time information of less than second, that is, the second part of the time information of the aforementioned EToD is a phase offset value, specifically, a first phase offset between the slave clock and the master clock, which is obtained by comparing the HPPS rising edge of the master clock with the HPPS rising edge of the slave clock in the slave EToD frame.

As can be seen from table three above, the first part of the EToD time information is not carried in the EToD frame. However, it should be noted that in practical implementation, the slave EToD frame may also carry the first part of the aforementioned EToD time information, which is not used in the time synchronization process, as the master EToD frame.

The following is a specific example of a slave EToD frame:

43 4D 01 21 00 10 00 06 11 0F 00 BC 11 FE 00 00 00 00 00 00 00 00 EE

wherein:

0x 430 x4D frame header SYNC CHAR1, SYNC CHAR 2;

0x 010 x21 message header, this combination representing the EToD time information sent from the clock;

a message length field of 0x000x 10, representing a message length of 16 bytes;

a payload field of 0x000x 060 x 110 x0F 0x000 xBC0x 110 xFE 0x000x 000x 000x 000x 000x 000x 000x00, wherein the specific message content of the payload field is divided as follows:

1)0x 000x 06: the ms portion of Δ phase is +6 ms;

2)0x 110 x 0F: the μ s portion of Δ phase is-271 μ s;

3)0x 000 xBC: the ns portion of Δ phase is +188 ns;

4)0x 110 xFE: the ps fraction of Δ phase is-510 ps;

5)0x 000x 000x 000x 000x00 reserved fields are all 0.

0xEE CRC check value.

From the ms, μ s, ns, ps part of Δ phase in the EToD frame in the above example, it is known that Δ phase is 6ms-271 μ s +188ns-510 ps-5729187.49 ns.

In table two and table three, U1, U2, and U4 represent assigned char, assigned home, and assigned long, respectively; i1 and I2 represent signed char and signed short, respectively.

After defining the HPPS + EToD interface, the master EToD frame and the slave EToD frame, the master clock and the slave clock use respective local timing interfaces (configured as the HPPS + EToD interfaces) to interact the master EToD frame and the slave EToD frame in a time division multiplexing mode, calculate the phase deviation offset between the slave clock and the master clock in the interaction process and perform time synchronization adjustment according to the phase deviation offset, thereby realizing time synchronization.

The following describes a half-duplex communication process between a master clock and a slave clock according to an embodiment of the present invention with reference to fig. 4 and 5, where fig. 4 is a diagram of a half-duplex communication process between a master clock and a slave clock according to an embodiment of the present invention, and fig. 5 is a diagram of a half-duplex communication topology between a master clock end interface device and a slave clock end interface device according to an embodiment of the present invention.

As shown in fig. 4, the half-duplex communication process between the master clock and the slave clock includes the following steps:

step 401, master clock and slave clock initialization. Wherein the master clock sets the initialization of the phase offset to 0ns, and the initial value of the second phase offset Δ phase2 to 0 ns; the slave clock sets the initial value of the first phase deviation Δ phase1 to 0 ns.

As shown in fig. 5, the interface device at the master clock end includes an EToD generation unit, which is used to perform initialization of offset and Δ phase 2; the slave-clock-side interface device includes an EToD generation unit therein, which is used to perform initialization of Δ phase 1.

Step 402, the master clock sends a master EToD frame to the slave clock through its own local timing interface.

As shown in fig. 5, the interface device at the master clock end further includes a local clock, and an HPPS generation unit, where the local clock is a local clock of the master clock, and can lock an external reference source such as GPS, 2Mps, 2MHz, and the like; the HPPS generation unit generates an HPPS pulse signal by taking a local clock of the master clock as a reference clock (in specific implementation, the HPPS pulse signal can be generated by a DDS frequency multiplier); the EToD generation unit sends a master EToD frame from the local timing interface of the master clock to the slave clock at a preset baud rate 9600 after 50 milliseconds (start time) of the rising edge of the HPPS by taking the rising edge of the HPPS as a quasi-time edge, so that the HPPS + EToD frame signal at the master clock end is transmitted to the slave clock end through the local timing interface of the master clock.

Step 403, after the transmission through the cable, the slave clock receives a master EToD frame sent by the master clock; during the reverse protection time, the following operations are performed:

1. performing CRC on the main EToD frame;

2. analyzing the main EToD frame to obtain offset;

3. a first phase offset Δ phase1 between the slave clock and the master clock is detected, encapsulating the first phase offset Δ phase1 into the slave EToD frame.

As shown in fig. 5, the interface device at the slave clock end includes an EToD parsing unit, a local clock, an HPPS generating unit, and an HPPS phase detecting unit, wherein,

the EToD analysis unit is used for carrying out CRC (cyclic redundancy check) on the EToD frame and analyzing offset from the EToD frame after the CRC is successful;

the HPPS generation unit generates an HPPS pulse signal by using a local clock of the slave clock as a reference clock (in a specific implementation, the HPPS pulse signal may be generated by a DDS frequency multiplier);

the HPPS phase detection unit is configured to detect an HPPS signal of a master clock at a receiving interface of a master EToD frame (that is, an intra-local timing interface of a slave clock), and obtain a first phase deviation Δ phase1 between the slave clock and the master clock by comparing a rising edge of the HPPS of the master clock with a rising edge of the HPPS of the slave clock (specifically, a phase detector may be used for comparison);

in addition, in the interface device at the slave clock end, the EToD generation unit is further configured to encapsulate Δ phase1 obtained by the HPPS phase detection unit into the slave EToD frame.

Step 404, the slave clock sends a slave EToD frame to the master clock through its own local timing interface.

As shown in fig. 5, in the interface device on the slave clock side after the inversion of the protection time, the EToD generation unit sends a slave EToD frame from the local timing interface of the slave clock to the master clock at a preset baud rate 9600 after 50 milliseconds (start time) of the rising edge of the HPPS, with the rising edge of the HPPS of the slave clock serving as a leading edge, so that the HPPS + EToD frame signal on the slave clock side is transmitted to the master clock side through the local timing interface of the slave clock.

Step 405, after the transmission through the cable, the master clock receives the slave EToD frame sent by the slave clock, and in the reverse protection time, the following operations are performed:

1. performing CRC check on the slave EToD frame;

2. resolving a first phase deviation Δ phase1 from the EToD frame;

3. detecting a second phase deviation delta phase2 between the master clock and the slave clock

4. And calculating the phase deviation offset between the slave clock and the master clock according to the first phase deviation delta phase1 and the second phase deviation delta phase2, and packaging the calculated offset into the master EToD frame.

As shown in fig. 5, the interface device on the master clock side further includes: an EToD analysis unit, an HPPS phase detection unit, and an offset calculation unit, wherein,

an EToD analysis unit for analyzing the received EToD frame to obtain delta phase 1;

the HPPS phase detection unit detects an HPPS signal of the slave clock at a receiving interface of the slave EToD frame (that is, an intra-local timing interface of the master clock), and obtains a second phase deviation Δ phase2 between the master clock and the slave clock by comparing a rising edge of the HPPS of the master clock with a rising edge of the HPPS of the slave clock (specifically, a phase detector may be used for comparison);

offset calculation unit: the phase offset between the master and slave clocks is calculated from Δ phase1 and Δ phase 2. Assuming that the fixed transmission delay caused by the transmission cable between the master clock and the slave clock is delay, Δ phase1 is delay + offset and Δ phase2 is delay-offset, so that it can be inferred that offset is (Δ phase1- Δ phase2) ÷ 2.

In the interface device on the master clock side, the EToD generating unit is also configured to encapsulate the offset calculated by the offset calculating unit in the master EToD frame.

Step 406, the master clock sends the master EToD frame to the slave clock through its own local timing interface.

As shown in fig. 5, in the interface device at the master clock end after the inversion protection time, the EToD generation unit sends a master EToD frame from the local timing interface of the master clock to the slave clock at a preset baud rate 9600 after 50 milliseconds (start time) of the rising edge of the HPPS, so that the HPPS + EToD frame signal at the master clock end is transmitted to the slave clock end through the local timing interface of the master clock.

Step 407, after the transmission through the cable, the slave clock receives the master EToD frame sent by the master clock, and in the reverse protection time, the following operations are performed:

1. performing CRC on the main EToD frame;

2. analyzing the main EToD frame to obtain offset;

3. a first phase deviation delta phase1 between the master clock and the slave clock is detected, and the first phase deviation delta phase1 is packaged into an EToD frame.

4. The phase adjustment is performed according to the offset.

5. Delta phase1 is encapsulated into the slave EToD frame.

As shown in fig. 5, the interface device at the slave clock end further includes a time synchronization unit (including a phase calibration unit and a clock control unit); wherein,

the EToD analysis unit is used for carrying out CRC (cyclic redundancy check) on the EToD frame and analyzing the offset from the EToD frame after the CRC is successful;

the phase calibration unit is used for performing phase adjustment according to the offset analyzed by the EToD analysis unit;

and the clock control unit is used for carrying out time adjustment on the local clock of the slave clock according to the first time information in the EToD frame.

The HPPS phase detection unit detects an HPPS signal of the master clock at a receiving interface of the master EToD frame (that is, an intra-local timing interface of the slave clock), and obtains a first phase deviation Δ phase1 between the master clock and the slave clock again by comparing a rising edge of the HPPS of the master clock with a rising edge of the HPPS of the slave clock (specifically, a phase detector may be used for comparison);

and an EToD generation unit for encapsulating the delta phase1 obtained again by the HPPS phase detection unit into an EToD frame.

Step 408 returns to step 404 to execute (the slave clock sends the slave EToD frame to the master clock through its own local timing interface again).

It can be seen that by repeatedly performing steps 404 and 408, the corrected offset value can be continuously updated, so that dynamic, ultra-high precision time synchronization can be achieved between the master clock and the slave clock through real-time interaction of the HPPS + EToD frame signals.

The half-duplex communication process between the master clock and the slave clock in the present invention is described in detail above, and in the communication process, the slave clock performs time synchronization with the master clock, and based on the time synchronization principle between the master clock and the slave clock in the communication process, the present invention provides a time synchronization method for intra-office distribution applied to the master clock and a time synchronization method for intra-office distribution applied to the slave clock, and the following description is made in detail with reference to fig. 6 and 7.

Referring to fig. 6, fig. 6 is a flowchart of a method for synchronizing time in local distribution according to an embodiment of the present invention, the method is applied to a master clock, as shown in fig. 6, and the method includes the following steps:

601, sending a master enhanced time of day EToD frame to a slave clock by an internal timing interface of the slave master clock;

step 602, receiving a slave EToD frame carrying a first phase deviation between a slave clock and a master clock returned by the slave clock at an intra-local timing interface of the master clock, and detecting and determining a second phase deviation between the master clock and the slave clock;

step 603, calculating a phase deviation between the slave clock and the master clock according to the first phase deviation and the second phase deviation, generating a master EToD frame carrying the phase deviation, and sending the master EToD frame from the local timing interface of the master clock to the slave clock, so that the slave clock performs time synchronization adjustment according to the master EToD frame.

In the method described in figure 6, the process,

taking the rising edge of half second pulse HPPS of the master clock as a quasi-time edge, and sending a master EToD frame from the local timing interface of the master clock to the slave clock at a preset baud rate after N milliseconds of the rising edge of the HPPS; wherein, N milliseconds is the preset starting time.

In the method described in figure 6, the process,

the slave EToD frame returned by the slave clock is sent from the local timing interface of the slave clock to the master clock at a preset baud rate after N milliseconds of the rising edge of the HPPS by taking the rising edge of half second pulse HPPS of the slave clock as a quasi-time edge;

the method for detecting and determining the second phase deviation between the master clock and the slave clock comprises the following steps: and detecting the HPPS signal of the slave clock by the local timing interface of the master clock, determining the HPPS rising edge of the slave clock according to the detected HPPS signal of the slave clock, and comparing the HPPS rising edge of the slave clock with the HPPS rising edge of the master clock to obtain a second phase deviation between the master clock and the slave clock.

In the method described in figure 6, the process,

the method for calculating the phase deviation between the slave clock and the master clock according to the first phase deviation and the second phase deviation comprises the following steps:

offset is (Δ phase1- Δ phase2) ÷ 2, where offset is the phase deviation between the slave and master clocks, Δ phase1 is the first phase deviation, and Δ phase2 is the second phase deviation.

Referring to fig. 7, fig. 7 is a flowchart of a method for time synchronization for local distribution according to an embodiment of the present invention, where the method is applied to a slave clock, as shown in fig. 7, and includes:

step 701, receiving a master enhanced time of day EToD frame sent by a master clock at an intra-office timing interface of a slave clock, and detecting and determining a first phase deviation between the slave clock and the master clock;

step 702, sending a slave EToD frame carrying a first phase deviation to a master clock from an intra-local timing interface of the slave clock, receiving a master EToD frame carrying a phase deviation between the slave clock and the master clock returned by the master clock, and performing time synchronization adjustment according to the master EToD frame returned by the master clock.

In the method shown in figure 7 of the drawings,

taking the rising edge of half second pulse HPPS of the slave clock as a quasi-time edge, and after the rising edge of the HPPS is N milliseconds, sending a slave EToD frame carrying a first phase deviation from a local timing interface of the slave clock to a master clock at a preset baud rate; wherein, N milliseconds is the preset starting time.

In the method shown in figure 7 of the drawings,

the main EToD frame sent by the main clock takes the rising edge of half second pulse HPPS of the main clock as a quasi-time edge, and is sent to a slave clock from a local timing interface of the main clock at a preset baud rate after N milliseconds of the rising edge of the HPPS;

the method for detecting and determining the first phase deviation between the slave clock and the master clock comprises the following steps: the method comprises the steps of detecting an HPPS signal of a master clock at a local timing interface of the slave clock, determining an HPPS rising edge of the master clock according to the detected HPPS signal of the master clock, and comparing the HPPS rising edge of the slave clock with the HPPS rising edge of the master clock to obtain a first phase deviation between the slave clock and the master clock.

In the method shown in figure 7 of the drawings,

the main EToD frame also carries time information sent by a main clock sending main EToD frame;

the method for performing time synchronization adjustment according to the main EToD frame returned by the main clock comprises the following steps: and performing phase adjustment according to the phase deviation between the slave clock and the master clock carried in the master EToD frame, and performing time adjustment according to the time information of sending the master EToD frame by the master clock carried in the master EToD frame and the current time information of the slave clock.

The present invention further provides a time synchronization apparatus (i.e. a master clock end interface apparatus) for intra-office distribution applied to a master clock and a time synchronization apparatus (i.e. a slave clock end interface apparatus) for intra-office distribution applied to a slave clock, which are described in detail below with reference to fig. 8 and 9.

Referring to fig. 8, fig. 8 is a schematic structural diagram of a time synchronization apparatus 800 for local distribution according to an embodiment of the present invention, which is applied to a master clock, and includes: EToD generation section 801, EToD analysis section 802, HPPS phase detection section 803, offset calculation section 804; wherein,

an EToD generating unit 801, configured to send a master enhanced time of day EToD frame from an intra-office timing interface of a master clock to a slave clock; a master EToD frame for generating a master EToD frame carrying the phase deviation between the slave clock and the master clock calculated by the offset calculation unit 804, and sending the master EToD frame from the local timing interface of the master clock to the slave clock, so that the slave clock performs time synchronization adjustment according to the master EToD frame;

an EToD analyzing unit 802, configured to, after the EToD generating unit 801 sends the master EToD frame to the slave clock from the local timing interface of the master clock, receive, at the local timing interface of the master clock, the slave EToD frame that is returned by the slave clock and carries the first phase offset between the master clock and the slave clock;

the HPPS phase detection unit 803 is configured to detect and determine a second phase deviation between the master clock and the slave clock when the EToD parsing unit 802 receives, from the local timing interface of the master clock, a slave EToD frame carrying a first phase deviation between the master clock and the slave clock and returned by the slave clock;

an offset calculation unit 804, configured to calculate a phase offset between the slave clock and the master clock according to the first phase offset and the second phase offset.

The apparatus shown in FIG. 8 further comprises an HPPS generation unit 805;

the HPPS generation unit 805 generates a half-second pulse HPPS with reference to a local clock of the master clock;

the EToD generating unit 801, taking a rising edge of an HPPS of a master clock as a quasi-time edge, and after N milliseconds of the rising edge of the HPPS, sending a master EToD frame from the local timing interface of the master clock to the slave clock at a preset baud rate; wherein, N milliseconds is the preset starting time.

In the arrangement shown in figure 8 of the drawings,

the HPPS phase detection unit 803, when detecting and determining the second phase deviation between the master clock and the slave clock, is configured to: and detecting the HPPS signal of the slave clock by the local timing interface of the master clock, determining the HPPS rising edge of the slave clock according to the detected HPPS signal of the slave clock, and comparing the HPPS rising edge of the slave clock with the HPPS rising edge of the master clock to obtain a second phase deviation between the master clock and the slave clock.

In the arrangement shown in figure 8 of the drawings,

the offset calculation unit 804, when calculating the phase deviation between the slave clock and the master clock according to the first phase deviation and the second phase deviation, is configured to:

Referring to fig. 9, fig. 9 is a schematic structural diagram of a time synchronization apparatus 900 for local distribution according to an embodiment of the present invention, which is applied to a slave clock, and as shown in fig. 9, the apparatus includes: an EToD analysis unit 901, an HPPS phase detection unit 902, an EToD generation unit 903, and a synchronization adjustment unit 904; wherein,

an EToD parsing unit 901, configured to receive, at an intra-local timing interface of a slave clock, a master enhanced time of day EToD frame sent by a master clock; the EToD generating unit 903 is configured to receive a master EToD frame carrying a phase offset between a slave clock and a master clock returned by the master clock after sending the slave EToD frame carrying a first phase offset from an intra-local timing interface of the slave clock to the master clock;

an HPPS phase detection unit 902, configured to detect and determine a first phase deviation between a slave clock and a master clock when an intra-local timing interface of the slave clock receives a master EToD frame sent by the master clock;

an EToD generating unit 903, configured to send a slave EToD frame carrying a first phase offset from an intra-local timing interface of a slave clock to a master clock;

and a synchronization adjusting unit 904, configured to perform time synchronization adjustment according to the master EToD frame returned by the master clock.

The apparatus shown in FIG. 9 further includes an HPPS generation unit 905;

the HPPS generation unit 905 generates a half-second pulse HPPS with reference to a local clock of the slave clock;

the EToD generating unit 903 is configured to send a slave EToD frame carrying a first phase offset from the local timing interface of the slave clock to the master clock at a preset baud rate N milliseconds after a rising edge of the HPPS, which is a quasi-time edge, of a half-second pulse HPPS of the slave clock; wherein, N milliseconds is the preset starting time.

In the arrangement shown in figure 9 of the drawings,

the HPPS phase detection unit 902, when detecting a first phase deviation between the slave clock and the master clock, is configured to: the method comprises the steps of detecting an HPPS signal of a master clock at a local timing interface of the slave clock, determining an HPPS rising edge of the master clock according to the detected HPPS signal of the master clock, and comparing the HPPS rising edge of the slave clock with the HPPS rising edge of the master clock to obtain a first phase deviation between the slave clock and the master clock.

In the arrangement shown in figure 9 of the drawings,

the synchronization adjustment unit 904 includes a phase calibration unit 9041 and a clock control unit 9042;

the phase calibration unit 9041 is configured to perform phase adjustment according to a phase deviation between a slave clock and a master clock carried in a master EToD frame;

the clock control unit 9042 is configured to perform time adjustment according to the time information of the master EToD frame and the current time information of the slave clock, where the time information of the master EToD frame is sent by the master clock carried in the master EToD frame.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A method for time synchronization of intra-office distribution applied to a master clock, the method comprising:

2. The method of claim 1,

3. The method of claim 2,

4. The method of claim 3,

5. A method for synchronizing time for intra-office distribution, applied to a slave clock, the method comprising:

6. The method of claim 5,

7. The method of claim 6,

8. The method of claim 7,

9. A time synchronizing apparatus for intra-office distribution, applied to a master clock, the apparatus comprising: an EToD generation unit, an EToD analysis unit, an HPPS phase detection unit and an offset calculation unit;

10. The apparatus of claim 9, further comprising an HPPS generation unit;

the HPPS generation unit generates half-second pulse HPPS by taking a local clock of the master clock as a reference;

the EToD generation unit takes the rising edge of the HPPS of the master clock as a quasi-time edge, and sends a master EToD frame to the slave clock from the local timing interface of the master clock at a preset baud rate after N milliseconds of the rising edge of the HPPS; wherein, N milliseconds is the preset starting time.

11. The apparatus of claim 10,

the HPPS phase detection unit, when detecting and determining a second phase deviation between the master clock and the slave clock, is configured to: and detecting the HPPS signal of the slave clock by the local timing interface of the master clock, determining the HPPS rising edge of the slave clock according to the detected HPPS signal of the slave clock, and comparing the HPPS rising edge of the slave clock with the HPPS rising edge of the master clock to obtain a second phase deviation between the master clock and the slave clock.

12. The apparatus of claim 11,

the offset calculation unit, when calculating the phase deviation between the slave clock and the master clock according to the first phase deviation and the second phase deviation, is configured to:

13. A time synchronizing device for intra-office distribution, applied to a slave clock, the device comprising: an EToD analysis unit, an HPPS phase detection unit, an EToD generation unit and a synchronization adjustment unit;

14. The apparatus of claim 13, further comprising an HPPS generation unit;

the HPPS generation unit is used for generating half-second pulse HPPS by taking a local clock of the slave clock as a reference;

the EToD generation unit takes the rising edge of half second pulse HPPS of the slave clock as a quasi-time edge, and sends a slave EToD frame carrying a first phase deviation from the local timing interface of the slave clock to the master clock at a preset baud rate after N milliseconds of the rising edge of the HPPS; wherein, N milliseconds is the preset starting time.

15. The apparatus of claim 14,

the HPPS phase detection unit, when detecting and determining a first phase deviation between the slave clock and the master clock, is configured to: the method comprises the steps of detecting an HPPS signal of a master clock at a local timing interface of the slave clock, determining an HPPS rising edge of the master clock according to the detected HPPS signal of the master clock, and comparing the HPPS rising edge of the slave clock with the HPPS rising edge of the master clock to obtain a first phase deviation between the slave clock and the master clock.

16. The apparatus of claim 15,

the synchronous adjusting unit comprises a phase calibration unit and a clock control unit;

the phase calibration unit is used for performing phase adjustment according to the phase deviation between the slave clock and the master clock carried in the master EToD frame;

and the clock control unit is used for carrying out time adjustment according to the time information of the master EToD frame and the current time information of the slave clock sent by the master clock carried in the master EToD frame.