CN107644816B - FinFET semiconductor device and method of manufacturing the same - Google Patents
FinFET semiconductor device and method of manufacturing the same Download PDFInfo
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Abstract
The invention provides a FinFET semiconductor device and a manufacturing method thereof, wherein after a first epitaxial layer is formed, a first dielectric layer is deposited on a semiconductor substrate to surround a first epitaxial layer and a second fin, then the first dielectric layer in a second area is etched to ensure that the height of the second fin is lower than that of a second side wall and the height of the first dielectric layer is higher than that of the second fin, then the second side walls on two sides of the second fin are etched in a transverse direction, the second side walls on two sides of the second fin are respectively etched outwards to the second side wall with the rest thickness, at the moment, because the first dielectric layer exists on two sides of the second side walls, the rest second side walls can be ensured not to collapse due to thickness reduction, then a second epitaxial layer is formed on the second fin and the second side walls, and the occurrence is prevented on the basis of increasing the volume of the epitaxial layer, finally, the purpose of improving the performance of the semiconductor device is achieved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a FinFET semiconductor device and a manufacturing method thereof.
Background
A Fin Field effect transistor (FinFET) is a new type of mosfet, and its structure is usually formed on a silicon-on-insulator (SOI) substrate, and includes a narrow and isolated semiconductor Fin structure (i.e., a vertical channel structure, also called a Fin) with gate structures formed on two sides of the Fin.
Referring specifically to fig. 1, a schematic diagram of a finfet structure in the prior art is shown. As shown in fig. 1, a conventional finfet includes: a semiconductor silicon-on-insulator substrate 1, a source 2, a drain 3, a fin-shaped strained silicon channel region 4, and a conductive gate 5 surrounding and on both sides of the fin-shaped strained silicon channel region 4. Wherein the fin-shaped strained silicon channel region 4 is typically extremely thin in thickness and protrudes with three controlled surfaces, controlled by the conductive gate 5. Therefore, the conductive gate 5 can easily form a fully depleted structure in the channel region, and completely cut off the conductive path of the channel. By adopting the FinFET structure, the device has smaller volume and higher performance.
However, as the size of the semiconductor device is continuously reduced, the source and drain regions are also reduced, so that the source and drain epitaxial layers are combined, and meanwhile, a large-size epitaxial layer is required to reduce contact resistance. In the prior art, an embedded SiP (silicon phosphorus) epitaxial layer is generally adopted to control the shape of the epitaxial layer and increase the volume of the epitaxial layer, but in the process of forming the SiP epitaxial layer, etching of a side wall is an important step, and the step easily causes collapse of the side wall.
Therefore, the problem to be solved by the skilled person is how to provide a sidewall with uniform thickness, especially to maintain the thickness uniformity of the sidewall after the sidewall etching.
Disclosure of Invention
The invention aims to provide a FinFET semiconductor device and a manufacturing method thereof, which can prevent side wall collapse caused by etching in the process of forming an epitaxial layer and improve the performance of the semiconductor device.
To achieve the above object, the present invention provides a method for manufacturing a FinFET semiconductor device, comprising the steps of:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a plurality of first areas and a plurality of second areas, the plurality of first areas and the plurality of second areas are sequentially arranged at intervals, first fins are formed on the first areas, and second fins are formed on the second areas;
performing a first deposition process on the semiconductor substrate, forming first side walls on the side walls and the top of the first fin, and forming second side walls on the side walls and the top of the second fin;
performing a first etching on the first fin and the first side wall until the first fin and the first side wall are at the height of the rest part;
performing an epitaxial process on the first fin, and forming a first epitaxial layer on the remaining first fin and the first side wall;
performing a second deposition process to form a first dielectric layer on the semiconductor substrate, wherein the first dielectric layer surrounds the first epitaxial layer, the second fin and the second side wall;
performing a second etching process on the first dielectric layer in the second region, so that the height of the second fin is lower than that of the second side wall, and the height of the first dielectric layer is higher than that of the second fin;
carrying out a third etching process on the second side walls on the two sides of the second fin, wherein the third etching process is transverse etching and is respectively carried out from the two sides of the second fin to the outside until the second side walls with the rest thickness are formed;
and performing an epitaxial process on the second fin to form a second epitaxial layer.
Optionally, the first region is a P-type semiconductor substrate, and the second region is an N-type semiconductor substrate.
Optionally, before the first deposition process is performed, a second dielectric layer is further formed on the semiconductor substrate, and the second dielectric layer covers the semiconductor substrate and the first fin and the second fin of a partial height; and a first oxide layer is formed on sidewalls and tops of the first and second fins.
Optionally, the second etching process includes:
etching the first dielectric layer of the second area until the top of the second side wall is exposed;
etching the exposed second side wall until the second fin is exposed;
etching the exposed second fin to the second fin with the remaining part of the height.
Optionally, the exposed second fin is etched, and the height of the etched second fin is 10nm to 30 nm.
Optionally, before etching the first dielectric layer in the second region, the method further includes: and forming patterned photoresist on the first dielectric layer.
Optionally, after etching the exposed second fin, the method further includes: and removing the patterned photoresist.
Optionally, the patterned photoresist is removed by ashing and wet cleaning, and the second fin is reoxidized while the photoresist is removed, so that a third oxide layer is formed on the upper surface of the second fin.
Optionally, in the first deposition process, the thickness of the formed second sidewall is 40nm to 80 nm.
Optionally, after the performing the epitaxial process on the first fin and before performing the second deposition process, the method further includes: and re-oxidizing the first epitaxial layer to form a second oxide layer on the surface of the first epitaxial layer.
Optionally, after the reoxidizing the first epitaxial layer and before the performing the second deposition process, the method further includes: and carrying out a third deposition process to increase the thickness of the second side wall.
Optionally, the thickness of the second sidewall is increased to 60nm to 120 nm.
Optionally, in the third etching process, the remaining thickness of the second sidewall is 1nm to 4 nm.
Optionally, after forming the second epitaxial layer, the method further includes: and reoxidizing the second epitaxial layer, and forming a fourth oxide layer on the surface of the second epitaxial layer.
Optionally, after the reoxidizing the second epitaxial layer, the method further includes: and carrying out a fourth deposition process, and forming a third dielectric layer on the semiconductor substrate, wherein the third dielectric layer surrounds the second epitaxial layer.
Optionally, the first epitaxial layer is a silicon germanium epitaxial layer, and the second epitaxial layer is a silicon phosphorus epitaxial layer.
Optionally, the longitudinal sections of the first epitaxial layer and the second epitaxial layer are both polygonal.
Accordingly, the present invention also provides a FinFET semiconductor device comprising:
the semiconductor substrate comprises a plurality of first regions and second regions which are sequentially arranged at intervals;
a first fin formed on the semiconductor substrate of the first region, a first epitaxial layer formed on the first fin;
a second fin formed on the semiconductor substrate in the second region, wherein a second sidewall is formed on a sidewall of the second fin, the second sidewall has a height higher than that of the second fin, and a second epitaxial layer is formed on the second fin and the sidewall thereof;
and a dielectric layer surrounding the first fin, the second fin, and the first epitaxial layer and the second epitaxial layer.
Optionally, the first epitaxial layer is a silicon germanium epitaxial layer, and the second epitaxial layer is a silicon phosphorus epitaxial layer.
Optionally, the longitudinal sections of the first epitaxial layer and the second epitaxial layer are both polygonal.
Compared with the prior art, the FinFET semiconductor device and the manufacturing method thereof have the following advantages:
after a first epitaxial layer is formed, depositing a first dielectric layer on a semiconductor substrate to surround the first epitaxial layer, a second fin and a second side wall, etching the first dielectric layer in a second area to enable the height of the second fin to be lower than that of the second side wall and the height of the first dielectric layer to be higher than that of the second fin, then etching the second side walls on two sides of the second fin, wherein the etching is transverse etching, the second side walls on two sides of the second fin are respectively etched outwards to the second side wall with the rest thickness, at the moment, because the first dielectric layer exists on two sides of the second side walls, the rest second side walls can be guaranteed not to collapse due to the reduction of the thickness, and then forming a second epitaxial layer on the second fin and the second side walls, the collapse is prevented on the basis of increasing the volume of the epitaxial layer, and finally the purpose of improving the performance of the semiconductor device is achieved.
Drawings
Fig. 1 is a schematic diagram of a finfet structure in the prior art.
Fig. 2 is a flow chart illustrating a method of fabricating a FinFET semiconductor device according to an embodiment of the present invention.
Fig. 3 to 16 are schematic structural diagrams of steps of a method for manufacturing a FinFET semiconductor device according to an embodiment of the present invention.
Detailed Description
In order to make the contents of the present invention more clearly understood, the contents of the present invention will be further described with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.
The present invention is described in detail with reference to the drawings, and for convenience of explanation, the drawings are not enlarged partially according to the general scale, and should not be construed as limiting the present invention.
The invention provides a manufacturing method of a FinFET semiconductor device, which comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a plurality of first areas and a plurality of second areas, the plurality of first areas and the plurality of second areas are sequentially arranged at intervals, first fins are formed on the first areas, and second fins are formed on the second areas; performing a first deposition process on the semiconductor substrate, forming first side walls on the side walls and the top of the first fin, and forming second side walls on the side walls and the top of the second fin; performing a first etching on the first fin and the first side wall until the first fin and the first side wall are at the height of the rest part; performing an epitaxial process on the first fin, and forming a first epitaxial layer on the remaining first fin and the first side wall; performing a second deposition process to form a first dielectric layer on the semiconductor substrate, wherein the first dielectric layer surrounds the first epitaxial layer, the second fin and the second side wall; performing a second etching process on the first dielectric layer in the second region, so that the height of the second fin is lower than that of the second side wall, and the height of the first dielectric layer is higher than that of the second fin; carrying out a third etching process on the second side walls on the two sides of the second fin, wherein the third etching process is transverse etching and is respectively carried out from the two sides of the second fin to the outside until the second side walls with the rest thickness are formed; and performing an epitaxial process on the second fin to form a second epitaxial layer.
After a first epitaxial layer is formed, depositing a first dielectric layer on a semiconductor substrate to surround the first epitaxial layer, a second fin and a second side wall, etching the first dielectric layer in a second area to enable the height of the second fin to be lower than that of the second side wall and the height of the first dielectric layer to be higher than that of the second fin, then etching the second side walls on two sides of the second fin, wherein the etching is transverse etching, the second side walls on two sides of the second fin are respectively etched outwards to the second side wall with the rest thickness, at the moment, because the first dielectric layer exists on two sides of the second side walls, the rest second side walls can be guaranteed not to collapse due to the reduction of the thickness, and then forming a second epitaxial layer on the second fin and the second side walls, the collapse is prevented on the basis of increasing the volume of the epitaxial layer, and finally the purpose of improving the performance of the semiconductor device is achieved.
Fig. 2 is a flowchart illustrating a method for fabricating a FinFET semiconductor device according to an embodiment of the present invention. As shown in fig. 2, the present invention provides a method of manufacturing a FinFET semiconductor device, comprising the steps of:
step S01: providing a semiconductor substrate, wherein the semiconductor substrate is divided into a plurality of first areas and second areas, the plurality of first areas and the plurality of second areas are sequentially arranged at intervals, first fins are formed on the first areas, and second fins are formed on the second areas;
step S02: performing a first deposition process on the semiconductor substrate, forming first side walls on the side walls and the top of the first fin, and forming second side walls on the side walls and the top of the second fin;
step S03: performing a first etching on the first fin and the first side wall until the first fin and the first side wall are at the height of the rest part;
step S04: performing an epitaxial process on the first fin, and forming a first epitaxial layer on the remaining first fin and the first side wall;
step S05: performing a second deposition process to form a first dielectric layer on the semiconductor substrate, wherein the first dielectric layer surrounds the first epitaxial layer, the second fin and the second side wall;
step S06: performing a second etching process on the first dielectric layer in the second region, so that the height of the second fin is lower than that of the second side wall, and the height of the first dielectric layer is higher than that of the second fin;
step S07: carrying out a third etching process on the second side walls on the two sides of the second fin, wherein the third etching process is transverse etching and is respectively carried out from the two sides of the second fin to the outside until the second side walls with the rest thickness are formed;
step S08: and performing an epitaxial process on the second fin to form a second epitaxial layer.
Fig. 3 to 16 are schematic structural diagrams of steps of a method for manufacturing a FinFET semiconductor device according to an embodiment of the present invention, and please refer to fig. 2, which is combined with fig. 3 to 16 to describe in detail the method for manufacturing a FinFET semiconductor device according to the present invention:
as shown in fig. 3, in step S01, a semiconductor substrate 100 is provided, the semiconductor substrate is divided into a plurality of first regions 10 and second regions 20, the plurality of first regions 10 and the plurality of second regions 20 are sequentially arranged at intervals, and a first fin 11 is formed on the first region 10 and a second fin 21 is formed on the second region 20.
In this embodiment, the first region 10 is a P-type semiconductor substrate, and the second region 20 is an N-type semiconductor substrate. A second dielectric layer 101 is further formed on the semiconductor substrate 100, and the second dielectric layer 101 covers the semiconductor substrate 100 and the first fin 11 and the second fin 21 at a part of the height; a first oxide layer 102 is formed on sidewalls and tops of the first fin 11 and the second fin 21. It should be noted that, in this embodiment, only one first region 10 and one second region 20 are listed, and in other embodiments, the number of the first regions 10 and the second regions 20 may be determined by actual situations. The first fin 11 and the second fin 21 are made of silicon or other materials known to those skilled in the art.
In step S02, a first deposition process is performed on the semiconductor substrate 100 to form a material layer 103 on the semiconductor substrate, wherein the material layer formed on the sidewalls and the top of the first fin 11 forms a first sidewall 103a, and the material layer formed on the sidewalls and the top of the second fin 21 forms a second sidewall 103b, as shown in fig. 4. In this embodiment, the thickness of the second sidewall 103b is 40nm to 80nm, for example, the thickness of the second sidewall 103b is 40nm, 50nm, 60nm, 70nm, or 80 nm.
In step S03, a first etching is performed on the first fin 11 and the first sidewall 103a until the first fin 11 and the first sidewall 103a are at the remaining height, as shown in fig. 5. Depositing a photoresist on the second dielectric layer 101, patterning to form a patterned photoresist 104 exposing the first region 10, and then performing a first etching on the first fin 11 and the first sidewall 103a with the patterned photoresist 104 as a mask until the remaining height of the first fin 11 and the first sidewall 103a is reached.
In step S04, an epitaxial process is performed on the first fin 11, and a first epitaxial layer 105 is formed on the remaining first fin 11 and the first sidewall 103a, as shown in fig. 6. Preferably, the first epitaxial layer 105 is a silicon germanium (SiGe) epitaxial layer; preferably, the longitudinal section of the first epitaxial layer 105 is polygonal, and the longitudinal section of the first epitaxial layer 105 formed in this step is not limited to a certain shape, and may be other irregular polygonal shapes.
As shown in fig. 7, after the first epitaxial layer 105 is formed, the method further includes: the first epitaxial layer 105 is re-oxidized to form an oxide layer on the surface of the first epitaxial layer 105, and the material of the oxide layer formed in this step is the same as that of the first oxide layer 102 formed in step S01, so in fig. 7, the first oxide layer 102 and the oxide layer formed in this step are not distinguished in the first region, and are collectively referred to as the second oxide layer 106.
Then, a third deposition process is performed to increase the thickness of the second sidewall 103b, in this embodiment, the increased thickness is 60nm to 120nm, for example, the increased thickness is 60nm, 80nm, 100nm or 120 nm. It should be noted that the first deposition process and the third deposition process have the same process conditions, and the material of the second sidewall formed on the second fin 21 is also the same, and the difference is only in the thickness of the sidewall, so for clarity of the subsequent steps, in fig. 7, in the second region, the second sidewall 103b formed by the first deposition process and the second sidewall formed by the third deposition process are not distinguished, and are collectively labeled as the second sidewall 108. The second sidewall 108 is generally made of nitride, and preferably, in this embodiment, the second sidewall 108 is made of silicon nitride.
A third deposition process is performed, while the thickness of the second sidewall on the second fin 21 is increased, sidewalls are formed on the surface of the second dielectric layer 101 and the surface of the second oxide layer 106 in the first region 10, and similarly, the sidewall 103a of the first fin 11 and the sidewall formed in this step are collectively labeled as a first sidewall 107.
In step S05, a second deposition process is performed to form a first dielectric layer 109 on the semiconductor substrate 100, wherein the first dielectric layer 109 surrounds the first epitaxial layer 105, the second fin 21 and the second sidewall 108, as shown in fig. 8. The first dielectric layer 109 is made of the same material as the second dielectric layer 101 formed in step S01, and is preferably an oxide layer, and after the first dielectric layer 109 is formed, planarization treatment is performed, for example, by using a Chemical Mechanical Polishing (CMP) method.
In step S06, a second etching process is performed on the first dielectric layer 109 in the second region, so that the height of the second fin 21 is lower than the height of the second fin sidewall 108, and the height of the first dielectric layer 109 is higher than the height of the second fin 21, as shown in fig. 11.
The second etching process specifically comprises the following steps:
first, the first dielectric layer 109 of the second region 20 is etched until the top of the second sidewall spacers 108 are exposed. Specifically, a photoresist is deposited on the first dielectric layer 109, and is patterned to form a patterned photoresist 110 exposing the second region 20, and then the patterned photoresist 110 is used as a mask to etch the first dielectric layer 109 in the second region 20 until the top of the second sidewall 108 is exposed, so as to form the structure shown in fig. 9.
The exposed second sidewalls 108 are then etched to expose the second fins 21, as shown in fig. 10. In the present embodiment, the first oxide layer 102 is formed on the second fin 21, so that the etching is stopped until the first oxide layer 102 on the top of the second fin 21 is exposed, and at this time, the upper surface of the second region 20 is a flat surface.
Finally, the exposed second fin 21 is etched to the remaining height of the second fin 21, so as to form the structure shown in fig. 11. In this embodiment, the height of the etched second fin is 10nm to 30nm, for example, 10nm, 15nm, 20nm, 25nm, and 30nm, and at this time, the height of the second fin 21 is lower than the height of the second sidewall 208, although the first dielectric layer 109 is inevitably partially etched in the process of etching the second fin 21, the height of the first dielectric layer 109 is finally higher than the height of the second fin 21, so as to ensure that the collapse of the second sidewall 108 is avoided in the subsequent etching and epitaxial processes of the second sidewall 108, and the volume of the epitaxial layer can be increased.
After etching the exposed second fin 21, further comprising: in this embodiment, the patterned photoresist 110 is removed by ashing and wet cleaning, and the second fin 21 is re-oxidized during the photoresist removal process, and a third oxide layer is formed on the upper surface of the second fin 21, as shown in fig. 12, since in step S01, the first oxide layer 102 is formed on the sidewall of the second fin 21, and the first oxide layer 102 and the third oxide layer formed in this step are made of the same material, in fig. 12, the oxide layers on the upper surface and the sidewall of the second fin 12 are both marked as the third oxide layer 111.
In step S07, a third etching process is performed on the second sidewalls 108, where the third etching process is a lateral etching, and the third etching process is performed from two sides of the second fin 21 to the outside respectively until the second sidewalls 108 with the remaining thickness are formed, as shown in fig. 13.
Since the first dielectric layer 109 is surrounded on both sides of the second sidewall 108, the second sidewall 108 is prevented from collapsing during the third etching process. In this embodiment, the second sidewall 108 is made of silicon nitride, the second sidewall 108 may be etched by a wet etching method, and the etching solution is preferably phosphoric acid (H)3PO4) The remaining thickness of the second sidewall 108 is 1nm to 4nm, i.e. the thickness of the second sidewalls on both sides of the second fin 21 is 1nm to 4nm, for example, 1nm, 2nm, 3nm or 4 nm.
In step S08, an epitaxial process is performed on the second fin 21 to form a second epitaxial layer 112, as shown in fig. 14. Specifically, the surface of the semiconductor device formed in step S07 is first pre-cleaned to remove impurities remaining from the third etching, and the third oxide layer 111 on the top of the second fin 21 is removed, and then an epitaxial process is performed to form the second epitaxial layer 112. Through steps S06 and S07, the volume of the second epitaxial layer 112 can be increased. Preferably, the second epitaxial layer 112 is a silicon-phosphorus epitaxial layer; preferably, the longitudinal section of the second epitaxial layer 112 is a polygon, and the longitudinal section of the second epitaxial layer 112 formed in this step is not limited to a certain shape, and may be other irregular polygon shapes.
Finally, the method also comprises the following steps: re-oxidizing the second epitaxial layer 112, forming a fourth oxide layer 113 on the surface of the second epitaxial layer 112, as shown in fig. 15, and finally performing a fourth deposition process to form a third dielectric layer, where the third dielectric layer surrounds the second epitaxial layer 112, so as to form the structure shown in fig. 16. In this embodiment, since the third dielectric layer formed in this step is made of the same material as the first dielectric layer 109, in fig. 16, the third dielectric layer formed in this step and the first dielectric layer 109 are collectively denoted by a third dielectric layer 114, and the material of the third dielectric layer 114 is preferably an oxide. After the fourth deposition process, a planarization process, such as a Chemical Mechanical Polishing (CMP) process, is required.
After a first epitaxial layer is formed, depositing a first dielectric layer on a semiconductor substrate to surround the first epitaxial layer, a second fin and a second side wall, etching the first dielectric layer in a second area to enable the height of the second fin to be lower than that of the second side wall and the height of the first dielectric layer to be higher than that of the second fin, then etching the second side walls on two sides of the second fin, wherein the etching is transverse etching, the second side walls on two sides of the second fin are respectively etched outwards to the second side wall with the rest thickness, at the moment, because the first dielectric layer exists on two sides of the second side walls, the rest second side walls can be guaranteed not to collapse due to the reduction of the thickness, and then forming a second epitaxial layer on the second fin and the second side walls, the collapse is prevented on the basis of increasing the volume of the epitaxial layer, and finally the purpose of improving the performance of the semiconductor device is achieved.
Accordingly, the present invention also provides a FinFET semiconductor device manufactured by the above method for manufacturing a FinFET semiconductor device, and referring to fig. 16, the present invention provides a FinFET semiconductor device, comprising:
the semiconductor device comprises a semiconductor substrate 100, wherein the semiconductor substrate 100 comprises a plurality of first regions 10 and second regions 20, and the plurality of first regions 10 and the plurality of second regions 20 are sequentially arranged at intervals; only one first area 10 and one second area 20 are shown in fig. 16, in other embodiments, the number of the first areas 10 and the second areas 20 may be determined by actual conditions;
a first fin 11 formed on the semiconductor substrate 100 of the first region 10, a first epitaxial layer 105 being formed on the first fin 11;
a second fin 21 formed on the semiconductor substrate 100 in the second region 20, wherein a second sidewall 108 is formed on a sidewall of the second fin 21, and a height of the second sidewall 108 is higher than a height of the second fin 21, and a second epitaxial layer 112 is formed on the second fin 21 and the sidewall 108 thereof;
and a third dielectric layer 114 surrounding the first fin 11, the second fin 21, and the first epitaxial layer 105 and the second epitaxial layer 111.
Preferably, a second dielectric layer 101 is further formed on the semiconductor substrate 100, a second oxide layer 106 and a sidewall 107 are formed on the first epitaxial layer 105, and a fourth oxide layer 113 is formed on the second epitaxial layer 112. Preferably, the first epitaxial layer 105 is a silicon germanium epitaxial layer, and the second epitaxial layer 111 is a silicon phosphorus epitaxial layer; preferably, the longitudinal cross sections of the first epitaxial layer 105 and the second epitaxial layer 111 are polygonal, and in this embodiment, the longitudinal cross section of the first epitaxial layer 105 and the second epitaxial layer 112 is not limited to a certain shape, and may be other irregular polygonal shapes.
In summary, after the first epitaxial layer is formed, the first dielectric layer is deposited on the semiconductor substrate to surround the first epitaxial layer, the second fin and the second side wall, then the first dielectric layer in the second region is etched to make the height of the second fin lower than the height of the second side wall and make the height of the first dielectric layer higher than the height of the second fin, then the second side walls on both sides of the second fin are etched, the etching is a lateral etching, the second side walls on both sides of the second fin are respectively etched to the outside from the second side walls on both sides of the second fin to the second side wall with the remaining thickness, at this time, because the first dielectric layer exists on both sides of the second side wall, the remaining second side wall can be ensured not to collapse due to the reduction of the thickness, and then the second epitaxial layer is formed on the second fin and the second side wall, the collapse is prevented on the basis of increasing the volume of the epitaxial layer, and finally the purpose of improving the performance of the semiconductor device is achieved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (17)
1. A method of manufacturing a FinFET semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a plurality of first areas and a plurality of second areas, the plurality of first areas and the plurality of second areas are sequentially arranged at intervals, first fins are formed on the first areas, and second fins are formed on the second areas;
performing a first deposition process on the semiconductor substrate, forming first side walls on the side walls and the top of the first fin, and forming second side walls on the side walls and the top of the second fin;
performing a first etching on the first fin and the first side wall until the first fin and the first side wall are at the height of the rest part;
performing an epitaxial process on the first fin, and forming a first epitaxial layer on the remaining first fin and the first side wall;
performing a second deposition process to form a first dielectric layer on the semiconductor substrate, wherein the first dielectric layer surrounds the first epitaxial layer, the second fin and the second side wall;
performing a second etching process on the first dielectric layer in the second region, so that the height of the second fin is lower than that of the second side wall, and the height of the first dielectric layer is higher than that of the second fin;
carrying out a third etching process on the second side walls on the two sides of the second fin, wherein the third etching process is transverse etching and is respectively carried out from the two sides of the second fin to the outside until the second side walls with the rest thickness are formed;
and performing an epitaxial process on the second fin to form a second epitaxial layer.
2. The method of fabricating a FinFET semiconductor device of claim 1, wherein the first region is a P-type semiconductor substrate and the second region is an N-type semiconductor substrate.
3. The method of manufacturing a FinFET semiconductor device of claim 2, wherein a second dielectric layer is further formed on the semiconductor substrate prior to the first deposition process, the second dielectric layer covering the semiconductor substrate and the first and second fins at least partially in height; and a first oxide layer is formed on sidewalls and tops of the first and second fins.
4. The method of manufacturing a FinFET semiconductor device of claim 1, wherein the second etching process comprises:
etching the first dielectric layer of the second area until the top of the second side wall is exposed;
etching the exposed second side wall until the second fin is exposed;
etching the exposed second fin to the second fin with the remaining part of the height.
5. The method of fabricating the FinFET semiconductor device of claim 4, wherein the exposed second fin is etched away to a height of 10nm to 30 nm.
6. The method of manufacturing a FinFET semiconductor device of claim 4, further comprising, prior to etching the first dielectric layer in the second region: and forming patterned photoresist on the first dielectric layer.
7. The method of fabricating the FinFET semiconductor device of claim 6, further comprising, after etching the exposed second fin: and removing the patterned photoresist.
8. The method of fabricating the FinFET semiconductor device of claim 7, wherein the patterned photoresist is removed by ashing and wet cleaning, wherein the second fin is reoxidized while the photoresist is removed, and wherein a third oxide layer is formed on the top surface of the second fin.
9. The method of manufacturing the FinFET semiconductor device of claim 1, wherein the second sidewall spacers are formed to a thickness of 40nm to 80nm in the first deposition process.
10. The method of fabricating the FinFET semiconductor device of claim 1, further comprising, after performing the epitaxial process on the first fin and before performing the second deposition process: and re-oxidizing the first epitaxial layer to form a second oxide layer on the surface of the first epitaxial layer.
11. The method of fabricating a FinFET semiconductor device of claim 10, further comprising, after reoxidizing the first epitaxial layer, prior to performing a second deposition process: and carrying out a third deposition process to increase the thickness of the second side wall.
12. The method of fabricating the FinFET semiconductor device of claim 11, wherein the second sidewalls are increased to a thickness of 60nm to 120 nm.
13. The method of manufacturing a FinFET semiconductor device of claim 1, wherein in the third etching process, the remaining thickness of the second sidewalls is all 1nm to 4 nm.
14. The method of fabricating a FinFET semiconductor device of claim 1, further comprising, after forming the second epitaxial layer: and reoxidizing the second epitaxial layer, and forming a fourth oxide layer on the surface of the second epitaxial layer.
15. The method of fabricating a FinFET semiconductor device of claim 12, further comprising, after reoxidizing the second epitaxial layer: and carrying out a fourth deposition process, and forming a third dielectric layer on the semiconductor substrate, wherein the third dielectric layer surrounds the second epitaxial layer.
16. The method of manufacturing the FinFET semiconductor device of any one of claims 1-15, wherein the first epitaxial layer is a silicon germanium epitaxial layer and the second epitaxial layer is a silicon phosphorus epitaxial layer.
17. The method of manufacturing a FinFET semiconductor device according to any of claims 1 to 15, wherein the first epitaxial layer and the second epitaxial layer are both polygonal in longitudinal cross section.
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