CN107643987B - Method for reducing DRAM (dynamic random Access memory) usage in solid state disk and solid state disk using same - Google Patents
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Abstract
The invention provides a method for reducing DRAM (dynamic random access memory) usage in a solid state disk and the solid state disk using the same, wherein the method comprises the following steps: providing a reference table in a DRAM of the solid state disk; providing a logic corresponding entity address table; receiving a command from a host of the solid state disk, and accessing a target logic address of the non-volatile memory unit; confirming whether the entity address is stored in a logic corresponding entity address table; using the mapping data in the subgroup to execute the command, or copying a corresponding subgroup of the mapping data containing the target logical address from the mapping table to the DRAM via the reference table; and adding the target physical address of the DRAM to the logical corresponding physical address table, wherein the mapping data of the target logical address is stored in the target physical address, so that the target logical address can correspond to the target physical address. It is not necessary to copy the entire mapping table from the flash memory chip to the DRAM, and thus the capacity requirement of the DRAM can be reduced.
Description
Technical Field
The present invention relates to the field of solid state disks, and in particular, to a method for reducing the usage of Dynamic Random Access Memory (DRAM) in a solid state disk and a solid state disk using the same.
Background
Recently, flash memory is widely used for storing digitized data, and has many application areas: the flash memory chips can be assembled to form a solid state disk as a main component of a notebook computer or be made into a portable storage device, such as a U disk; a single flash memory chip can also be packaged to form a micro SD memory card, and the micro SD memory card is inserted into the smart phone to record data. Taking the solid state disk as an example, compared with the conventional hard disk, the solid state disk has the advantages of shock resistance, small size, low heat dissipation, fast reading and writing, and the like. Although conventional hard disks have a higher bit cost ratio than solid state disks, the difference between them is shrinking. Solid state disks are replacing traditional hard disks and become the mainstream of storage devices.
In a solid state drive or other similar storage device, mapping tables are used to achieve read/write characteristics. Typically, the mapping tables are very large and either the entire mapping table or a portion of the mapping table is used to perform the read or write tasks. Thus, it is actually necessary to store the entire or partial mapping table in a DRAM to respond to the read/write command quickly. Before the DRAM is initialized to download the whole mapping table or part of the mapping table, the whole mapping table is stored in the flash memory units (pages or blocks) of the solid state disk. Solid state disk controllers are typically designed and manufactured with DRAM having a storage capacity of about 1/1000 that is the full flash memory in a solid state disk. For example, if the capacity of the solid state disk is 512GB, the DRAM of the solid state disk controller should be no less than 512 MB. In the past, the capacity of a solid state disk is not large, and the required DRAM is not large. The cost of DRAM is not significant. However, as the capacity of solid state drives increases rapidly, the cost of DRAM becomes an issue.
Disclosure of Invention
In view of the above, it is necessary to provide a method for reducing the use of DRAM in a solid state disk and a solid state disk using the same, which can reduce the capacity requirement of DRAM, thereby reducing the cost, in order to solve the problem that the DRAM is high in cost as the capacity of the solid state disk is increased conventionally. In order to solve the foregoing problems, the present invention provides a method for reducing DRAM usage in a solid state disk, the method comprising the steps of:
A. providing a reference table in a DRAM of a solid state disk, wherein the reference table has physical addresses of a plurality of subgroups of mapping tables in non-volatile memory units of the solid state disk, wherein the mapping tables have mapping data, each mapping data for mapping a logical address to a corresponding physical address of a non-volatile memory unit of the solid state disk; each subgroup includes a portion of all the mapping data;
B. providing a logical corresponding physical address table in a DRAM of the solid state disk, wherein the logical corresponding physical address table stores a plurality of logical addresses and physical addresses of the DRAM, wherein each physical address of the DRAM corresponds to one logical address and points to a subgroup of the mapping data having the corresponding logical address;
C. receiving a command, wherein the command is from a host of the solid state disk and is used for accessing a target logic address of the non-volatile memory unit;
D. confirming whether the physical address of the DRAM corresponding to the target logical address is stored in the logical corresponding physical address table;
E. if the result of step D is yes, using the mapping data in the subgroup to execute the command, or if the result of step D is no, copying the corresponding subgroup of mapping data containing the target logical address from the mapping table to the DRAM through the reference table to execute the command; and
F. and adding a target physical address of the DRAM to the logical corresponding physical address table, wherein the mapping data of the target logical address is stored in the target physical address so that the target logical address can correspond to the target physical address.
In one embodiment, step E1 is further included before step F:
e1, when the logical corresponding physical address table reaches the maximum storage capacity, removing the target logical address with the lowest priority in all the target logical addresses from the logical corresponding physical address table.
In one embodiment, the priority is set by ordering hit rates of temporary data accesses, ordering recent access records, or ordering discretionary weighting.
In one embodiment, step B1 is further included after step B:
b1, providing subgroup address to logical address table in the DRAM of the solid state disk, wherein the subgroup address to logical address table stores logical addresses and physical addresses of the DRAM for the mapping data of the corresponding subgroup.
In one embodiment, if the command is write, step F is preceded by step E2:
e2, programming data corresponding to the physical address in the nonvolatile memory cell according to the subgroup address to logical address table.
In one embodiment, the nonvolatile memory unit is a flash memory chip in the solid state disk.
In one embodiment, the flash memory chip is a NAND flash memory chip, a NOR flash memory chip, or a charge extraction flash memory chip.
The invention also provides a solid state disk using the method, which comprises the following steps:
a plurality of non-volatile memory cells;
a DRAM; and
a controller for creating a reference table in the DRAM, wherein the reference table has physical addresses of a plurality of subgroups of mapping tables in the non-volatile memory unit, wherein the mapping tables have mapping data, each mapping data for mapping a logical address to a corresponding physical address of the non-volatile memory unit; each subgroup includes a portion of all the mapping data;
creating a logical-to-physical address table in the DRAM, wherein the logical-to-physical address table stores a plurality of logical addresses and physical addresses of the DRAM, wherein each physical address of the DRAM corresponds to one logical address and points to a subgroup storing mapping data of the corresponding logical address;
receiving a command, wherein the command is from a host of the solid state disk and is used for accessing a target logic address of the non-volatile memory unit;
confirming whether the physical address of the DRAM corresponding to the target logical address is stored in the logical corresponding physical address table;
if the result of the confirmation is yes, using the mapping data in the subgroup to execute the command;
if the result of the confirmation is negative, copying a corresponding subgroup of mapping data containing the target logical address from the mapping table to the DRAM through the reference table to execute the command; and
and adding a target physical address of the DRAM to the logical corresponding physical address table, wherein the mapping data of the target logical address is stored in the target physical address so that the target logical address can correspond to the target physical address.
In one embodiment, the controller further removes the target logical address having the lowest priority among all the target logical addresses from the logically corresponding physical address table when the logically corresponding physical address table reaches the maximum storage capacity.
In one embodiment, the priority is set by ordering hit rates of temporary data accesses, ordering recent access records, or ordering discretionary weighting.
In one embodiment, the controller is further configured to create a subgroup address to logical address table in the DRAM, wherein the subgroup address to logical address table stores logical addresses and physical addresses of the DRAM for mapping data of corresponding subgroups.
In one embodiment, if the command is a write command, the controller is further configured to program data corresponding to a physical address in the non-volatile memory cells according to the subgroup address to logical address table.
In one embodiment, the nonvolatile memory unit is a flash memory chip in the solid state disk.
In one embodiment, the flash memory chip is a NAND flash memory chip, a NOR flash memory chip, or a charge extraction flash memory chip.
The beneficial effects of the invention at least comprise:
compared with the traditional solid state disk, the method for reducing the use of the DRAM in the solid state disk and the solid state disk using the same do not need to copy the whole mapping table from the flash memory chip to the DRAM of the solid state disk. Thus, the capacity requirements of the DRAM may be reduced.
Drawings
FIG. 1 is a schematic structural diagram of a solid state disk in one embodiment;
FIG. 2 is a data structure diagram of a DRAM in one embodiment;
FIG. 3 is a flow diagram illustrating a method for reducing DRAM usage in a solid state drive, in one embodiment.
Detailed Description
The present invention will be described more specifically with reference to the following embodiments.
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the following describes in detail a method for reducing DRAM usage in a solid state disk and a solid state disk using the same, with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, a solid state disk 10 is provided in one embodiment, the solid state disk 10 having reduced DRAM usage. The solid state disk 10 is used for storing data for access (writing and reading). Therefore, the solid state disk 10 may have a plurality of nonvolatile memory cells. The number of the non-volatile memory units is determined by the capacity of the solid state disk 10, and the storage capacity of each non-volatile memory unit is not limited. In fact, the non-volatile memory unit can be a flash memory chip. Preferably, the flash memory chip can be a NAND flash memory chip, a NOR flash memory chip, or a charge extraction flash memory chip, but the invention is not limited thereto.
In this embodiment, the solid state disk 10 includes 8 flash memory chips (a first flash memory chip 301, a second flash memory chip 302, a third flash memory chip 303, a fourth flash memory chip 304, a fifth flash memory chip 305, a sixth flash memory chip 306, a seventh flash memory chip 307, and an eighth flash memory chip 308), the DRAM200, and the controller 100. The controller 100 has many functions. According to the present invention, the main function is to create a logical mapping table 206 (the logical mapping table stores a plurality of logical addresses and the physical address of the DRAM 200; each physical address of the DRAM200 corresponds to a logical address and points to a subgroup storing mapping data of the corresponding logical address) in the DRAM200 in the reference table 204 (the reference table 204 has physical addresses of a plurality of subgroups of mapping tables in the flash memory chips; the mapping table has mapping data, each mapping data is used for mapping a logical address to a corresponding physical address of the flash memory chip; each physical address of the DRAM200 corresponds to a logical address and points to a subgroup storing mapping data of the corresponding logical address), receive a command from the host 20 of the solid state disk 10 to access a target logical address of the flash memory chip, confirm whether the physical address of the DRAM200 corresponding to the target logical address is stored in the logical mapping table 206, and receive a command to determine whether the physical address of the DRAM200 corresponding to the target logical address is stored in the logical address table, If the result is yes, the command is executed by using the mapping data in the subgroup, if the result is no, the corresponding subgroup of the mapping data containing the target logical address is copied from the mapping table to the DRAM200 via the reference table 204 to execute the command, the target physical address of the DRAM200 is added to the logical corresponding physical address table 206, the mapping data of the target logical address is stored in the target physical address so that the target logical address can correspond to the target physical address, when the logical corresponding physical address table reaches the maximum storage capacity, the target logical address having the lowest priority among all the target logical addresses (the priority can be set by the hit rate of the ordered temporary data access, the order of the most recently accessed records, or the order random grant weight) is removed from the logical corresponding physical address table 206, and a subgroup address to logical address table 208 is created in the DRAM200 (the subgroup address to logical address table 208 is the mapping data of the corresponding subgroup Stores the logical address and the physical address of the DRAM 200) and, if the command is a write, programs the data corresponding to the corresponding physical address in the flash memory chips according to the subgroup address to logical address table 208. A method of reducing the amount of DRAM200 used in the solid state disk 10 is substantially implemented by the controller 100. Therefore, the operation (functions used) of the controller 100 and the solid state disk 10 will be described in detail in a method description under different scenarios.
Referring to fig. 3, a flowchart of steps of a method for reducing DRAM usage in a solid state drive in one embodiment is shown. The first step is: s01, a reference table 204 is provided in the DRAM200 of the solid state disk 10. It is clear that the reference table 204 must be created because there is no data remaining in the DRAM200 upon power-up. The reference table 204 has physical addresses of a plurality of subgroups of mapping tables in the flash memory chips of the solid state disk 10, and the mapping tables are used to map logical addresses to corresponding physical addresses of the flash memory chips of the solid state disk 10, which is quite large. Therefore, the mapping table is usually broken into many subgroups and stored to a plurality of addresses (physical addresses of flash memory chips) with mapping data, each mapping data is used to map a logical address to a corresponding physical address of the non-volatile memory unit of the solid state disk; each subgroup includes a portion of all the image data. For a better understanding of this, please refer to fig. 2. FIG. 2 is a diagram of an embodiment of a DRAM200 data structure. The reference table 204 has two blocks. One of the physical addresses records the physical address of the mapping table in the flash memory chip of the solid state disk 10 (block 0 page 1 of the eighth flash memory chip 308, block 0 page 2 of the eighth flash memory chip 308, block 0 page 3 of the eighth flash memory chip 308, block 1 page 1 of the eighth flash memory chip 308, and block 1 page 2 of the eighth flash memory chip 308), and the other indicates the logical address of each subgroup of mapping data. For example, "1-10" refers to logical addresses 1-10 of the mapping data of the first subgroup. Block 0, page 2 of the eighth flash chip 308 stores logical addresses 1 through 10 of the mapping data. Of course, the arrangement of the reference table 204 may have a plurality of logical addresses in subgroups, or may have only one logical address in each subgroup, which is not limited in the present invention.
Next, in step S02, the logical correspondent physical address table 206 is provided in the DRAM200 of the solid state disk 10. The logical-to-physical address table 206 stores a plurality of logical addresses and physical addresses of the DRAM 200. In fig. 2, logical address 1 corresponds to physical address 0x80000001, and logical address 12 corresponds to physical address 0x 80000002. 0x80000001 of the DRAM200 records a logical address 1 of the image data. 0x80000002 of the DRAM200 records a logical address 12 of the image data. Logical address 1 belongs to a first subgroup and logical address 12 belongs to a second subgroup of the mapping table. Each physical address of DRAM200 corresponds to a logical address and points to a subgroup of mapped data having the corresponding logical address. The storage space 202 includes the physical address of the DRAM200 referenced by the logical corresponding physical address table 206 and is used for temporarily storing the image data. At this time, the storage space 202 has mapping data 1(MD1) and mapping data 2(MD2), and mapping data 3 shown in bold italics will be provided later. Similarly, the logical correspondent physical address table 206 needs to be created because it does not exist when the DRAM200 is powered on.
The third step is S03, receiving a command from the host 20 of the solid state disk 10 to access the target logical address of the non-volatile memory chip. Access refers to both writing and reading. For some steps, the writing and reading are considered the same, and the differences are indicated in the working examples. The mapping data for the target logical address may be found in the logical correspondent entity address table 206, e.g., 0x80000001 and 0x 80000002. The mapping data for the target logical address may not be retained in the logical correspondent entity address table 206. If a target logical address, 23, is to be accessed, further steps are performed since it is not in the logical correspondent physical address table 206. Therefore, in step S04, it is necessary to confirm whether the physical address of the DRAM200 corresponding to the target logical address is stored in the logical corresponding physical address table 206. If the result of step S04 is YES, step S05, only the mapped data in the subgroup need be used to execute the command. If the result of step S04 is NO, step S06 copies the corresponding subgroup of mapping data containing the target logical address from the mapping table to DRAM200 via the reference table 204 to execute the command. That is, the mapping table referred to by the reference table 204 functions to find the physical address of the flash memory chip of the solid state disk 10 corresponding to the target logical address, 23. According to the reference table 204, the physical addresses of the flash chips of the solid state disk 10 are in block 0, page 3 of the eighth flash chip 308. To access the target logical address, 23, controller 100 copies image data 3(MD3) into storage space 202. Finally, if the copying is performed, step S07, the target physical address of the DRAM200 is added to the logical-to-physical address table 206, and the mapping data of the target logical address is stored in the target physical address so that the target logical address can be mapped to the target physical address in the future.
Step S07 is to update the logical to physical address table 206 with the new mapping data for the target logical address that was not in the logical to physical address table 206 before the command was received. In this embodiment, there are 3 sets of the physical address of the module 200 and the corresponding logical address of the logical corresponding physical address table 206. Although in other embodiments there may be more sets, the number is not limited. The method requires further steps when the logical mapping physical address table 206 reaches the maximum storage capacity but continues to receive commands to access the new target logical address. In other embodiments, when the logical corresponding physical address table 206 reaches the maximum storage capacity, the target logical address with the lowest priority among all the target logical addresses is removed from the logical corresponding physical address table 206. This step may be added before step S07. That is, the least used or least important target logical address should be removed from the logical correspondent physical address table 206, as determined by priority. For example, the priority may be set by sorting the hit rate of the temporary data access (removing the target logical address of the temporary data with the smallest hit rate), or by arranging the most recently accessed records (removing the target logical address of the temporary data with the least accessed). Even more, the priority may be determined by the weight that the ordering optionally grants to each target logical address.
As described above, in one embodiment, access may include writing and reading. If the command is a write command, a further step is required after step S02: the subgroup address is provided in the DRAM200 of the solid state disk 10 to the logical address table 208. The subgroup address to logical address table 208 stores the logical address and the physical address of the DRAM200 for the mapping data of the corresponding subgroup. As shown in FIG. 2, the subgroup address-to-logical address table 208 originally stores logical address 1 and logical address 12, and the mapping data of subgroup 1 and subgroup 2(MD1 and MD 2). At this time, a new logical address of 3 and the physical address of the DRAM200 corresponding to subgroup 3 are added to the subgroup address to logical address table 208. The function of the subgroup address to logical address table 208 is to speed up the speed of programming data to the flash memory chip. The programming may be a separate step prior to step S07: data corresponding to the corresponding physical address of the flash memory chip is programmed according to the subgroup address to logical address table 204. For example, if the contents of logical address 23 are changed, the changed data will be programmed to a new physical address, block 0, page 0 through page 3 of the third flash chip 303. The previous physical address for storing the original data can be block 15, page 0 through page 3 of the third flash chip 303. The correct physical address of the new data is always tracked and recorded by the mapping table.
Compared with the traditional solid state disk, the method and the solid state disk framework provided by the invention do not need to copy the whole mapping table from the flash memory chip to the DRAM of the solid state disk. Thus, the capacity requirements of the DRAM may be reduced. The cost of the solid state disk can be reduced. Also, because of the use of the lookup table 204 and the increased I/O capability of the flash memory chip, the speed of locating the physical address of the data requested by the access command does not differ much from the speed of using DRAM.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
[ notation ] to show
10, a solid state disk; 100 a controller; 20, a host; 200 DRAMs; 202 a storage space; 204 refer to the table; 206 logic corresponds to a physical address table; 208 subgroup address to logical address table; 301 a first flash memory chip; 302 a second flash memory chip; 303 a third flash memory chip; 304 a fourth flash memory chip; 305 a fifth flash memory chip; 306 a sixth flash memory chip; 307 a seventh flash memory chip; 308 eighth flash memory chip.
Claims (14)
1. A method for reducing DRAM usage in a solid state disk, comprising the steps of:
A. providing a reference table in a DRAM of a solid state disk, wherein the reference table has physical addresses of a plurality of subgroups of mapping tables in non-volatile memory units of the solid state disk, wherein the mapping tables have mapping data, each mapping data for mapping a logical address to a corresponding physical address of a non-volatile memory unit of the solid state disk; each subgroup includes a portion of all the mapping data;
B. providing a logical corresponding physical address table in a DRAM of the solid state disk, wherein the logical corresponding physical address table stores a plurality of logical addresses and physical addresses of the DRAM, wherein each physical address of the DRAM corresponds to one logical address and points to a subgroup of the mapping data having the corresponding logical address;
C. receiving a command, wherein the command is from a host of the solid state disk and is used for accessing a target logic address of the non-volatile memory unit;
D. confirming whether the physical address of the DRAM corresponding to the target logical address is stored in the logical corresponding physical address table;
E. if the result of step D is yes, using the mapping data in the subgroup to execute the command, or if the result of step D is no, copying the corresponding subgroup of mapping data containing the target logical address from the mapping table to the DRAM through the reference table to execute the command; and
F. and adding a target physical address of the DRAM to the logical corresponding physical address table, wherein the mapping data of the target logical address is stored in the target physical address so that the target logical address can correspond to the target physical address.
2. The method of claim 1, further comprising, before step F, step E1:
e1, when the logical corresponding physical address table reaches the maximum storage capacity, removing the target logical address with the lowest priority in all the target logical addresses from the logical corresponding physical address table.
3. The method of claim 2, wherein the priority is set by ranking hit rates of temporary data accesses, ranking recent access records in order, or ranking discretionary weighting.
4. The method of claim 1, further comprising, after step B, step B1:
b1, providing subgroup address to logical address table in the DRAM of the solid state disk, wherein the subgroup address to logical address table stores logical addresses and physical addresses of the DRAM for the mapping data of the corresponding subgroup.
5. The method of claim 1, wherein if the command is a write, the method further comprises, before step F, step E2:
e2, programming data corresponding to the physical address in the nonvolatile memory cell according to the subgroup address to logical address table.
6. The method of claim 1, wherein the non-volatile memory unit is a flash memory chip in the solid state disk.
7. The method of claim 6, wherein the flash memory chip is a NAND flash memory chip, a NOR flash memory chip, or a charge extraction flash memory chip.
8. A solid state disk, comprising:
a plurality of non-volatile memory cells;
a DRAM; and
a controller for creating a reference table in the DRAM, wherein the reference table has physical addresses of a plurality of subgroups of mapping tables in the non-volatile memory unit, wherein the mapping tables have mapping data, each mapping data for mapping a logical address to a corresponding physical address of the non-volatile memory unit; each subgroup includes a portion of all the mapping data;
creating a logical-to-physical address table in the DRAM, wherein the logical-to-physical address table stores a plurality of logical addresses and physical addresses of the DRAM, wherein each physical address of the DRAM corresponds to one logical address and points to a subgroup storing mapping data of the corresponding logical address;
receiving a command, wherein the command is from a host of the solid state disk and is used for accessing a target logic address of the non-volatile memory unit;
confirming whether the physical address of the DRAM corresponding to the target logical address is stored in the logical corresponding physical address table;
if the result of the confirmation is yes, using the mapping data in the subgroup to execute the command;
if the result of the confirmation is negative, copying a corresponding subgroup of mapping data containing the target logical address from the mapping table to the DRAM through the reference table to execute the command; and
and adding a target physical address of the DRAM to the logical corresponding physical address table, wherein the mapping data of the target logical address is stored in the target physical address so that the target logical address can correspond to the target physical address.
9. The solid state disk of claim 8, wherein the controller is further to remove a target logical address having a lowest priority of all target logical addresses from the logically corresponding physical address table when the logically corresponding physical address table reaches a maximum storage capacity.
10. The solid state disk of claim 9, wherein the priority is set by sorting hit rates of temporary data accesses, arranging the most recent access records in order, or ordering randomly granting weight.
11. The solid state disk of claim 8, wherein the controller is further configured to create a subgroup address to logical address table in the DRAM, wherein the subgroup address to logical address table stores logical addresses and physical addresses of the DRAM for mapping data of corresponding subgroups.
12. The solid state disk of claim 11, wherein if the command is a write command, the controller is further configured to program data corresponding to a physical address in the non-volatile memory cells according to the subgroup address to logical address table.
13. The solid state disk of claim 8, wherein the non-volatile memory cells are flash memory chips in the solid state disk.
14. The solid state disk of claim 13, wherein the flash memory chips are NAND flash memory chips, NOR flash memory chips, or charge extraction flash memory chips.
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| CN101989235A (en) * | 2009-08-06 | 2011-03-23 | 慧国(上海)软件科技有限公司 | Flash memory device and operating method thereof |
| CN102023927A (en) * | 2009-09-22 | 2011-04-20 | 点序科技股份有限公司 | Flash memory control device and access method thereof |
| CN105632534A (en) * | 2015-03-24 | 2016-06-01 | 上海磁宇信息科技有限公司 | Solid-state drive with mixed use of DRAM (Dynamic Random Access Memory) and MRAM (Magnetic Random Access Memory) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101989235A (en) * | 2009-08-06 | 2011-03-23 | 慧国(上海)软件科技有限公司 | Flash memory device and operating method thereof |
| CN102023927A (en) * | 2009-09-22 | 2011-04-20 | 点序科技股份有限公司 | Flash memory control device and access method thereof |
| CN105632534A (en) * | 2015-03-24 | 2016-06-01 | 上海磁宇信息科技有限公司 | Solid-state drive with mixed use of DRAM (Dynamic Random Access Memory) and MRAM (Magnetic Random Access Memory) |
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