CN107643876A - Storage management method, memory storage apparatus and memorizer control circuit unit - Google Patents
Storage management method, memory storage apparatus and memorizer control circuit unit Download PDFInfo
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Abstract
The present invention provides a kind of storage management method, memory storage apparatus and memorizer control circuit unit.The method includes：Unit is wiped for the first physics and configures pre-arranged code rule, and it includes being intended to store to the data of the first physics erasing unit to encode based on default code check；And the false assessment information of unit is wiped according to the first physics, unit, which is wiped, for the first physics configures the first coding rule, it is included being intended to store to the data for the first kind physics programming unit for belonging to the first physics erasing unit to encode based on the first code check and is intended to store to the data for the second class physics programming unit for belonging to the first physics erasing unit to encode based on the second code check, wherein the value of the first code check is more than the value of default code check, and the value of the second code check is less than the value of default code check.Thereby, the life-span of memory storage apparatus can be extended.
Description
Technical field
The present invention relates to a kind of memory management technique, more particularly to a kind of storage management method, memory storage to fill
Put and memorizer control circuit unit.
Background technology
Digital camera, mobile phone and MP3 player are very rapid in growth over the years so that consumer is to storage
The demand of media also rapidly increases.Because rewritable nonvolatile memory module (for example, flash memory) has data non-
Volatibility, power saving, small volume, and without characteristics such as mechanical structures, thus be especially suitable for being built into it is above-mentioned it is illustrated it is various can
Take in formula multimedia device.
In some storage arrangements, data can first be encoded and then can just be stored.Later, when needing to read this data
When, the data read out can be decoded, to attempt to correct mistake therein.However, the usage time with storage arrangement
Increase, wherein increasing memory block may be considered as damaging and can not continuing to use.When depositing for a predetermined number
When reservoir block damages, storage arrangement can enter write protection state.Under write protection state, new data will be unable to be write
Enter into storage arrangement.Therefore, on the premise of normal use storage arrangement, how by extension wherein memory block
Life-span, actually those skilled in the art endeavour one of problem of research.
The content of the invention
The present invention provides a kind of storage management method, memory storage apparatus and memorizer control circuit unit, can prolong
The life-span of long memory storage device.
One example of the present invention embodiment provides a kind of storage management method, and it is used to include multiple physics erasing units
Rewritable nonvolatile memory module, the storage management method includes：First in unit is wiped for the physics
Physics erasing unit configuration pre-arranged code rule, wherein pre-arranged code rule includes being intended to store to encode based on default code check
To the first kind physics programming unit that belongs to first physics erasing unit data and encoded based on the default code check
It is intended to store to the data for the second class physics programming unit for belonging to the first physics erasing unit；First physics is obtained to wipe
Except the false assessment information of unit；And the false assessment information of unit is wiped according to first physics, for described the
One physics erasing unit configures the first coding rule, wherein first coding rule includes being intended to deposit to encode based on the first code check
Store up to the data for the first kind physics programming unit for belonging to the first physics erasing unit and compiled based on the second code check
Code is intended to store to the data for the second class physics programming unit for belonging to the first physics erasing unit, wherein described first
The value of code check is more than the value of the default code check, and the value of second code check is less than the value of the default code check.
In one example of the present invention embodiment, the false assessment information of unit is wiped according to first physics,
Wiping the step of unit configures first coding rule for first physics includes：Wiped according to first physics is belonged to
The first kind physics programming unit of unit or the second class physics programming list for belonging to the first physics erasing unit
The bit error rate of member determines first code check and second code check.
Another example of the present invention embodiment provides a kind of memory storage apparatus, and it includes connecting interface unit, can weighed
Write non-volatile memory module and memorizer control circuit unit.The connecting interface unit is being connected to host computer system.
The rewritable nonvolatile memory module includes multiple physics erasing unit.The memorizer control circuit unit is connected to
The connecting interface unit and the rewritable nonvolatile memory module, the memorizer control circuit unit is to for institute
The first physics erasing unit configuration pre-arranged code rule in physics erasing unit is stated, wherein pre-arranged code rule includes base
In default code check come encode be intended to store to the first kind physics programming unit for belonging to the first physics erasing unit data simultaneously
It is intended to store to the second class physics programming unit for belonging to the first physics erasing unit to encode based on the default code check
Data, the memorizer control circuit unit are described more to obtain the false assessment information of the first physics erasing unit
Memorizer control circuit unit is more described first to wipe the false assessment information of unit according to first physics
Physics erasing unit configures the first coding rule, wherein first coding rule includes being intended to store to encode based on the first code check
To the first kind physics programming unit that belongs to first physics erasing unit data and encoded based on the second code check
It is intended to store to the data for the second class physics programming unit for belonging to the first physics erasing unit, wherein described first yard
The value of rate is more than the value of the default code check, and the value of second code check is less than the value of the default code check.
In one example of the present invention embodiment, the pre-arranged code rule also includes encoding based on the default code check
It is intended to store to the data for the 3rd class physics programming unit for belonging to the first physics erasing unit, first coding rule is also
Including programming list based on third yard rate to encode to be intended to store to the 3rd class physics for belonging to the first physics erasing unit
The data of member, wherein the summation of the value of the value of first code check, the value of second code check and the third yard rate is equal to institute
State the value of default code check three times.
In one example of the present invention embodiment, the memorizer control circuit unit is wiped single according to first physics
The false assessment information of member, the operation of unit configuration first coding rule is wiped for first physics to be included：Root
According to the first kind physics programming unit for belonging to the first physics erasing unit or belong to the first physics erasing unit
The bit error rate of the second class physics programming unit determine first code check and second code check.
Another example of the present invention embodiment provides a kind of memorizer control circuit unit, and it, which is used to control, includes multiple things
The rewritable nonvolatile memory module of reason erasing unit, the memorizer control circuit unit include HPI, storage
Device interface, error checking and correcting circuit and memory management circuitry.The HPI is being connected to host computer system.It is described
Memory interface is being connected to the rewritable nonvolatile memory module.The memory management circuitry is connected to described
HPI, the memory interface and the error checking and correcting circuit, the memory management circuitry is to be described
The first physics erasing unit configuration pre-arranged code rule in physics erasing unit, wherein pre-arranged code rule is included by institute
Error checking and correcting circuit is stated to be intended to store to belonging to the first of the first physics erasing unit to encode based on default code check
The data of class physics programming unit are simultaneously intended to store to belonging to the first physics erasing unit based on the default code check to encode
The second class physics programming unit data, the memory management circuitry is more obtaining first physics erasing unit
False assessment information, the memory management circuitry are more believed to wipe the false assessment of unit according to first physics
Breath, wipe unit for first physics and configure the first coding rule, wherein first coding rule is included by the mistake
Check and correcting circuit encodes the first kind for being intended to store to the first physics erasing unit is belonged to based on the first code check
The data of physics programming unit are simultaneously intended to store to belonging to described in the first physics erasing unit based on the second code check to encode
The data of second class physics programming unit, wherein the value of first code check is more than the value of the default code check, and described second
The value of code check is less than the value of the default code check.
In one example of the present invention embodiment, the first kind physics programming unit is lower physics programming unit, and
The second class physics programming unit is upper physics programming unit.
In one example of the present invention embodiment, the summation of the value of first code check and the value of second code check is equal to
Two times of the value of the default code check.
In one example of the present invention embodiment, the pre-arranged code rule is also included by the error checking and correction electricity
Roadbed encodes the 3rd class physics programming unit for being intended to store to the first physics erasing unit is belonged in the default code check
Data, first coding rule also include be intended to store to encode based on third yard rate with correcting circuit by the error checking
To the data for the 3rd class physics programming unit for belonging to first physics erasing unit, wherein first code check
The summation of the value of value, the value of second code check and the third yard rate is equal to three times of the value of the default code check.
In one example of the present invention embodiment, the first kind physics programming unit is lower physics programming unit, described
Second class physics programming unit is upper physics programming unit, and the 3rd class physics programming unit is that the programming of extra physics is single
Member.
In one example of the present invention embodiment, the value of the third yard rate is equal to the value of the default code check.
In one example of the present invention embodiment, the memory management circuitry wipes unit according to first physics
The false assessment information, the operation of unit configuration first coding rule is wiped for first physics to be included：According to category
The first kind physics programming unit of unit is wiped in first physics or belongs to the institute of the first physics erasing unit
The bit error rate of the second class physics programming unit is stated to determine first code check and second code check.
Based on above-mentioned, coding rule of the present invention dynamically renewal corresponding to specific physics erasing unit.By control
Belong to the code check of the physics programming unit of multiple types of specific physics erasing unit, the life-span of this specific physics erasing unit can
To be extended.Thereby, the life-span of memory storage apparatus can also be extended.
For features described above of the invention and advantage can be become apparent, special embodiment below, and it is detailed to coordinate accompanying drawing to make
Carefully it is described as follows.
Brief description of the drawings
Fig. 1 is host computer system, memory storage apparatus and input according to one example of the present invention embodiment/defeated
Go out the schematic diagram of (I/O) device；
Fig. 2 is host computer system, memory storage apparatus and the I/O dresses according to another example of the present invention embodiment
The schematic diagram put；
Fig. 3 is the signal of the host computer system and memory storage apparatus according to another example of the present invention embodiment
Figure；
Fig. 4 is the summary block diagram of the memory storage apparatus according to one example of the present invention embodiment；
Fig. 5 is the summary block diagram of the memorizer control circuit unit according to one example of the present invention embodiment；
Fig. 6 is showing for the management rewritable nonvolatile memory module according to one example of the present invention embodiment
It is intended to；
Fig. 7 A are the showing come coded data based on pre-arranged code rule according to one example of the present invention embodiment
It is intended to；
Fig. 7 B are the showing come coded data based on the first coding rule according to one example of the present invention embodiment
It is intended to；
Fig. 8 A be according to another example of the present invention embodiment based on pre-arranged code rule come coded data
Schematic diagram；
Fig. 8 B be according to another example of the present invention embodiment based on the first coding rule come coded data
Schematic diagram；
Fig. 9 is the schematic diagram of the error checking and correcting circuit according to one example of the present invention embodiment；
Figure 10 is the flow chart of the storage management method according to one example of the present invention embodiment.
Reference：
10、30：Memory storage apparatus；
11、31：Host computer system；
110：System bus；
111：Processor；
112：Random access memory；
113：Read-only storage；
114：Data transmission interface；
12：Input/output (I/O) device；
20：Motherboard；
201：Portable disk；
202：Storage card；
203：Solid state hard disc；
204：Radio memory storage device；
205：GPS module；
206：NIC；
207：Radio transmitting device；
208：Keyboard；
209：Screen；
210：Loudspeaker；
32：SD card；
33：CF cards；
34：Embedded storage device；
341：Embedded multi-media card；
342：Embedded type multi-core piece sealed storage device；
402：Connecting interface unit；
404：Memorizer control circuit unit；
406：Rewritable nonvolatile memory module；
502：Memory management circuitry；
504：HPI；
506：Memory interface；
508：Error checking and correcting circuit；
510：Buffer storage；
512：Electric power management circuit；
601：Memory block；
602：Replacement area；
610 (0)~610 (B), 710,810：Physics wipes unit；
612 (0)~612 (C)：Logic unit；
701_1~701_n, 801_1~801_n：First kind physics programming unit；
701_2~702_n, 802_1~802_n：Second class physics programming unit；
803_1~803_n：3rd class physics programming unit；
901：Code rate selection device；
902：Coding circuit；
S1001：Step (wipes unit for the first physics and configures pre-arranged code rule, wherein pre-arranged code rule bag
Include based on default code check come encode be intended to store to the first kind physics programming unit for belonging to the first physics erasing unit data simultaneously
It is intended to store to the data for the second class physics programming unit for belonging to the first physics erasing unit to encode based on default code check)；
S1002：Step (the false assessment information for obtaining the first physics erasing unit)；
S1003：Step (wipes the false assessment information of unit according to the first physics, unit configuration is wiped for the first physics
First coding rule, wherein the first coding rule includes being intended to store to belonging to the erasing of the first physics singly to encode based on the first code check
The data of the first kind physics programming unit of member simultaneously wipe unit based on the second code check to encode to be intended to store to belonging to the first physics
The second class physics programming unit data).
Embodiment
In general, memory storage apparatus (also referred to as, storage system) includes rewritable nonvolatile memory
Module (rewritable non-volatile memory module) and controller (also referred to as, control circuit).It is commonly stored device
Storage device is used together with host computer system, so that host computer system can write data into memory storage apparatus or from storage
Data are read in device storage device.
Fig. 1 is host computer system, memory storage apparatus and input according to one example of the present invention embodiment/defeated
Go out the schematic diagram of (I/O) device.Fig. 2 is that host computer system according to another example of the present invention embodiment, memory are deposited
The schematic diagram of storage device and I/O devices.
Fig. 1 and Fig. 2 are refer to, host computer system 11 generally comprises processor 111, random access memory (random
Access memory, RAM) 112, read-only storage (read only memory, ROM) 113 and data transmission interface 114.Place
Reason device 111, random access memory 112, read-only storage 113 and data transmission interface 114 are all connected to system bus
(system bus)110。
In this exemplary embodiment, host computer system 11 is connected by data transmission interface 114 and memory storage apparatus 10
Connect.For example, host computer system 11 can via data transmission interface 114 by data storage to memory storage apparatus 10 or from memory
Data are read in storage device 10.In addition, host computer system 11 is to be connected by system bus 110 with I/O devices 12.It is for example, main
Output signal can be sent to I/O devices 12 via system bus 110 or receive input signal from I/O devices 12 by machine system 11.
In this exemplary embodiment, processor 111, random access memory 112, read-only storage 113 and data transfer
Interface 114 may be provided on the motherboard 20 of host computer system 11.The number of data transmission interface 114 can be one or more.
By data transmission interface 114, motherboard 20 can be connected to memory storage apparatus 10 via wired or wireless way.Storage
Device storage device 10 can be for example portable disk 201, storage card 202, solid state hard disc (Solid State Drive, SSD) 203 or
Radio memory storage device 204.Radio memory storage device 204 can be for example wireless near field communication (Near Field
Communication, NFC) memory storage apparatus, radio facsimile (WiFi) memory storage apparatus, bluetooth (Bluetooth)
Memory storage apparatus or low-power consumption bluetooth memory storage apparatus (for example, iBeacon) etc. using various wireless communication technology as
The memory storage apparatus on basis.In addition, motherboard 20 can also be connected to global positioning system by system bus 110
(Global Positioning System, GPS) module 205, NIC 206, radio transmitting device 207, keyboard 208,
The various I/O devices such as screen 209, loudspeaker 210.For example, in an exemplary embodiment, motherboard 20 can pass through radio transmitting device
207 access wireless memory storage apparatus 204.
In an exemplary embodiment, mentioned host computer system is substantially to coordinate with memory storage apparatus to store
Any system of data.Although in above-mentioned exemplary embodiment, host computer system is explained with computer system, however, Fig. 3 is
The schematic diagram of host computer system and memory storage apparatus according to another example of the present invention embodiment.It refer to Fig. 3,
In another exemplary embodiment, host computer system 31 can also be digital camera, video camera, communicator, audio player, video
The system such as player or tablet personal computer, and memory storage apparatus 30 can be its used secure digital (Secure
Digital, SD) card 32, that compact flash (Compact Flash, CF) blocks 33 or embedded storage devices 34 etc. is various non-volatile
Property memory storage apparatus.Embedded storage device 34 includes embedded multi-media card (embedded Multi-Chip
Package, eMMC) 341 and/or embedded type multi-core piece encapsulation (embedded Multi Chip Package, eMCP) storage dress
Put all types of embedded storage devices memory module being directly connected on the substrate of host computer system such as 342.
Fig. 4 is the summary block diagram of the memory storage apparatus according to one example of the present invention embodiment.
Refer to Fig. 4, memory storage apparatus 10 include connecting interface unit 402, memorizer control circuit unit 404 with
Rewritable nonvolatile memory module 406.
Connecting interface unit 402 by memory storage apparatus 10 being connected to host computer system 11.In this exemplary embodiment
In, connecting interface unit 402 be compatible to the advanced annex of sequence (Serial Advanced Technology Attachment,
SATA) standard.However, it is necessary to be appreciated that, the invention is not restricted to this, connecting interface unit 402 can also meet elder generation arranged side by side
Enter annex (Parallel Advanced Technology Attachment, PATA) standard, Institute of Electrical and Electric Engineers
(Institute of Electrical and Electronic Engineers, IEEE) 1394 standards, high-speed peripheral part
Connecting interface (Peripheral Component Interconnect Express, PCI Express) standard, universal sequence
Bus (Universal Serial Bus, USB) standard, SD interface standard, a ultrahigh speed generation (Ultra High Speed-I,
UHS-I) interface standard, the generation of ultrahigh speed two (Ultra High Speed-II, UHS-II) interface standard, memory stick (Memory
Stick, MS) interface standard, MCP interface standards, MMC interface standards, eMMC interface standards, general flash memory
(Universal Flash Storage, UFS) interface standard, eMCP interface standards, CF interface standards, integrated driving electronics
Interface (Integrated Device Electronics, IDE) standard or other suitable standards.Connecting interface unit 402 can
It is encapsulated in memorizer control circuit unit 404 in a chip, or connecting interface unit 402 is to be laid in one to include storage
Outside the chip of device control circuit unit 404.
Memorizer control circuit unit 404 is performing multiple gates or control with hardware pattern or firmware pattern implementation
System instruction and according to the instruction of host computer system 11 carried out in rewritable nonvolatile memory module 406 data write-in,
The running such as reading and erasing.
Rewritable nonvolatile memory module 406 is to be connected to memorizer control circuit unit 404 and to store
The data that host computer system 11 is write.Rewritable nonvolatile memory module 406 can be single-order memory cell (Single
Level Cell, SLC) NAND flash memory module (that is, can store the flash memory of 1 position in a memory cell
Module), multi-level cell memory (Multi Level Cell, MLC) NAND flash memory module (that is, memory cell
In can store the flash memory modules of 2 positions), three rank memory cell (Triple Level Cell, TLC) NAND flash
Memory module (that is, the flash memory module that 3 positions can be stored in a memory cell), other flash memory modules or
Other have the memory module of identical characteristic.
Each memory cell in rewritable nonvolatile memory module 406 is with voltage (hereinafter also referred to threshold value
Voltage) change store one or more positions.Specifically, the control gate (control gate) of each memory cell
There is an electric charge capture layer between channel.By bestowing a write-in voltage to control gate, thus it is possible to vary electric charge is mended and catches layer
Amount of electrons, and then change the threshold voltage of memory cell.This operation for changing threshold voltage also referred to as " is write the data to storage
Unit " or " sequencing memory cell ".It is every in rewritable nonvolatile memory module 406 with the change of threshold voltage
One memory cell has multiple storage states.It may determine that a memory cell is which belongs to by bestowing reading voltage
Storage state, thereby obtain one or more positions that this memory cell is stored.
Fig. 5 is the summary block diagram of the memorizer control circuit unit according to one example of the present invention embodiment.
Fig. 5 is refer to, memorizer control circuit unit 404 includes memory management circuitry 502, HPI 504, storage
Device interface 506 and error checking and correcting circuit 508.
Memory management circuitry 502 to control memory control circuit unit 404 overall operation.Specifically, deposit
Reservoir management circuit 502 has multiple control instructions, and when memory storage apparatus 10 operates, this little control instruction can quilt
Perform to carry out the runnings such as the write-in of data, reading and erasing.It is equivalent when illustrating the operation of memory management circuitry 502 below
In the operation of explanation memorizer control circuit unit 404.
In this exemplary embodiment, the control instruction of memory management circuitry 502 is to carry out implementation with firmware pattern.For example,
Memory management circuitry 502 has microprocessor unit (not shown) and read-only storage (not shown), and this little control refers to
Order is by imprinting so far read-only storage.When memory storage apparatus 10 operates, this little control instruction can be by microprocessor
Unit is operated to perform with carrying out the write-in of data, reading and erasing etc..
In another exemplary embodiment, the control instruction of memory management circuitry 502 can also procedure code pattern be stored in
The specific region of rewritable nonvolatile memory module 406 is (for example, storage system data are exclusively used in memory module is
Unite area) in.In addition, memory management circuitry 502 have microprocessor unit (not shown), read-only storage (not shown) and with
Machine accesses memory (not shown).Particularly, this read-only storage has boot code (boot code), and works as memory control
When circuit unit 404 processed is enabled, microprocessor unit can first carry out this boot code and be deposited rewritable nonvolatile is stored in
Control instruction in memory modules 406 is loaded into the random access memory of memory management circuitry 502.Afterwards, microprocessor
Device unit can operate this little control instruction to carry out the runnings such as the write-in of data, reading and erasing.
In addition, in another exemplary embodiment, the control instruction of memory management circuitry 502 can also a hardware pattern
Implementation.For example, memory management circuitry 502 includes microcontroller, Storage Unit Management circuit, memory write circuit, storage
Device reading circuit, memory erasing circuit and data processing circuit.Storage Unit Management circuit, memory write circuit, storage
Device reading circuit, memory erasing circuit and data processing circuit are to be connected to microcontroller.Storage Unit Management circuit to
Manage memory cell or its group of rewritable nonvolatile memory module 406.Memory write circuit is to rewritable
Non-volatile memory module 406 assigns write instruction sequence to write data into rewritable nonvolatile memory module
In 406.Memory reading circuitry reads command sequence with from can weigh to be assigned to rewritable nonvolatile memory module 406
Write in non-volatile memory module 406 and read data.Memory erasing circuit is to rewritable nonvolatile memory mould
Block 406 assigns erasing instruction sequence so that data to be wiped from rewritable nonvolatile memory module 406.Data processing circuit
It is intended to write to the data of rewritable nonvolatile memory module 406 and from rewritable nonvolatile memory mould to handle
The data read in block 406.Write instruction sequence, reading command sequence and erasing instruction sequence can distinctly include one or more journeys
Sequence code or instruction code and to indicate that rewritable nonvolatile memory module 406 performs corresponding write-in, reading and wiping
Operated except waiting.In an exemplary embodiment, memory management circuitry 502 can also assign other kinds of command sequence to can weigh
Non-volatile memory module 406 is write to indicate to perform corresponding operation.
HPI 504 is to be connected to memory management circuitry 502 and to receive and identify that host computer system 11 is passed
The instruction sent and data.That is, the instruction that host computer system 11 is transmitted can be sent to data by HPI 504
Memory management circuitry 502.In this exemplary embodiment, HPI 504 is to be compatible to SATA standard.However, it is necessary to understand
Be the invention is not restricted to this, HPI 504 can also be compatible to PATA standards, the standards of IEEE 1394, PCI
Express standards, USB standard, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS marks
Standard, CF standards, IDE standards or other suitable data transmission standards.
Memory interface 506 is to be connected to memory management circuitry 502 and to access rewritable nonvolatile storage
Device module 406.That is, the data for being intended to write to rewritable nonvolatile memory module 406 can be via memory interface
506 are converted to the receptible form of the institute of rewritable nonvolatile memory module 406.Specifically, if memory management circuitry
502 will access rewritable nonvolatile memory module 406, and memory interface 506 can transmit corresponding command sequence.For example,
These command sequences may include that the write instruction sequence of instruction write-in data, instruction read the reading command sequence of data, instruction
Wipe the erasing instruction sequence of data and to indicate that various storage operations (read voltage quasi position or execution for example, changing
Garbage reclamation program etc.) corresponding command sequence.These command sequences are, for example, to be produced by memory management circuitry 502
And rewritable nonvolatile memory module 406 is sent to by memory interface 506.These command sequences may include one or
Multiple signals, or the data in bus.These signals or data may include instruction code or procedure code.For example, refer in reading
Make in sequence, the information such as identification code, the storage address of reading can be included.
Error checking and correcting circuit 508 be connected to memory management circuitry 502 and to perform error checking with
Correct operation is to ensure the correctness of data.Specifically, write when memory management circuitry 502 receives from host computer system 11
When entering to instruct, error checking can be error correcting code corresponding to the data generation of this corresponding write instruction with correcting circuit 508
(error correcting code, ECC) and/or error checking code (error detecting code, EDC), and store
Device management circuit 502 data of this corresponding write instruction and corresponding error correcting code and/or error checking code can be write to
In rewritable nonvolatile memory module 406.Afterwards, when memory management circuitry 502 is from rewritable nonvolatile memory
Error correcting code corresponding to this data and/or error checking code, and mistake inspection can be read when data are read in module 406 simultaneously
Look into correcting circuit 508 data read can be performed according to this error correcting code and/or error checking code error checking with
Correct operation.
In this exemplary embodiment, error checking supports low-density parity inspection (low-density with correcting circuit 508
Parity-check, LDPC) code.For example, error checking and correcting circuit 508 can utilize low-density parity check code encoding and
Decoding.However, in another exemplary embodiment, error checking can also support BCH code, convolution code with correcting circuit 508
The other kinds of coding/decoding algorithms such as (convolutional code), block code (block code), the present invention are not limited
System.Those of ordinary skill in the art be understood that how using the coding/decoding algorithm come perform coding and decoding operate,
This is not just repeated.
In an exemplary embodiment, memorizer control circuit unit 404 also includes buffer storage 510 and power management electricity
Road 512.Buffer storage 510 is to be connected to memory management circuitry 502 and be configured to temporarily store the number for coming from host computer system 11
According to the data with instructing or coming from rewritable nonvolatile memory module 406.Electric power management circuit 512 is to be connected to storage
Device manages circuit 502 and to the power supply of control memory storage device 10.
Fig. 6 is showing for the management rewritable nonvolatile memory module according to one example of the present invention embodiment
It is intended to.It will be appreciated that the physical location of the rewritable nonvolatile memory module 406 described in following exemplary embodiment
Running when, it is concept in logic to carry out operating physical unit with words such as " packets ".That is, rewritable nonvolatile stores
The physical location of the physical location of device module 406 is not changed, but in logic to rewritable nonvolatile memory module 406
Physical location operated.
In this exemplary embodiment, the memory cell of rewritable nonvolatile memory module 406 can form multiple physics
Programming unit, and this little physics programming unit can form multiple physics erasing units.Specifically, depositing in same wordline
Storage unit can form one or more physics programming units.If each memory cell can store the position of more than 2, same
Physics programming unit in wordline can at least be classified as lower physics programming unit and upper physics programming unit.If for example, one
Memory cell can store 2 positions (for example, " 11 ", " 10 ", " 00 " or " 01 "), then the physics programming unit bag in same wordline
Include a lower physics programming unit and a upper physics programming unit.In MLC NAND flash memories, lower physics programming
The writing speed of unit can be more than the writing speed of upper physics programming unit, and/or the reliability of lower physics programming unit is high
In the reliability of upper physics programming unit.If in addition, a memory cell can store 3 positions (for example, " 111 ", " 110 ",
" 100 ", " 011 ", " 010 ", " 000 ", " 001 " or " 101 "), then the physics programming unit in same wordline is included under one
Physics programming unit, a upper physics programming unit and extra (extra) physics programming unit.
In this exemplary embodiment, physics programming unit is the minimum unit of sequencing.That is, physics programming unit is write-in
The minimum unit of data.For example, physics programming unit is physical page (page) or physics fan (sector).If physics programs
Unit is physical page, then this little physics programming unit generally includes data bit area and redundancy (redundancy) position area.Data
Position area includes multiple physics and fanned, to store user's data, and redundant digit area to memory system data (for example, it is wrong more
Code).In this exemplary embodiment, data bit area includes 32 physics and fanned, and the size of a physics fan is 512 hytes
(byte,B).However, in other exemplary embodiments, it can also include 8,16 in data bit area or number is more or less
Physics is fanned, and the size of each physics fan can also be greater or lesser.On the other hand, physics erasing unit is erasing
Least unit.That is, each physics erasing unit contains the memory cell being wiped free of in the lump of minimal amount.For example, physics is wiped
Unit is physical block (block).
Fig. 6 is refer to, memory management circuitry 502 can wipe the physics of rewritable nonvolatile memory module 406
(B) is logically grouped into memory block 601 and replacement area 602 for unit 610 (0)~610.Physics erasing unit in memory block 601
610 (0)~610 (A) are that the physics erasing unit 610 (A+1)~610 (B) to data storage, and in replacement area 602 is then
Unit is wiped to replace the physics damaged in memory block 601.For example, if the data read in unit are wiped from some physics
Comprising mistake it is excessive and when can not be corrected, this physics erasing unit can be considered to be the physics erasing unit of damage.
In one exemplary embodiment, the physics erasing unit of damage is also referred to as bad block (bad block).If it is noted that replacement area 602
In there is no available physics erasing unit, then whole memory storage device 10 can be declared as writing by memory management circuitry 502
Enter protection (write protect) state, and data can not be write again.
The meeting configuration logic unit 612 of memory management circuitry 502 (0)~612 (C) is with the physics in mapped memory region 601
Wipe unit 610 (0)~610 (A).For example, in this exemplary embodiment, host computer system 11 is by logical address (logical
Address, LA) data in memory block 601 are accessed, therefore, each logic in logic unit 612 (0)~612 (C)
Unit refers to a logical address.However, each in another exemplary embodiment, in logic unit 612 (0)~612 (C)
Logic unit may also mean that a logical program unit, a logic erasing unit or by multiple continuous or discrete
Logical address forms.In addition, each logic unit in logic unit 612 (0)~612 (C) can be mapped to one or more
Individual physics wipes unit.
Memory management circuitry 502 can by logic unit and physics erasing unit between mapping relations (also referred to as logic-
Physical mappings relation) it is recorded in an at least logical-physical mapping table.When host computer system 11 is intended to read from memory storage apparatus 10
Data or when writing data to memory storage apparatus 10, memory management circuitry 502 can according to this logical-physical mapping table come
Perform the data access for memory storage apparatus 10.
In this exemplary embodiment, error checking can encode a certain user with correcting circuit 508 based on a certain code check
Data (that is, from host computer system 11 and the data to be stored) simultaneously produce a coded data, and wherein this code check refers to user
The ratio that data are occupied in coded data.For example, it is assumed that user's packet is containing (n-k) individual position and via encoding operation
Caused coded data includes n position, then the code check for being used to encode this user's data is (n-k)/n.In other words, it is based on
(n-k)/n code check can produce the coded data of n position to encode user's data of (n-k) individual position, wherein this n position
Coded data is made up of user's data of (n-k) individual position and odd even (parity) data of k position.In addition, this k position
Odd and even data be the error correcting code (and/or error checking code) that can be considered user's data corresponding to this (n-k) individual position.
Then, some physics that the coded data of this n position can be stored in rewritable nonvolatile memory module 406 is compiled
Cheng Danyuan.For example, one or more logic units belonging to user's data of (n-k) the individual position can map so far physics programming
Unit.In this physics programming unit, user's data of (n-k) individual position can be stored in data bit area, and the odd even of k position
Data can then be stored in redundant digit area.
At the initial stage that uses of memory storage apparatus 10, memory management circuitry 502 can be that rewritable nonvolatile stores
Each physics erasing unit in device module 406 configures a coding rule (hereinafter also referred to pre-arranged code rule).Foundation
This pre-arranged code rule, error checking can be compiled with correcting circuit 508 based on a code check (hereinafter also referred to default code check)
Code is intended to store to the data of corresponding physics erasing unit.
It is that each physics in rewritable nonvolatile memory module 406 wipes unit in this exemplary embodiment
The pre-arranged code rule of configuration is all identical.That is, for encode be intended to store it is pre- to the data of each physics erasing unit
If code check is all identical.It is different in rewritable nonvolatile memory module 406 however, in another exemplary embodiment
The pre-arranged code rule of physics erasing unit configuration may also be different so that be intended to store to the data of different physics erasing unit
It can be encoded based on different default code checks.For example, it is contemplated that stored to a certain physics erasing unit in rewritable nonvolatile
Material property, the operator scheme of some physics erasing unit of position, some physics erasing unit in device module 406
(for example, operating in SLC, MLC or TLC pattern) and/or multiple physics wipe unit in rewritable nonvolatile memory module
Relative position in 406 etc., different pre-arranged code rules can initially be allocated to different physics erasing units.
Fig. 7 A are the showing come coded data based on pre-arranged code rule according to one example of the present invention embodiment
It is intended to.
Fig. 7 A are refer to, in this exemplary embodiment, physics erasing unit 710 wipes unit as the first physics, and
Each memory cell in physics erasing unit 710 can store 2 positions.Physics erasing unit 710 includes multiple first kind things
Programming unit 701_1~701_n and multiple second class physics programming unit 702_1~702_n are managed, wherein first kind physics programs
Each of unit 701_1~701_n is a lower physics programming unit, and the second class physics programming unit 702_1~
Each of 702_n is a upper physics programming unit.In addition, first kind physics programming unit 701_1 and the second class physics
Programming unit 702_1 is made up of the memory cell in same word line, first kind physics programming unit 701_2 and the second class physics
Programming unit 702_2 is made up of the memory cell in same word line, and first kind physics programming unit 701_n and the second class
Physics programming unit 702_n is made up of the memory cell in same word line, by that analogy.
Memory management circuitry 502 can be that physics wipes the one pre-arranged code rule of configuration of unit 710.This pre-arranged code is advised
Then include being intended to store to first kind physics programming unit to encode based on a default code check by error checking and correcting circuit 508
701_1~701_n data and code check is preset based on identical come encode be intended to store to the second class physics programming unit 702_1~
702_n data.Because the code check for coded data is all identical (that is, default code check), be stored to each first
User's data and odd and even data in the coded data of class physics programming unit and each the second class physics programming unit
Ratio is also all identical.For example, user's data for being stored in first kind physics programming unit 701_n and odd and even data
Ratio meets this default code check, and the user's data and odd and even data being stored in the second class physics programming unit 702_n
Ratio also comply with this default code check, as shown in Figure 7 A.It is noted that user's data and the ratio of odd and even data are
Refer to the ratio of data volume.
With the usage time increase of memory storage apparatus 10, the data read from the first physics erasing unit can include
Increasing mistake.Memory management circuitry 502 can obtain the false assessment information of the first physics erasing unit and according to this
False assessment information, wipe unit for the first physics and configure another coding rule (hereinafter also referred to the first coding rule).This is wrong
Assessing information by mistake may include any information relevant with the usage degree of the first physics erasing unit and/or error generation rate.Example
Such as, this false assessment information may include the first physics erasing unit write-in number, the first physics erasing unit reading times,
The erasing times of first physics erasing unit, the first physics wipe the bit error rate of one or more physics programming units in unit
Or the combination of above- mentioned information.
Fig. 7 B are the showing come coded data based on the first coding rule according to one example of the present invention embodiment
It is intended to.
Fig. 7 B are refer to, after memory storage apparatus 10 is using a period of time, according to first kind physics programming unit
The bit error rate of 701_1~701_n bit error rate and/or second class physics programming unit 702_1~702_n, memory pipe
It can be that physics wipes one the first coding rule of configuration of unit 710 to manage circuit 502.This first coding rule includes being based on a code check
(hereinafter also referred to the first code check) is intended to store to each of first kind physics programming unit 701_1~701_n's to encode
Data and based on another code check (hereinafter also referred to the second code check) come encode be intended to store to the second class physics programming unit 702_1~
Each of 702_n data, wherein the value of the first code check is more than the value of default code check, and the value of the second code check is less than in advance
If the value of code check.
Because the value of the first code check is more than the value of default code check, each first kind physics programming unit is stored in Fig. 7 B
The data volumes of user's data can be more than user's data that each first kind physics programming unit is stored in Fig. 7 A
Data volume, and the data volume that the odd and even data of each first kind physics programming unit is stored in Fig. 7 B can be less than in Fig. 7 A
It is stored in the data volume of the odd and even data of each first kind physics programming unit.Further, since the value of the second code check is less than in advance
If the value of code check, the data volume of user's data of each the second class physics programming unit is stored in Fig. 7 B can be less than Fig. 7 A
In be stored in each the second class physics programming unit user's data data volume, and be stored in Fig. 7 B each
The data volume of the odd and even data of two class physics programming units, which can be more than in Fig. 7 A, is stored in each second class physics programming unit
Odd and even data data volume.
In an exemplary embodiment, the summation of the value of the first code check and the value of the second code check can be equal to the value of default code check
Two times.Because the reliability of first kind physics programming unit is higher than the reliability of the second class physics programming unit, therefore, by carrying
High first code check simultaneously reduces the second code check, can not reduce the total amount of data for the data that the first physics erasing unit can store
Under the premise of, extend the life-span that the first physics wipes unit.By taking Fig. 7 B as an example, even if from the second class physics programming unit 702_1~
Increasing mistake is included in the data that any one of 702_n is read, (that is, increase is stored in by reducing the second code check
The data volume of parity bit in each second class physics programming unit), this little mistake has bigger probability to be corrected.By
This, the time point that physics erasing unit 710 is considered as bad block can be delayed by.
Fig. 8 A be according to another example of the present invention embodiment based on pre-arranged code rule come coded data
Schematic diagram.
Fig. 8 A are refer to, in this exemplary embodiment, physics erasing unit 810 wipes unit as the first physics, and
Each memory cell in physics erasing unit 810 can store 3 bits.Physics erasing unit 810 includes multiple first kind
Physics programming unit 801_1~801_n, multiple second class physics programming unit 802_1~802_n and multiple 3rd class physics
Programming unit 803_1~803_n, wherein each of first kind physics programming unit 801_1~801_n are a lower physics
Each of programming unit, second class physics programming unit 802_1~802_n is a upper physics programming unit, and the
Each of three class physics programming unit 803_1~803_n are an extra physics programming unit.In addition, first kind physics
Programming unit 801_1, the second class physics programming unit 802_1 and the 3rd class physics programming unit 803_1 are by same word line
Memory cell composition；First kind physics programming unit 801_n, the second class physics programming unit 802_n and the 3rd class physics are compiled
Cheng Danyuan 803_n are made up of the memory cell in same word line, by that analogy.
At the initial stage that uses of memory storage apparatus 10, memory management circuitry 502 can be that physics erasing unit 810 configures
One pre-arranged code rule.This pre-arranged code rule includes being based on the default code check of identical by error checking and correcting circuit 508
To encode the data for being intended to store to physics each the physics programming unit wiped in unit 810, as shown in Figure 8 A.
Fig. 8 B be according to another example of the present invention embodiment based on the first coding rule come coded data
Schematic diagram.
Fig. 8 B are refer to, after memory storage apparatus 10 is using a period of time, according to first kind physics programming unit
The bit error rate, and/or the 3rd class thing of 801_1~801_n bit error rate, second class physics programming unit 802_1~802_n
Programming unit 803_1~803_n bit error rate is managed, memory management circuitry 502 can be that physics wipes the configuration of unit 810 one
First coding rule.This first coding rule includes being intended to store to first kind physics programming unit to encode based on the first code check
Each of 801_1~801_n data, based on the second code check it is intended to store to the second class physics programming unit 802_ to encode
Each of 1~802_n data and it is intended to store to encode based on another code check (hereinafter also referred to third yard rate)
Each of three class physics programming unit 803_1~803_n data, wherein the value of the first code check is more than default code check
Value, and the value of the second code check is less than the value of default code check.In an exemplary embodiment, the value of the first code check, second code check
The summation of the value of value and third yard rate can be equal to three times of the value of default code check.In an exemplary embodiment, the value of third yard rate
The value of default code check can be equal to.However, in another exemplary embodiment, the value of third yard rate may also be not equal to default code check
Value, but change with the value of the first code check and/or the second code check.
It is noted that although Fig. 7 A, Fig. 7 B, Fig. 8 A and Fig. 8 B are to wipe one or more in unit according to the first physics
The bit error rate of physics programming unit determines the first coding rule, the first code check, the second code check and/or third yard rate, another
In one exemplary embodiment, other kinds of false assessment information also can be used to determine the first coding rule, the first code check, second code
Rate and/or third yard rate.For example, in a Fig. 8 A and Fig. 8 B exemplary embodiment, it is " 0.889 " to preset code check.When the second class
When physics programming unit 802_2 erasing times increase is " 1750 ", the coding rule of unit 810 is wiped by more corresponding to physics
Newly for the first coding rule and the first code check, the second code check and third yard rate be respectively set to " 0.903 ", " 0.875 " and
“0.889”.Then, when it is " 2000 " that the second class physics programming unit 802_2 erasing times, which further increase, corresponding to thing
The coding rule of reason erasing unit 810 be correspondingly updated to another first coding rule and the first code check, the second code check and
Third yard rate is updated to " 0.917 ", " 0.861 " and " 0.889 ".For example, the second class physics programming unit 802_2 erasing time
Number can be input to a look-up table, and according to the output of this look-up table, the first code check, the second code check and third yard rate after renewal
At least within one can be obtained.It is with the wiping of a second class physics programming unit in addition, in above-mentioned exemplary embodiment
Except trigger condition of the number increase " 150 " as the coding rule for updating corresponding physics erasing unit.Implement in other examples
In example, other trigger conditions may correspond to different false assessment information and set, for example, some second class physics
The bit error rate of programming unit increases preset value etc., so as to control the time point of renewal present encoding rule.
In an exemplary embodiment, the pre-arranged code rule for the first physics erasing unit can be used for a prolonged period to first
The false assessment information of some physics programming unit meets a preparatory condition in physics erasing unit.When this physics programming unit
False assessment information when meeting this preparatory condition, the first coding rule can just be configured to the first physics erasing unit.For example,
In Fig. 8 A and Fig. 8 B an exemplary embodiment, the second class physics programming unit 802_2 erasing times reach " 1500 " it
Before, default code check can be persistently used for encoding any to be stored to the data of physics erasing unit 810；And compiled in the second class physics
After Cheng Danyuan 802_2 erasing times reach " 1500 ", the first code check, the second code check and third yard rate can be determined and by
It is allocated to the physics programming unit of respective type in physics erasing unit 910.In addition, Fig. 7 A, Fig. 7 B, Fig. 8 A and Fig. 8 B example
Embodiment can be applied to any one physics erasing unit that data storage is can be used in Fig. 6.
Fig. 9 is the schematic diagram of the error checking and correcting circuit according to one example of the present invention embodiment.
Fig. 9 is refer to, in an exemplary embodiment, error checking includes code rate selection device 901 with compiling with correcting circuit 508
Code circuit 902, wherein code rate selection device 901 are connected to coding circuit 902.As user's data Data to be encoded, code check choosing
User's data Data and corresponding system information SI can be received by selecting device 901.For example, this user's data Data believes with system
Breath SI is mutually matched.System information SI can indicate that user's data Data is to be stored to belonging to the erasing of which physics
Which physics programming unit of unit.According to system information SI, code rate selection device 901 can be compiled according to being currently configured to this physics
The coding rule of physics erasing unit belonging to Cheng Danyuan determines a code check parameter Para, and wherein code check parameter Para can be right
Should be to a specific code check.According to code check parameter Para, coding circuit 902 can encode user's data based on this specific code check
Data simultaneously exports the coded data Data_Encoded for meeting this specific code check.By taking Fig. 8 B as an example, if user's data Data
Default is to be stored to the second class physics programming unit 802_2, based on the second code check come after encoding user's data Data,
Caused coded data Data_Encoded (including user's data Data and corresponding odd and even data) can be stored to
Second class physics programming unit 802_2.
In another exemplary embodiment, system information SI can also include compiling to store user's data Data physics
Cheng Danyuan false assessment information.According to this false assessment information, code rate selection device 901 can be compiled according to being currently configured to this physics
The coding rule of physics erasing unit belonging to Cheng Danyuan is inquired about the code check corresponding to this physics programming unit and exported corresponding
Coding parameter Para.By taking Fig. 8 B as an example, if it is to be stored to the second class physics programming unit that user's data Data is default
802_1, code rate selection device 901 can inquire about the second class physics programming unit 802_ under the first coding rule according to system information SI
1 is to correspond to the second code check and export corresponding coding parameter Para.According to this coding parameter Para, coding circuit 902 can base
Encode user's data Data in the second code check and produce coded data Data_Encoded.
Figure 10 is the flow chart of the storage management method according to one example of the present invention embodiment.
Figure 10 is refer to, in step S1001, unit is wiped for the first physics and configures pre-arranged code rule, wherein described
Pre-arranged code rule includes compiling to encode to be intended to store to the first kind physics for belonging to the first physics erasing unit based on default code check
Cheng Danyuan data are simultaneously programmed based on default code check to encode to be intended to store to the second class physics for belonging to the first physics erasing unit
The data of unit.In step S1002, the false assessment information of the first physics erasing unit is obtained.In the step s 1003, root
According to the false assessment information of the first physics erasing unit, wipe unit for the first physics and configure the first coding rule, wherein first
Coding rule includes programming list based on the first code check to encode to be intended to store to the first kind physics for belonging to the first physics erasing unit
The data of member simultaneously encode the second class physics programming unit for being intended to store to the first physics erasing unit is belonged to based on the second code check
Data, wherein the value of the first code check is more than the value of default code check, and the value of the second code check is less than the value of default code check.In step
After rapid S1003, if meeting the trigger condition of renewal coding rule, step S1002 can be repeatedly executed.By dynamically adjusting
The coding rule of whole first physics erasing unit, the life-span of the first physics erasing unit can be extended.
However, each step has described in detail as above in Figure 10, just repeat no more herein.It is it is worth noting that, each in Figure 10
Step can be implemented as multiple procedure codes or circuit, and the present invention is not any limitation as.In addition, more than Figure 10 method can arrange in pairs or groups
Exemplary embodiment is used, and can also be used alone, and the present invention is not any limitation as.
In summary, the coding rule corresponding to specific physics erasing unit can be automatically updated in the present invention.By control
Belong to the code check of the physics programming unit of multiple types of specific physics erasing unit, the life-span of this specific physics erasing unit can
To be extended.Thereby, the life-span of memory storage apparatus can also be extended.
Although the present invention is disclosed as above with embodiment, so it is not limited to the present invention, any art
Middle those of ordinary skill, without departing from the spirit and scope of the present invention, when a little change and retouching can be made, in the present invention
In the range of.
Claims (21)
1. a kind of storage management method, for including the rewritable nonvolatile memory module of multiple physics erasing unit,
Characterized in that, the storage management method includes：
The first physics in unit is wiped for the multiple physics and wipes unit configuration pre-arranged code rule, wherein the default volume
Code rule includes encoding the first kind physics programming for being intended to store to the first physics erasing unit is belonged to based on default code check
The data of unit simultaneously encode the second class thing for being intended to store to the first physics erasing unit is belonged to based on the default code check
Manage the data of programming unit；
Obtain the false assessment information of the first physics erasing unit；
The false assessment information of unit is wiped according to first physics, unit configuration first is wiped for first physics
Coding rule, wherein first coding rule includes being intended to store to belonging to the first physics wiping to encode based on the first code check
Except the first kind physics programming unit of unit data and be intended to store to encode to belonging to described first based on the second code check
The data of the second class physics programming unit of physics erasing unit,
The value of wherein described first code check is more than the value of the default code check, wherein the value of the second code rate is less than described preset
The value of code check.
2. storage management method according to claim 1, it is characterised in that under the first kind physics programming unit is
Physics programming unit, and the second class physics programming unit is upper physics programming unit.
3. storage management method according to claim 1, it is characterised in that the value of first code check and described second
The summation of the value of code check is equal to two times of the value of the default code check.
4. storage management method according to claim 1, it is characterised in that the pre-arranged code rule also includes being based on
The default code check is intended to store to the data for the 3rd class physics programming unit for belonging to the first physics erasing unit to encode,
Wherein described first coding rule also includes wiping to encode to be intended to store to belonging to first physics based on third yard rate
The data of the 3rd class physics programming unit of unit,
The summation of the value of the value of wherein described first code check, the value of second code check and the third yard rate is equal to described default
Three times of the value of code check.
5. storage management method according to claim 4, it is characterised in that under the first kind physics programming unit is
Physics programming unit, the second class physics programming unit is upper physics programming unit, and the 3rd class physics programming is single
Member is extra physics programming unit.
6. storage management method according to claim 4, it is characterised in that the value of the third yard rate is equal to described pre-
If the value of code check.
7. storage management method according to claim 1, it is characterised in that unit is wiped according to first physics
The false assessment information, wiping the step of unit configures first coding rule for first physics includes：
According to the first kind physics programming unit for belonging to the first physics erasing unit or belong to the first physics wiping
First code check and second code check are determined except the bit error rate of the second class physics programming unit of unit.
A kind of 8. memory storage apparatus, it is characterised in that including：
Connecting interface unit, to be connected to host computer system；
Rewritable nonvolatile memory module, including multiple physics erasing unit；And
Memorizer control circuit unit, the connecting interface unit and the rewritable nonvolatile memory module are connected to,
Wherein described memorizer control circuit unit wipes unit to the first physics wiped for the multiple physics in unit
Pre-arranged code rule is configured, wherein pre-arranged code rule includes being intended to store to belonging to described the to encode based on default code check
The data of the first kind physics programming unit of one physics erasing unit are simultaneously intended to store to belonging to based on the default code check to encode
The data of second class physics programming unit of the first physics erasing unit,
Wherein described memorizer control circuit unit more to obtain the false assessment information of first physics erasing unit,
Wherein described memorizer control circuit unit is more believed to wipe the false assessment of unit according to first physics
Breath, wipe unit for first physics and configure the first coding rule, wherein first coding rule includes being based on first yard
Rate is intended to store to the data for the first kind physics programming unit for belonging to the first physics erasing unit and be based on to encode
Second code check is intended to store to the data for the second class physics programming unit for belonging to the first physics erasing unit to encode,
The value of wherein described first code check is more than the value of the default code check, wherein the value of the second code rate is less than described preset
The value of code check.
9. memory storage apparatus according to claim 8, it is characterised in that under the first kind physics programming unit is
Physics programming unit, and the second class physics programming unit is upper physics programming unit.
10. memory storage apparatus according to claim 8, it is characterised in that the value of first code check and described the
The summation of the value of two code checks is equal to two times of the value of the default code check.
11. memory storage apparatus according to claim 8, it is characterised in that the pre-arranged code rule also includes base
It is intended to store to the number for the 3rd class physics programming unit for belonging to the first physics erasing unit to encode in the default code check
According to,
Wherein described first coding rule also includes wiping to encode to be intended to store to belonging to first physics based on third yard rate
The data of the 3rd class physics programming unit of unit,
The summation of the value of the value of wherein described first code check, the value of second code check and the third yard rate is equal to described default
Three times of the value of code check.
12. memory storage apparatus according to claim 11, it is characterised in that the first kind physics programming unit is
Lower physics programming unit, the second class physics programming unit is upper physics programming unit, and the 3rd class physics programs
Unit is extra physics programming unit.
13. memory storage apparatus according to claim 11, it is characterised in that the value of the third yard rate is equal to described
The value of default code check.
14. memory storage apparatus according to claim 8, it is characterised in that the memorizer control circuit unit root
According to the false assessment information of first physics erasing unit, wipe unit configuration described first for first physics and compile
The operation of code rule includes：
According to the first kind physics programming unit for belonging to the first physics erasing unit or belong to the first physics wiping
First code check and second code check are determined except the bit error rate of the second class physics programming unit of unit.
15. a kind of memorizer control circuit unit, the rewritable nonvolatile that multiple physics erasing units are included for controlling is deposited
Memory modules, it is characterised in that the memorizer control circuit unit includes：
HPI, to be connected to host computer system；
Memory interface, to be connected to the rewritable nonvolatile memory module；
Error checking and correcting circuit；And
Memory management circuitry, the HPI, the memory interface and the error checking and correcting circuit are connected to,
Wherein described memory management circuitry wipes unit to wipe the first physics in unit for the multiple physics
Pre-arranged code rule is configured, wherein pre-arranged code rule includes being based on default code check by the error checking and correcting circuit
It is intended to store to the data for the first kind physics programming unit for belonging to the first physics erasing unit and based on described pre- to encode
If code check is intended to store to the data for the second class physics programming unit for belonging to the first physics erasing unit to encode,
Wherein described memory management circuitry more to obtain the false assessment information of first physics erasing unit,
Wherein described memory management circuitry more to according to first physics wipe unit the false assessment information, be
First physics erasing unit configures the first coding rule, wherein first coding rule include by the error checking with
Correcting circuit is compiled based on the first code check to encode to be intended to store to the first kind physics for belonging to the first physics erasing unit
Cheng Danyuan data simultaneously encode second class for being intended to store to the first physics erasing unit is belonged to based on the second code check
The data of physics programming unit,
The value of wherein described first code check is more than the value of the default code check, wherein the value of the second code rate is less than described preset
The value of code check.
16. memorizer control circuit unit according to claim 15, it is characterised in that the first kind physics programming is single
Member is lower physics programming unit, and the second class physics programming unit is upper physics programming unit.
17. memorizer control circuit unit according to claim 15, it is characterised in that the value of first code check and institute
The summation for stating the value of the second code check is equal to two times of value of the default code check.
18. memorizer control circuit unit according to claim 15, it is characterised in that the pre-arranged code rule is also wrapped
Include and the default code check is based on by the error checking and correcting circuit be intended to store to encode to belonging to the first physics erasing
The data of 3rd class physics programming unit of unit,
Wherein described first coding rule also includes being intended to deposit to encode based on third yard rate with correcting circuit by the error checking
Store up to the data for the 3rd class physics programming unit for belonging to the first physics erasing unit,
The summation of the value of the value of wherein described first code check, the value of second code check and the third yard rate is equal to described default
Three times of the value of code check.
19. memorizer control circuit unit according to claim 18, it is characterised in that the first kind physics programming is single
Member is lower physics programming unit, and the second class physics programming unit is upper physics programming unit, and the 3rd class physics
Programming unit is extra physics programming unit.
20. memorizer control circuit unit according to claim 18, it is characterised in that the value of the third yard rate is equal to
The value of the default code check.
21. memorizer control circuit unit according to claim 15, it is characterised in that the memory management circuitry root
According to the false assessment information of first physics erasing unit, wipe unit configuration described first for first physics and compile
The operation of code rule includes：
According to the first kind physics programming unit for belonging to the first physics erasing unit or belong to the first physics wiping
First code check and second code check are determined except the bit error rate of the second class physics programming unit of unit.
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