CN107632957A - A kind of calculating acceleration system and its accelerated method based on large-scale F PGA chips - Google Patents
A kind of calculating acceleration system and its accelerated method based on large-scale F PGA chips Download PDFInfo
- Publication number
- CN107632957A CN107632957A CN201710813770.1A CN201710813770A CN107632957A CN 107632957 A CN107632957 A CN 107632957A CN 201710813770 A CN201710813770 A CN 201710813770A CN 107632957 A CN107632957 A CN 107632957A
- Authority
- CN
- China
- Prior art keywords
- data
- fpga
- calculating
- server
- accelerator card
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a kind of calculating acceleration system and its accelerated method based on large-scale F PGA chips, the acceleration system that calculates includes server and the FPGA being connected with server calculating accelerator cards；The server, the result data obtained after accelerator card speed-up computation is calculated to FPGA calculating accelerator cards, and for reading the FPGA for sending data to be calculated；The FPGA calculates accelerator card, data to be calculated for being sent using server carry out corresponding speed-up computation, obtain the result data, designed by the acceleration of hardware description language, it is converted into the soft cores of ip, the hardware logic electric circuit of high concurrent is realized finally by large-scale F PGA chips, realizes and calculates acceleration.It the advantage is that and provide a kind of more common low energy consumption, high performance new calculating accelerated method.
Description
Technical field
The invention belongs to calculate acceleration technique field, more particularly to a kind of calculating based on large-scale F PGA chips accelerates system
System and its accelerated method.
Background technology
Currently the operand in fields such as genetic engineering, weather forecast, oil exploration, seismic studies increasingly increases.Can be with
, it is envisioned that the calculating demand in these following fields will be increasing, this just accelerates to propose higher requirement to calculating.Current
Calculate accelerated method and be broadly divided into three kinds：PC cluster accelerates, the parallel computation based on GPU accelerates and the restructural based on FPGA
Calculate and accelerate.
PC cluster（Cluster Computing）
Cluster is the parallel or distributed system that the computer being mutually connected to each other by some is formed.Server cluster system
System generally be exactly multiple servers are got up by high-speed traffic link connection, externally come, these servers just as
One server is working, and internally for, outside come load these Node stations are dynamically allocated into by certain mechanism
In, so as to reach high-performance, the High Availabitity that superserver just has.Clustering is a kind of relatively new technology, is passed through
Clustering, the of a relatively high receipts in terms of performance, reliability, flexibility can be being obtained in the case of paying lower cost
Benefit.At present, in the supercomputer being currently running all over the world, many is all realized using Clustering.
GPU（Graphics Processing Unit）, i.e. graphics processor, it is that one kind exclusively carries out image operation work
Microprocessor.Nowadays GPU as coprocessor it is a kind of turn into the present age calculate acceleration system important component it
One, it is the current main method for calculating and accelerating.From NVIDIA in 1999 will since first GPU is introduced to the market in the world,
GPU is developed rapidly, and its function develops into high-speed parallel from single figure shows and calculated in short ten years（GPGPU,
General Purpose GPU, i.e. general-purpose computations GPU）.The Heterogeneous Computing pattern being made up of CPU+GPU, because its is excellent
Power dissipation ratio of performance, it is widely deployed in engineering fields such as physics simulation, molecular dynamics, earthquake simulations.
FPGA（Field-Programmable Gate Array）, i.e. field programmable gate array, it is by by can
Program the semiconductor devices that configurable logic block (CLB) matrix of mutual downlink connection is formed.Reconfigurable Computation
（Reconfigurable Computing）Technology refers under software control, using the reusable resource in system, according to
Application need reconfigure a new calculating platform, reach close to specialized hardware design high-performance.
Restructurable computing system based on FPGA accelerates to be a kind of new side to find application in engineering calculation at present
Method, suitable for most computation-intensive and data-intensive application, such as financial calculating, cryptography, life science, oil
Exploration, big data processing etc..It realizes the more preferable operational efficiency to application-specific, i.e. duration performance by hardware optimization
The value closer to peak value operational performance can be reached, while FPGA Energy Efficiency Ratio is higher compared with GPU and CPU, is a kind of emerging
Promising calculating accelerated method.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of new FPGA for the deficiency of background technology and can weigh
Structure, highdensity calculating acceleration system and its accelerated method based on large-scale F PGA chips.
The present invention uses following technical scheme to solve above-mentioned technical problem
A kind of calculating acceleration system based on large-scale F PGA chips, the FPGA meters being connected comprising server and with the server
Calculate accelerator card；
The server, for sending data to be calculated to FPGA calculating accelerator cards, and based on reading the FPGA
Calculate the result data obtained after accelerator card speed-up computation；
The FPGA calculates accelerator card, and the data to be calculated for being sent using server carry out corresponding speed-up computation, obtain
The result data.
As a kind of further preferred scheme of the calculating acceleration system based on large-scale F PGA chips of the present invention, the clothes
Business device includes power module, data distribution and recycling module, interface module, accelerating module and corresponding distribution of services module；
Wherein, power module, for providing electric energy needed for server；
Data distribution and recycling module, for distributing and data collection result of calculation；
Interface module, carry out data transmission for calculating accelerator card with FPGA：By sending data to be calculated to based on the FPGA
Accelerator card is calculated, and the result data after FPGA calculating accelerator card speed-up computations is transmitted to server；
Accelerating module and corresponding distribution of services module, for accelerating the distribution and recovery of processing data.
It is described as a kind of further preferred scheme of the calculating acceleration system based on large-scale F PGA chips of the present invention
FPGA calculates accelerator card and includes data communication interface, 12 fpga chips and connected one to one respectively with the fpga chip
Memory；
The data communication interface, for carrying out data transmission with server：The data to be calculated sent for the reception server,
And the result data calculated FPGA after accelerator card speed-up computation is transmitted to server；
The fpga chip, the data to be calculated sent for speed-up computation server；
The memory, after the data to be calculated of storage server transmission, and FPGA calculating accelerator card speed-up computations
Result data.
It is described to connect as a kind of further preferred scheme of the calculating acceleration system based on large-scale F PGA chips of the present invention
Mouth mold block and data communication interface use PCIe interface.
It is described as a kind of further preferred scheme of the calculating acceleration system based on large-scale F PGA chips of the present invention
Fpga chip uses Xilinx Spartan-6 chips.
It is described to deposit as a kind of further preferred scheme of the calculating acceleration system based on large-scale F PGA chips of the present invention
Reservoir uses DDR3.
A kind of calculating accelerated method based on large-scale F PGA chips, is specifically comprised the following steps；
Step 1, the data for needing speed-up computation are analyzed；
Step 2, the accelerating part of pending data is extracted, and designs and accelerates the soft cores of ip；
Step 3, communication mode and data format are designed；
Step 4, pending data is transmitted to FPGA and calculates accelerator card FPGA by several data formats of communication modes being related to step 3
Accelerator card, and then complete the speed-up computation of data.
As the present invention it is a kind of based on fpga chip calculating accelerated method further preferred scheme, in step 2, if
Meter accelerates the soft cores of ip to be completed especially by following two methods：When the multistage flowing water accelerating algorithm of design, second, design multinuclear increases
Add the utilization rate of fpga chip.
The present invention compared with prior art, has following technique effect using above technical scheme：
1. high-performance：FPGA hardware accelerating circuit logical capacity of the present invention is big, speed is fast, degree of parallelism is high, operational capability
By force, acceleration effect is notable, and so that DES keys travel through speed as an example, every kilowatt of speed reaches for 657,900,000,000/second；
2. low-power consumption, high performance-price ratio：In FPGA, CPU, GPU three, FPGA every kilowatt of consumed power operational performance highest, so
Its is least in power-consuming for identical performance, and compared to traditional calculations, FPGA low energy consumption high-performance calculation is with the obvious advantage；
3. relative to general server cluster（Or cloud computing）, GPU arrays, the cost of the FPGA solutions of same performance
Typically want low more, therefore the present invention has very high cost performance.
Brief description of the drawings
Fig. 1 is DES decoding algorithm flow charts；
Fig. 2 is working method schematic diagram of the present invention；
Fig. 3 is the system construction drawing of the present invention；
Fig. 4 is the hardware structure diagram that FPGA calculates accelerator card；
Fig. 5 a are server machine frame pictorial diagrams；
Fig. 5 b are server board pictorial diagrams；
Fig. 6 is shown as the server connection diagram of working method of the present invention.
Embodiment
Technical scheme is described in further detail below in conjunction with the accompanying drawings：
A kind of calculating acceleration system based on large-scale F PGA chips, the FPGA meters being connected comprising server and with the server
Calculate accelerator card；
The server, for sending data to be calculated to FPGA calculating accelerator cards, and based on reading the FPGA
Calculate the result data obtained after accelerator card speed-up computation；
The FPGA calculates accelerator card, and the data to be calculated for being sent using server carry out corresponding speed-up computation, obtain
The result data.
The server includes power module, data distribution and recycling module, interface module, accelerating module and corresponding
Distribution of services module；
Wherein, power module, for providing electric energy needed for server；
Data distribution and recycling module, for distributing and data collection result of calculation；
Interface module, carry out data transmission for calculating accelerator card with FPGA：By sending data to be calculated to based on the FPGA
Accelerator card is calculated, and the result data after FPGA calculating accelerator card speed-up computations is transmitted to server；
Accelerating module and corresponding distribution of services module, for accelerating the distribution and recovery of processing data；
The FPGA calculates accelerator card and includes data communication interface, more fpga chips and distinguish one by one with the fpga chip
The memory of corresponding connection；The interface module and data communication interface can use Pcle interfaces, and the fpga chip can be adopted
With Xilinx Spartan-6 chips, the memory can use DDR3 chips.More fpga chips are minimum two.
The data communication interface, for carrying out data transmission with server：Sent for the reception server to be calculated
Data, and the result data after FPGA calculating accelerator card speed-up computations is transmitted to server；
The fpga chip, the data to be calculated sent for speed-up computation server；
The memory, after the data to be calculated of storage server transmission, and FPGA calculating accelerator card speed-up computations
Result data.
Specific embodiment is as follows：
High-performance restructural server of the present invention includes 10 pieces of FPGA and calculates card, and every piece contains 12 Xilinx
Spartan-6 chips, totally 120,10 pieces of boards can be with flexible configuration；Every fpga chip is all equipped with 512MB DRAM internal memories；
Monolithic calculates card power and reaches 120 watts, and complete machine power is 1475 watts；Data communication interface is made an excuse using USB3.0, also optional
PCIe interface；Machine physical size is standard 6U cabinets；Cluster working method is supported, 10 pieces of a set of equipment calculates card, Ke Yiduo
Complete equipment concurrent working, performance linear enhancing.
In use, the system is mainly responsible for dedicated computing, and it must be controlled by other main frames.One host can be with
Control multiple servers.Communicated between main frame and server by USB (or PCIe) interface.Host computer side provides java, c++
Language api interface interacts with foundation stone server, to load the soft cores of IP, control, state-detection and data transfer etc..
Server is connected on Linux Host by USB, you can use the system.Mainly there are two kinds of occupation modes,
A kind of is the big data application for having had exploitation to finish（Electric power big data calculates application）, run directly on Host,
Host can give calculating task to high-performance calculation platform automatically and calculate.For the first occupation mode, the ring after being pre-configured with
Behind border, the software for the electric power big data specially developed directly is run on Host.
Also a kind of occupation mode is directly to use the API of bottom, carries out various application and developments.This occupation mode uses
SDK, direct maneuvering calculation acceleration system.More suitable for there is the unit of special research staff.
One kind is introduced below in conjunction with the accompanying drawings realizes that DES decrypts accelerated method using the present invention：
DES（Data Encryption Standard）It is the earliest most widely used packet symmetric encipherment algorithm of invention.DES
The suction parameter of algorithm has three：Key、Data、Mode.Wherein Key is 8 bytes totally 64, is that the work of DES algorithms is close
Key；Data is also 8 bytes 64, is data to be encrypted or decrypted；Mode is DES working method, there is two kinds：Add
Close or decryption.
Keys and additional 8 bit parity check positions of the DES using one 56, produce maximum 64 point
Group size.This is the block cipher of an iteration, using referred to as Feistel technology, wherein the text block of encryption is divided into
Two halves., then will output and second half progress nonequivalence operation using sub-key to wherein half application circulatory function；Then hand over
This two halves is changed, this process may proceed to down, but last circulation does not exchange.DES is using 16 circulations, using XOR,
Displacement, replacement, four kinds of basic operations of shifting function.
Fig. 1 is that DES decrypts flow chart.
Acceleration design is carried out to DES decipherment algorithms underneath with the present invention：
1st, to needing to accelerate DES decipherment algorithms to analyze.
2nd, accelerating part is extracted, design accelerates the soft cores of ip.Mainly realized and accelerated by two methods, first, design multilevel flow
Water accelerating algorithm；Second, design multinuclear increase FPGA utilization rate.
3rd, according to hardware interface design communication mode and data format.
4th, FPGA speed-up computation results are integrated, complete the design that algorithm accelerates.
The present invention is accelerated using FPGA hardware, and the accelerating algorithm that design is completed, this working method can be directly manipulated by SDK
Principle is as shown in Figure 2.Overall system architecture figure is as shown in Figure 3.
In general, decrypt performance and the FPGA calculating card quantity contained by equipment is linearly directly proportional, calculate and block more times
It is shorter.High-performance server of the present invention includes 10 pieces of FPGA and calculates card, and every piece contains 12 Xilinx Spartan-6 cores
Piece, totally 120,10 pieces of boards can be with flexible configuration；Single-chip FPGA（Spartan 6）Crack speed and reach 80.6 hundred million times/second.
Hardware configuration is as shown in Figure 4.The restructural server machine frame and restructural server board material object wherein used are respectively as attached
Fig. 5 a, shown in 5b.
In addition, the present invention also supports cluster working method, 10 pieces of a set of equipment calculates card, can more parallel works of complete equipment
Make, performance linear enhancing；Cooperateed with and decrypted using more equipment autonomouslies, reduce decryption time at double, support minute level decryption performance.Collection
Group's working method is as shown in Figure 6.By actual measurement, it is 0.9672 × 10 that the DES accelerated by the system, which decrypts speed,12Secondary/second.
Claims (8)
- A kind of 1. calculating acceleration system based on large-scale F PGA chips, it is characterised in that：Comprising server and with the service The FPGA of device connection calculates accelerator card；The server, for sending data to be calculated to FPGA calculating accelerator cards, and based on reading the FPGA Calculate the result data obtained after accelerator card speed-up computation；The FPGA calculates accelerator card, and the data to be calculated for being sent using server carry out corresponding speed-up computation, obtain The result data.
- A kind of 2. calculating acceleration system based on fpga chip according to claim 1, it is characterised in that：The server Include power module, data distribution and recycling module, interface module, accelerating module and corresponding distribution of services module；Wherein, power module, for providing electric energy needed for server；Data distribution and recycling module, for distributing and data collection result of calculation；Interface module, carry out data transmission for calculating accelerator card with FPGA：By sending data to be calculated to based on the FPGA Accelerator card is calculated, and the result data after FPGA calculating accelerator card speed-up computations is transmitted to server；Accelerating module and corresponding distribution of services module, for accelerating the distribution and recovery of processing data.
- A kind of 3. calculating acceleration system based on large-scale F PGA chips according to claim 1, it is characterised in that：It is described FPGA calculates accelerator card and includes data communication interface, 12 fpga chips and connected one to one respectively with the fpga chip Memory；The data communication interface, for carrying out data transmission with server, and by after FPGA calculating accelerator card speed-up computations Result data transmit to server；The fpga chip, the data to be calculated sent for speed-up computation server；The memory, after the data to be calculated of storage server transmission, and FPGA calculating accelerator card speed-up computations Result data.
- A kind of 4. calculating acceleration system based on large-scale F PGA chips according to Claims 2 or 3, it is characterised in that： The interface module and data communication interface use PCIe interface.
- A kind of 5. calculating acceleration system based on large-scale F PGA chips according to claim 3, it is characterised in that：It is described Fpga chip uses Xilinx Spartan-6 chips.
- A kind of 6. calculating acceleration system based on large-scale F PGA chips according to claim 3, it is characterised in that：It is described Memory uses DDR3 chips.
- A kind of 7. calculating accelerated method based on large-scale F PGA chips, it is characterised in that：Specifically comprise the following steps；Step 1, the data for needing speed-up computation are analyzed；Step 2, the accelerating part of pending data is extracted, and designs and accelerates the soft cores of ip；Step 3, communication mode and data format are designed；Step 4, pending data is transmitted to FPGA and calculates accelerator card FPGA by several data formats of communication modes being related to step 3 Accelerator card, and then complete the speed-up computation of data.
- A kind of 8. calculating accelerated method based on fpga chip according to claim 7, it is characterised in that：In step 2, Design accelerates the soft cores of ip to be completed especially by following two methods：When the multistage flowing water accelerating algorithm of design, second, design multinuclear Increase the utilization rate of fpga chip.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710813770.1A CN107632957A (en) | 2017-09-11 | 2017-09-11 | A kind of calculating acceleration system and its accelerated method based on large-scale F PGA chips |
| CN201811048816.6A CN109284250A (en) | 2017-09-11 | 2018-09-10 | A kind of calculating acceleration system and its accelerated method based on large-scale F PGA chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710813770.1A CN107632957A (en) | 2017-09-11 | 2017-09-11 | A kind of calculating acceleration system and its accelerated method based on large-scale F PGA chips |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107632957A true CN107632957A (en) | 2018-01-26 |
Family
ID=61101184
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710813770.1A Pending CN107632957A (en) | 2017-09-11 | 2017-09-11 | A kind of calculating acceleration system and its accelerated method based on large-scale F PGA chips |
| CN201811048816.6A Pending CN109284250A (en) | 2017-09-11 | 2018-09-10 | A kind of calculating acceleration system and its accelerated method based on large-scale F PGA chip |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811048816.6A Pending CN109284250A (en) | 2017-09-11 | 2018-09-10 | A kind of calculating acceleration system and its accelerated method based on large-scale F PGA chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN107632957A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108921767A (en) * | 2018-06-06 | 2018-11-30 | 国网四川省电力公司信息通信公司 | A kind of image digital watermark processing system and its processing method based on FPGA |
| CN109062858A (en) * | 2018-08-01 | 2018-12-21 | 郑州云海信息技术有限公司 | A kind of FPGA accelerator card based on Xilinx XCVU37P chip |
| CN109739833A (en) * | 2018-12-18 | 2019-05-10 | 山东超越数控电子股份有限公司 | A kind of Domestic Platform database accelerator system and method based on FPGA |
| CN111884952A (en) * | 2020-07-06 | 2020-11-03 | 华东师范大学 | Multichannel calculation accelerating equipment based on FPGA |
| CN113822003A (en) * | 2021-11-24 | 2021-12-21 | 南京集成电路设计服务产业创新中心有限公司 | FPGA-based static timing analysis delay calculation acceleration system and method |
| CN116561051A (en) * | 2023-04-10 | 2023-08-08 | 中科驭数（北京）科技有限公司 | Hardware acceleration card and heterogeneous computing system |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110490300B (en) * | 2019-07-26 | 2022-03-15 | 苏州浪潮智能科技有限公司 | Deep learning-based operation acceleration method, device and system |
| CN113673704B (en) * | 2021-07-05 | 2022-07-01 | 中国电子科技集团公司第十五研究所 | Relational network reasoning optimization method based on software and hardware cooperative acceleration |
| CN114968886B (en) * | 2022-07-27 | 2022-10-25 | 中科亿海微电子科技（苏州）有限公司 | Reconfigurable financial acceleration card based on double FPGA, reconfigurable method and acceleration method |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080222417A1 (en) * | 2007-03-06 | 2008-09-11 | James Downes | Method, System, And Apparatus For Nested Security Access/Authentication With Media Initiation |
| CN102377754A (en) * | 2010-08-20 | 2012-03-14 | 上海海加网络科技有限公司 | Secure socket layer virtual private network (SSL VPN) realization method based on parallel encryption and decryption calculation of FDP250K-II field programmable gate array (FPGA) and central processing unit (CPU) |
| CN104657308A (en) * | 2015-03-04 | 2015-05-27 | 浪潮电子信息产业股份有限公司 | Method for realizing server hardware acceleration by using FPGA (field programmable gate array) |
| CN105824780A (en) * | 2016-04-01 | 2016-08-03 | 浪潮电子信息产业股份有限公司 | Stand-alone multi-FPGA (Field Programmable Gate Array)-based parallel development method |
| CN105956666B (en) * | 2016-04-29 | 2018-09-07 | 浪潮(北京)电子信息产业有限公司 | A kind of machine learning method and system |
| CN106020425A (en) * | 2016-05-27 | 2016-10-12 | 浪潮(北京)电子信息产业有限公司 | FPGA heterogeneous acceleration calculating system |
| CN106528490B (en) * | 2016-11-30 | 2020-02-07 | 郑州云海信息技术有限公司 | FPGA heterogeneous acceleration computing device and system |
| CN106778015A (en) * | 2016-12-29 | 2017-05-31 | 哈尔滨工业大学（威海） | One kind is based on FPGA isomery accelerated gene computational methods in cloud platform |
-
2017
- 2017-09-11 CN CN201710813770.1A patent/CN107632957A/en active Pending
-
2018
- 2018-09-10 CN CN201811048816.6A patent/CN109284250A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108921767A (en) * | 2018-06-06 | 2018-11-30 | 国网四川省电力公司信息通信公司 | A kind of image digital watermark processing system and its processing method based on FPGA |
| CN108921767B (en) * | 2018-06-06 | 2023-06-13 | 国网四川省电力公司信息通信公司 | Image digital watermark processing system and processing method based on FPGA |
| CN109062858A (en) * | 2018-08-01 | 2018-12-21 | 郑州云海信息技术有限公司 | A kind of FPGA accelerator card based on Xilinx XCVU37P chip |
| CN109739833A (en) * | 2018-12-18 | 2019-05-10 | 山东超越数控电子股份有限公司 | A kind of Domestic Platform database accelerator system and method based on FPGA |
| CN111884952A (en) * | 2020-07-06 | 2020-11-03 | 华东师范大学 | Multichannel calculation accelerating equipment based on FPGA |
| CN113822003A (en) * | 2021-11-24 | 2021-12-21 | 南京集成电路设计服务产业创新中心有限公司 | FPGA-based static timing analysis delay calculation acceleration system and method |
| CN116561051A (en) * | 2023-04-10 | 2023-08-08 | 中科驭数（北京）科技有限公司 | Hardware acceleration card and heterogeneous computing system |
| CN116561051B (en) * | 2023-04-10 | 2024-02-02 | 中科驭数（北京）科技有限公司 | Hardware acceleration card and heterogeneous computing system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109284250A (en) | 2019-01-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107632957A (en) | A kind of calculating acceleration system and its accelerated method based on large-scale F PGA chips | |
| Samardzic et al. | F1: A fast and programmable accelerator for fully homomorphic encryption | |
| CN101854353B (en) | Multi-chip parallel encryption method based on FPGA | |
| CN111291859A (en) | Semiconductor circuit for universal matrix-matrix multiplication data stream accelerator | |
| CN106293508B (en) | Data-storage system and method | |
| CN102509036B (en) | Reconfigurable cipher processor and anti-power consumption attach method | |
| CN102073481B (en) | Multi-kernel DSP reconfigurable special integrated circuit system | |
| CN105335331B (en) | A kind of SHA256 realization method and systems based on extensive coarseness reconfigurable processor | |
| US8572407B1 (en) | GPU assist for storage systems | |
| CN100536390C (en) | A novel elliptic curve password coprocessor | |
| Jiang et al. | Fleetrec: Large-scale recommendation inference on hybrid gpu-fpga clusters | |
| CN1481524A (en) | Cryptographic processor | |
| CN105912501A (en) | SM4-128 encryption algorithm implementation method and system based on large-scale coarseness reconfigurable processor | |
| CN102799563A (en) | Reconfigurable computing array and construction method | |
| CN102611951A (en) | Method for reducing power consumption of integrated circuit system of Ethernet passive optical network physical layer | |
| CN102279753A (en) | Method for configuring and managing reconfigurable system and configuration management unit for reconfigurable system | |
| CN111783933A (en) | Hardware circuit design and method for data loading device combining main memory and accelerating deep convolution neural network calculation | |
| CN106775987A (en) | A kind of dispatching method of virtual machine for improving resource efficiency safely in IaaS cloud | |
| CN103701593A (en) | 256-system large number-based Ron Rivest, Adi Shamir and Leonard Adleman (RSA) encryption method | |
| CN105224286B (en) | Buffer storage for restructural cipher processor | |
| CN110890120B (en) | Universal block chain application processing acceleration method and system based on resistive random access memory | |
| CN112988621A (en) | Data loading device and method for tensor data | |
| CN102253920B (en) | Fully-interconnected route structure dynamically-reconfigurable data processing method and processor | |
| CN202183093U (en) | Configuration management unit for reconfigurable system | |
| CN103761213A (en) | On-chip array system based on circulating pipeline computation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20180126 |