CN107613355A - Processing system for video and video processor - Google Patents
Processing system for video and video processor Download PDFInfo
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- CN107613355A CN107613355A CN201710868591.8A CN201710868591A CN107613355A CN 107613355 A CN107613355 A CN 107613355A CN 201710868591 A CN201710868591 A CN 201710868591A CN 107613355 A CN107613355 A CN 107613355A
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Abstract
The embodiment of the invention discloses a kind of processing system for video, including the first video processor and the second video processor, first video processor includes the first pluggable expanding unit and the first back board device, the first pluggable expanding unit is provided with the first connector and the first subtending port, and first back board device is provided with the first video input processing unit interface group, the first video frequency output processing unit interface group, the first expanding unit interface, the first master control set interface and the first matrix switch module；Second video processor includes：Second pluggable expanding unit and the second back board device, the second pluggable expanding unit is provided with the second connector and the second subtending port, and second back board device is provided with the second video input processing unit interface group, the second video frequency output processing unit interface group, the second expanding unit interface, the second master control set interface and the second matrix switch module；Wherein, the second subtending port connects the first subtending port by cable.
Description
Technical field
The present invention relates to Video processing and display technology field, more particularly to a kind of processing system for video and a kind of video
Processor.
Background technology
At present, conventional video processor can be by the video image of different type or form after scan picture
Become digital video signal to be exported with set form, and then the video frequency output is to showing in display device.However, by existing
The limitation of the input/output channel quantity of video processor, single video processor is when handling more input/output signal sources
It has been increasingly difficult to meet demand.
The content of the invention
Embodiments of the invention provide a kind of processing system for video and a kind of video processor, to realize more multi input/defeated
Go out the technique effect of access and the processing of signal source.
On the one hand, a kind of processing system for video provided in an embodiment of the present invention, including：
First video processor, including：
First pluggable expanding unit, is provided with the first connector and the first subtending port；
First back board device, it is provided with the first video input processing unit interface group, the first video frequency output processing unit connects
Mouth group, the first expanding unit interface, the first master control set interface and the first matrix switch module, wherein first matrix switch
Module connects the first video input processing unit interface group, the first video frequency output processing unit interface group, described the
One expanding unit interface and the first master control set interface, the first video input processing unit interface group regard for connection
Frequency input processing device, the first video frequency output processing unit interface group are used to connect video frequency output processing unit, and described the
One master control set interface is used to connect master control set, and the first expanding unit interface connects first connector；
Second video processor, including：
Second pluggable expanding unit, is provided with the second connector and the second subtending port；
Second back board device, it is provided with the second video input processing unit interface group, the second video frequency output processing unit connects
Mouth group, the second expanding unit interface, the second master control set interface and the second matrix switch module, wherein second matrix switch
Module connects the second video input processing unit interface group, the second video frequency output processing unit interface group, described the
Two expanding unit interfaces and the second master control set interface, the second video input processing unit interface group regard for connection
Frequency input processing device, the second video frequency output processing unit interface group are used to connect video frequency output processing unit, and described the
Two master control set interfaces are used to connect master control set, and the second expanding unit interface connects second connector；
Wherein, second subtending port connects first subtending port by cable.
In one embodiment of the invention, formed with data between first connector and first subtending port
Path and control access, relay repeater is provided with the data path, and relay repeater connection described first connects
Plug-in unit and first subtending port.
In one embodiment of the invention, the relay repeater connects described the by serializer/deserializers bus
One connector and first subtending port.
In one embodiment of the invention, first back board device also includes：First network physical layer transceiver group；
Second networked physics layer transceiver group；3rd networked physics layer transceiver group；First PLD, connection described first
Master control set interface, pass through first network physical layer transceiver group connection the first video input processing unit interface
Group, the first video frequency output processing unit interface group is connected by the second networked physics layer transceiver group and passed through
The 3rd networked physics layer transceiver group connects the first expanding unit interface.
In one embodiment of the invention, first PLD also connects including the output of the first control sequential
Mouth group and the second control sequential output interface group, the first control sequential output interface group are connected at first video input
Device interface group is managed, the second control sequential output interface group connects the first video frequency output processing unit interface group.
In one embodiment of the invention, the first matrix switch module passes through multichannel serializer/deserializers bus
Connect the first expanding unit interface.
In one embodiment of the invention, first back board device also includes：Microcontroller circuit, including microcontroller
Device and the memory for connecting the microcontroller；Wherein, the microcontroller connects the first master control set interface, described the
One video input processing unit interface group and the first video frequency output processing unit interface group.
In one embodiment of the invention, first PLD connects institute by storage control bus
State master control set interface, it is each in the first control sequential output interface group and the second control sequential output interface group
Road control sequential output interface is used to export comprising clock signal, data enable signal, line synchronising signal and field sync signal
Timing control signal；The first control sequential output interface group is believed for output multi-channel multisignal source premonitoring with SECO
Number, the second control sequential output interface group is used for the currently playing signal source timing control signal of output multi-channel.
In one embodiment of the invention, first back board device is additionally provided with the first genlock device and described
One synchronous phase locking unit connects the first expanding unit interface；Second backboard is additionally provided with the second genlock device and described
Second genlock device connects the second expanding unit interface.
On the other hand, a kind of video processor provided in an embodiment of the present invention, including：
Pluggable expanding unit, is provided with connector and subtending port；
Back board device, it is provided with video input processing unit interface group, video frequency output processing unit interface group, expanding unit
Interface, master control set interface and matrix switch module, wherein the matrix switch module connects the video input processing unit
Interface group, the video frequency output processing unit interface group, the expanding unit interface and the master control set interface, the video
Input processing device interface group is used to connect video input processing unit, and the video frequency output processing unit interface group is used to connect
Video frequency output processing unit, the master control set interface are used to connect master control set, connect described in the expanding unit interface connection
Plug-in unit；
Wherein, lead between the connector and the subtending port formed with data path and control access, the data
Relay repeater is provided with road, and the relay repeater connects the connector and the subtending port.
In one embodiment of the invention, the back board device also includes：First network physical layer transceiver group；Second
Networked physics layer transceiver group；3rd networked physics layer transceiver group；PLD, connect the master control set and connect
Mouthful, the video input processing unit interface group connected by the first network physical layer transceiver group, passes through described second
Networked physics layer transceiver group connects the video frequency output processing unit interface group and received by the 3rd networked physics layer
Send out device group and connect the expanding unit interface.
In one embodiment of the invention, the PLD also includes the first control sequential output interface group
With the second control sequential output interface group, the first control sequential output interface group connects the video input processing unit and connect
Mouth group, the second control sequential output interface group connect the video frequency output processing unit interface group；During first control
It is used for output bag per control sequential output interface all the way in sequence output interface group and the second control sequential output interface group
Timing control signal containing clock signal, data enable signal, line synchronising signal and field sync signal；First control sequential
Output interface group is used for output multi-channel multisignal source premonitoring timing control signal, and the second control sequential output interface group is used
In the currently playing signal source timing control signal of output multi-channel.
In one embodiment of the invention, the back board device is additionally provided with genlock device and the genlock
Device connects the expanding unit interface.
Above-mentioned technical proposal can have following one or more advantages：By setting pluggable expansion in video processor
Extending apparatus, make to cascade to share information to be formed processing system for video between multiple video processors, be directed to so as to improve
The disposal ability of multi input/signal source output operating mode；Furthermore device is forwarded as data, order using PLD,
And by increasing the data physical channels such as networked physics layer transceiver group, it can reach the purpose of simplify control logic and can be real
Existing point-to-point communication, adds Data Transfer Parallelism, so as to lift properties of product.
Brief description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Accompanying drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill of field, on the premise of not paying creative work, it can also be obtained according to these accompanying drawings other
Accompanying drawing.
Fig. 1 is a kind of structural representation of processing system for video of the embodiment of the present invention；
Fig. 2 is a kind of structural representation of pluggable expanding unit of the embodiment of the present invention；
Fig. 3 is a kind of structural representation of video processor of the embodiment of the present invention；
Fig. 4 is a kind of structural representation of back board device of the embodiment of the present invention；
Fig. 5 is the communication mode schematic diagram of PLD shown in Fig. 4；
Fig. 6 is a kind of structural representation of back board device of another embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
As shown in figure 1, the processing system for video that one embodiment of the invention provides includes two video processors, wherein one
Individual video processor 10 includes back board device 11, video input processing unit 13, video frequency output processing unit 15 and pluggable
Expanding unit 16, another video processor 20 include back board device 21, video input processing unit 23, video frequency output processing
Device 25 and pluggable expanding unit 26.Wherein, back board device 11 is used to connect video input processing unit 13, at video frequency output
Manage device 15 and pluggable expanding unit 16；Back board device 21 is used to connect video input processing unit 23, video frequency output processing
Device 25 and pluggable expanding unit 26.The pluggable expanding unit 16 and video processor that video processor 10 passes through its own
20 pluggable expanding unit 26 interconnects via cable (such as CXP cables etc.), to realize signal interaction, so as to improve pin
Access and disposal ability to multi input/signal source output operating mode.
It should be noted that the tandem type video process apparatus in the present embodiment only gives two video processor cascades
Situation, it is possible to understand that ground, the video processor with two or more similar structures cascade formed video process apparatus
Should be within protection scope of the present invention.
Because video processor 10 is similar with the structure of video processor 20, therefore for the ease of describing, hereinafter only
The structure of video processor 10 is described in detail.
Specifically, as shown in Fig. 2 pluggable expanding unit 16 includes connector 161 and subtending port 162.Subtending port
162 interconnections being used between multiple video processors, it is, for example, CXP high-speed interfaces, and CXP is CoaXPress abbreviation,
It is a kind of point-to-point serial communication Digital Interface Standard of asymmetrical high speed.Connector 161 connect the back board device 11 with
Data path and control access are formed, it is, for example, FCI high speed connectors, and the data path is for example with serializer/unstring
Device bus realizes data transfer, while in order to ensure completion of the data in high-speed transfer, in being set preferably in data path
Forwarding enhancing is carried out to signal after forwarding chip 163.As for control access, then it is, for example, and is made up of more signal lines.
Referring to Fig. 3, video processor 10 includes back board device 11, video input processing unit 13, video frequency output processing dress
Put 15, pluggable expanding unit 16 and master control set 17.
Wherein, the concrete structure of back board device 11 is as shown in figure 4, it is specifically included：Video input processing unit interface group
111st, video frequency output processing unit interface group 113, master control set interface 115, expanding unit interface 116, matrix switch module
117th, networked physics layer transceiver group 118a, networked physics layer transceiver group 118b, networked physics layer transceiver group 118c, can compile
Journey logical device 119 and genlock device 110.
Wherein, video input processing unit interface group 111 for example including multiple video input processing unit interfaces 1111 and
Neck form can be used.
Video frequency output processing unit interface group 113 including multiple video frequency output processing unit interfaces 1131 and can for example adopt
With neck form.
Master control set interface 115 and expanding unit interface 116 can use neck form.
The connection matrix Switching Module 117 of expanding unit interface 116 and PLD 119.Specifically, extension dress
Interface 116 is put for example via multichannel SERDES bus connection matrix Switching Module 117 and for example by networked physics layer transceiver
Group 118c connections PLD 119.Furthermore expanding unit interface 116 be used for connect pluggable expanding unit 16 with
Other video processors such as 20 form cascade, so as to which two video processors being connected can share signal source.
Matrix switch module 117 connects video input processing unit interface group 111, video frequency output processing unit interface group
113 and master control set interface 115, its such as including high speed matrix switch chip as CrossPoint Switch chips.
Interconnected between genlock device such as 110,210 in multiple video processors, pass through genlock device 110,210
The synchronizing signal of offer allows the output signal of multiple video processors to be operated in synchronous mode, avoids two and its output
The situation that picture caused by signal is asynchronous is torn.
PLD 119 connects master control set interface 115, by networked physics layer transceiver (or network
PHY) organize 118a connection video input processing units interface group 111 and pass through networked physics layer transceiver group 118b connection videos
Output processing apparatus interface group 113.In addition, PLD 118 also includes control sequential output interface group 1191 and control
Sequential export interface group 1193 processed, control sequential output interface group 1191 connect video input processing unit interface group 111, control
Sequential export interface group 1193 connects video frequency output processing unit interface group 113.
More specifically, eight video input processing unit interfaces 1111 are included with video input processing unit interface group 111
And exemplified by video frequency output processing unit interface group 113 includes eight video frequency output processing unit interfaces 1131, then networked physics layer
Transceiver group 118a may include eight road network physical layer transceivers to connect eight video input processing unit interfaces 1111 respectively,
Networked physics layer transceiver group 118b may include eight road network physical layer transceivers to connect eight video frequency output processing dresses respectively
Put interface 1131；Similarly, control sequential output interface group 1191 may include eight tunnel control sequential output interfaces to connect respectively
Eight video input processing unit interfaces 1111, control sequential output interface group 1193 may include eight tunnel control sequential output interfaces
To connect eight video frequency output processing unit interfaces 1131 respectively.Certainly, it is worth mentioning at this point that, the interface quantity illustrate herein in
Not it is used for limiting the present invention, it can be according to being actually needed elastic design.Furthermore the PLD of the present embodiment
119 be, for example, FPGA (Field Programmable Gate Array, field programmable gate array) device, certainly the present invention
It is not limited thereto.In addition, what deserves to be explained is, the PLD 119 of the present embodiment is mainly used in realizing data, life
The forwarding of order, and by increasing the data physical channels such as networked physics layer transceiver group 118a, 118b, it can reach simplified control
The purpose of logic processed simultaneously can realize point-to-point communication, add Data Transfer Parallelism.
Hold above-mentioned, video input processing unit 13 is connected to the video input in video input processing unit interface group 111
Processing unit interface 1111 (referring to Fig. 4), video input processing unit 13 can also be referred to as defeated for example with board form
Enter card, correspondingly video input processing unit interface 1111 can be notch；As for being connected to video input processing unit
The quantity of the video input processing unit 13 of interface group 111 can be one, or multiple, particular number regards actual demand
Depending on.Furthermore video input processing unit 13 can realize video input, video pre-filtering, or even video scaling, video preprocessor
The functions such as prison, OSD (on-screen display), UMD (Under Monitor Display).Video pre-filtering therein is
The operations such as gamma (Gamma) conversion, color gamut conversion (such as yuv format is converted into rgb format), filtering (such as medium filtering).
In addition, each video input processing unit interface 1111 for example passes through multichannel SERDES bus connection matrix Switching Module 117.
Video frequency output processing unit 15 is connected to the video frequency output processing unit in video frequency output processing unit interface group 113
Interface 1131 (referring to Fig. 4), video frequency output processing unit 15 can also be referred to as output card for example with board form, accordingly
Ground video frequency output processing unit interface 1131 can be notch；As for being connected to video frequency output processing unit interface group 113
Video frequency output processing unit 15 quantity can be one, or multiple, particular number is depending on actual demand.Again
Person, video frequency output processing unit 15 can realize the functions such as image scaling, imaging importing, video frequency output.In addition, each video
Output processing apparatus interface 1131 for example passes through multichannel SERDES bus connection matrix Switching Module 117.
Master control set 17 is connected to the master control set interface 115 (referring to Fig. 4) of back board device 11, and it can be used as host computer
Communication bridge between video processor 10, mainly realizes control function.Specifically, master control set 17 can pass through FMC
(Flexible Memory Controller, variable storage control)/FSMC (Flexible Static Memory
Controller, variable static storage controller) etc. storage control bus communicated with PLD 119, and pass through
PLD 119 carries out data transmission with video input processing unit 13, video frequency output processing unit 15.
Furthermore in the embodiment shown in fig. 3, video input processing unit 13, video frequency output processing unit 15 and matrix are handed over
Connected between mold changing block 117 using serializer/deserializers (SERDES) bus, to reach the purpose of high speed data transfer.Matrix
Switching Module 117 uses high speed matrix switch chip, and it can be regarded according to the switching command that master control set 17 issues by corresponding to
The data of frequency input processing device 13 are switched in corresponding video frequency output processing unit 15.
Referring to Fig. 5, PLD 119 is for example including command analysis module, ID configuration modules, data storage mould
The functional modules such as block, MVR/PGM sequence generation modules.
After the system electrification of video processor 10, master control set 17 sends ID configuration orders to PLD first
119, ID configuration orders are parsed by the command analysis module of PLD 119, control ID configuration modules produce n
Individual ID such as ID1 ... IDn, n value is generally by video input processing unit interface 1111 and video frequency output processing unit herein
The total quantity of interface 1131 determines.N ID caused by ID configuration modules passes via networking physical layer transceiver group 118a, 118b
Each video input processing unit 13 and video frequency output processing unit 15 are delivered to, by video input processing unit 13 and video frequency output
Processing unit 15 reads the ID received and preserved into RAM.Then, at each video input processing unit 13 and video frequency output
Reason device 15 produces responsion signal Ack 1 respectively ..., ACKn is to represent to have been received by ID and by networked physics layer transceiver
The data memory module that group 118a, 118b send PLD 119 to preserve as the processing of each video input
The ID status informations of device 13 and video frequency output processing unit 15, and PLD 119 can produce interrupt signal to master
Device 17 is controlled, the ID status informations preserved in data memory module are read by master control set 17.
As for MVR/PGM sequence generation modules, it can produce MVR (Multi-Viewer) sequential and PGM
(Programming) sequential.Wherein, MVR sequential is for example including multichannel multisignal source premonitoring timing control signal, and per all the way
Multisignal source premonitoring is with timing control signal for example comprising clock signal (MCLK), data enable signal (DE), line synchronising signal
(HS) and field sync signal (VS) and via the output interface of control sequential all the way in control sequential output interface group 1191 and
The transceiver of networked physics layer all the way in networked physics layer transceiver group 118a is sent to corresponding video input processing unit
13, to be used as multisignal source premonitoring picture processing control sequential.Similarly, PGM sequential is for example including the currently playing letter of multichannel
Number source (or PGM signal sources, it typically is the currently playing signal source shown for upper screen) output timing control signal, and
Per signal source output currently playing all the way with timing control signal for example comprising clock signal (PCLK), data enable signal
(DE), line synchronising signal (HS) and field sync signal (VS) and during via control all the way in control sequential output interface group 1193
The transceiver of networked physics layer all the way in sequence output interface and networked physics layer transceiver group 118b is sent to corresponding regard
Frequency output processing apparatus 15, to be used as currently playing signal source output control sequential.
Referring to Fig. 6, in another embodiment of the present invention, back board device 31 includes：Video input processing unit interface
Group 311, video frequency output processing unit interface group 313, microcontroller circuit 314, master control set interface 315, expanding unit interface
316th, matrix switch module 317, networked physics layer transceiver group 318a, networked physics layer transceiver group 318b, networked physics layer
Transceiver group 318c and PLD 319 and genlock device 310.
Wherein, video input processing unit interface group 311 for example including multiple video input processing unit interfaces 1111 and
Neck form can be used, it is used to connect one or more video input processing units.
The connection matrix Switching Module 317 of expanding unit interface 316 and PLD 319.Specifically, extension dress
Interface 316 is put for example via multichannel SERDES bus connection matrix Switching Module 317 and for example by networked physics layer transceiver
Group 318c connections PLD 319.Furthermore expanding unit interface 316 is used to connect described in such as previous embodiment
Pluggable expanding unit is cascaded with being formed with other video processors, so as to which two video processors being connected can share letter
Number source.
Video frequency output processing unit interface group 313 including multiple video frequency output processing unit interfaces 3131 and can for example adopt
With neck form, it is used to connect one or more video frequency output processing units.
Microcontroller circuit 314 connects master control set interface 315, such as connects master control set interface by serial ports (UART)
315.Specifically, microcontroller circuit 314 can include microcontroller as MCU and the memory of connection microcontroller, and this
The memory at place for example connects microcontroller via universal serial bus.Furthermore microcontroller circuit 314 is connected by its microcontroller
Video input processing unit interface group 311 and video frequency output processing unit interface group 313 are connect with gathering video input processing unit
At the video frequency output that the video input processing units and video frequency output processing unit interface group 313 that mouth group 311 is connected are connected
Manage the physical parameters such as the voltage signal of device；Memory such as flash memory by universal serial bus as spi bus and micro-controller communications,
Preserve the data record on microcontroller.
Master control set interface 315 can use neck form, and it is used to connect master control set.And the master control set connected
Control function can be mainly realized as the communication bridge between host computer and video processor.
Matrix switch module 317 connects video input processing unit interface group 311, video frequency output processing unit interface group
313 and master control set interface 315, its such as including high speed matrix switch chip as CrossPoint Switch chips.This
Locate, each video input processing unit interface 3111 in video input processing unit interface group 311 for example passes through multichannel
SERDES bus connection matrix Switching Module 317；Similarly, each video in video frequency output processing unit interface group 313
Output processing apparatus interface 3131 for example passes through multichannel SERDES bus connection matrix Switching Module 317.
PLD 319 is for example by universal serial bus as spi bus connects master control set interface 315, passes through net
Network physical layer transceiver group 318a connection video input processing units interface group 311 and pass through networked physics layer transceiver group
318b connection video frequency output processing units interface group 313.Connect in addition, PLD 318 also includes control sequential output
Mouth group 3191 and control sequential output interface group 3193, control sequential output interface group 3191 connect video input processing unit and connect
Mouth group 311, control sequential output interface group 3193 connects video frequency output processing unit interface group 313.
More specifically, eight video input processing unit interfaces 3111 are included with video input processing unit interface group 311
And exemplified by video frequency output processing unit interface group 313 includes eight video frequency output processing unit interfaces 3131, then networked physics layer
Transceiver group 318a may include eight road network physical layer transceivers to connect eight video input processing unit interfaces 3111 respectively,
Networked physics layer transceiver group 318b may include eight road network physical layer transceivers to connect eight video frequency output processing dresses respectively
Put interface 3131；Similarly, control sequential output interface group 3191 may include eight tunnel control sequential output interfaces to connect respectively
Eight video input processing unit interfaces 3111, control sequential output interface group 3193 may include eight tunnel control sequential output interfaces
To connect eight video frequency output processing unit interfaces 3131 respectively.Certainly, it is worth mentioning at this point that, the interface quantity illustrate herein in
Not it is used for limiting the present invention, it can be according to being actually needed elastic design.Furthermore the PLD of the present embodiment
319 be, for example, FPGA device, and certain present invention is not limited thereto.In addition, what deserves to be explained is, the programmable of the present embodiment is patrolled
Volume device 319 is mainly used in realizing data, the forwarding of order, and by increase by networked physics layer transceiver group 318a,
The data physical channels such as 318b, it can reach the purpose of simplify control logic and realize point-to-point communication, add data biography
Defeated concurrency.
Finally, it is worth mentioning at this point that, in other embodiments of the present invention, foregoing PLD can not also configure
Control sequential output interface group, it can equally reach the purpose that more video processors share for example shared input source of information.
In several embodiments provided herein, it should be understood that disclosed system, device and/or method, can
To realize by another way.For example, device embodiment described above is only schematical, for example, unit is drawn
Point, only a kind of division of logic function, there can be other dividing mode when actually realizing, such as multichannel unit or component can
To combine or be desirably integrated into another system, or some features can be ignored, or not perform.It is another, it is shown or beg for
The mutual coupling of opinion or direct-coupling or communication connection can be the INDIRECT COUPLINGs by some interfaces, device or unit
Or communication connection, can be electrical, mechanical or other forms.
The unit illustrated as separating component can be or may not be physically separate, be shown as unit
Part can be or may not be physical location, you can with positioned at a place, or can also be distributed to multi-channel network
On unit.Some or all of unit therein can be selected to realize the purpose of this embodiment scheme according to the actual needs.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
The present invention is described in detail previous embodiment, it will be understood by those within the art that：It still can be to foregoing
Technical scheme described in each embodiment is modified, or carries out equivalent substitution to which part technical characteristic；And these are repaiied
Change or replace, the essence of appropriate technical solution is departed from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (13)
- A kind of 1. processing system for video, it is characterised in that including：First video processor, including：First pluggable expanding unit, is provided with the first connector and the first subtending port；First back board device, be provided with the first video input processing unit interface group, the first video frequency output processing unit interface group, First expanding unit interface, the first master control set interface and the first matrix switch module, wherein the first matrix switch module Connect the first video input processing unit interface group, the first video frequency output processing unit interface group, first expansion Extending apparatus interface and the first master control set interface, the first video input processing unit interface group are defeated for connecting video Enter processing unit, the first video frequency output processing unit interface group is used to connect video frequency output processing unit, first master Control device interface is used to connect master control set, and the first expanding unit interface connects first connector；Second video processor, including：Second pluggable expanding unit, is provided with the second connector and the second subtending port；Second back board device, be provided with the second video input processing unit interface group, the second video frequency output processing unit interface group, Second expanding unit interface, the second master control set interface and the second matrix switch module, wherein the second matrix switch module Connect the second video input processing unit interface group, the second video frequency output processing unit interface group, second expansion Extending apparatus interface and the second master control set interface, the second video input processing unit interface group are defeated for connecting video Enter processing unit, the second video frequency output processing unit interface group is used to connect video frequency output processing unit, second master Control device interface is used to connect master control set, and the second expanding unit interface connects second connector；Wherein, second subtending port connects first subtending port by cable.
- 2. processing system for video as claimed in claim 1, it is characterised in that first connector and first order connection Formed with data path and control access between mouthful, relay repeater, and the relay forwarding are provided with the data path Device connects first connector and first subtending port.
- 3. processing system for video as claimed in claim 2, it is characterised in that the relay repeater passes through serializer/unstring Device bus connects first connector and first subtending port.
- 4. processing system for video as claimed in claim 1, it is characterised in that first back board device also includes：First network physical layer transceiver group；Second networked physics layer transceiver group；3rd networked physics layer transceiver group；First PLD, connect the first master control set interface, pass through the first network physical layer transceiver Group connects the first video input processing unit interface group, connects described the by the second networked physics layer transceiver group One video frequency output processing unit interface group and pass through the 3rd networked physics layer transceiver group connect it is described first extension dress Put interface.
- 5. processing system for video as claimed in claim 4, it is characterised in that first PLD also includes the One control sequential output interface group and the second control sequential output interface group, the first control sequential output interface group connect institute The first video input processing unit interface group is stated, the second control sequential output interface group is connected at first video frequency output Manage device interface group.
- 6. processing system for video as claimed in claim 1, it is characterised in that the first matrix switch module passes through multichannel string Change device/deserializer bus and connect the first expanding unit interface.
- 7. processing system for video as claimed in claim 1, it is characterised in that first back board device also includes：Microcontroller circuit, including microcontroller and the memory for connecting the microcontroller；Wherein, the microcontroller connects the first master control set interface, the first video input processing unit interface group With the first video frequency output processing unit interface group.
- 8. processing system for video as claimed in claim 4, it is characterised in that first PLD passes through storage Controller bus connects the master control set interface, and the first control sequential output interface group and second control sequential are defeated It is used to export per control sequential output interface all the way comprising clock signal, data enable signal, the synchronous letter of row in outgoing interface group Number and field sync signal timing control signal；It is pre- that the first control sequential output interface group is used for output multi-channel multisignal source Prison timing control signal, the second control sequential output interface group are used for output multi-channel currently playing signal source sequential control Signal processed.
- 9. processing system for video as claimed in claim 1, it is characterised in that it is same that first back board device is additionally provided with first Walk phase locking unit and the first genlock device connects the first expanding unit interface；Second backboard is additionally provided with second Genlock device and the second genlock device connection the second expanding unit interface.
- A kind of 10. video processor, it is characterised in that including：Pluggable expanding unit, is provided with connector and subtending port；Back board device, it is provided with video input processing unit interface group, video frequency output processing unit interface group, expanding unit and connects Mouth, master control set interface and matrix switch module, connect wherein the matrix switch module connects the video input processing unit Mouth group, the video frequency output processing unit interface group, the expanding unit interface and the master control set interface, the video are defeated Enter processing unit interface group to be used to connect video input processing unit, the video frequency output processing unit interface group regards for connection Frequency output processing apparatus, the master control set interface are used to connect master control set, patched described in the expanding unit interface connection Part；Wherein, between the connector and the subtending port formed with data path and control access, in the data path Relay repeater is provided with, and the relay repeater connects the connector and the subtending port.
- 11. video processor as claimed in claim 10, it is characterised in that the back board device also includes：First network physical layer transceiver group；Second networked physics layer transceiver group；3rd networked physics layer transceiver group；PLD, connect the master control set interface, institute is connected by the first network physical layer transceiver group State video input processing unit interface group, the video frequency output processing dress is connected by the second networked physics layer transceiver group Put interface group and the expanding unit interface is connected by the 3rd networked physics layer transceiver group.
- 12. video processor as claimed in claim 11, it is characterised in that the PLD also includes the first control Sequential export interface group processed and the second control sequential output interface group, regard described in the first control sequential output interface group connection Frequency input processing device interface group, the second control sequential output interface group connect the video frequency output processing unit interface Group；It is defeated per control sequential all the way in the first control sequential output interface group and the second control sequential output interface group Outgoing interface is used to export the timing control signal for including clock signal, data enable signal, line synchronising signal and field sync signal； The first control sequential output interface group is used for output multi-channel multisignal source premonitoring timing control signal, second control Sequential export interface group is used for the currently playing signal source timing control signal of output multi-channel.
- 13. the video processor as described in claim 10-12 any one, it is characterised in that the back board device is also set up There is genlock device and the genlock device connects the expanding unit interface.
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Inventor after: Wang Huorong Inventor after: Zong Jingguo Inventor before: Wang Huorong Inventor before: Zong Jingguo Inventor before: Qian Cheng |