CN107613302B - Decoding method and device, storage medium and processor - Google Patents
Decoding method and device, storage medium and processor Download PDFInfo
- Publication number
- CN107613302B CN107613302B CN201710826776.2A CN201710826776A CN107613302B CN 107613302 B CN107613302 B CN 107613302B CN 201710826776 A CN201710826776 A CN 201710826776A CN 107613302 B CN107613302 B CN 107613302B
- Authority
- CN
- China
- Prior art keywords
- state
- decoding
- hardware
- hardware decoding
- configuration parameters
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Compression Or Coding Systems Of Tv Signals (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
The invention discloses a decoding method and device, a storage medium and a processor. Wherein, the method comprises the following steps: detecting the state of a state machine set in the decoding process in the process of decoding a current frame in video data to be decoded, wherein the state is used for indicating actions executed in the decoding process; executing the action corresponding to the state and switching the state of the state machine to execute the following operations: storing hardware decoding configuration parameters in a ping-pong cache mode; analyzing the slice header of the next frame to obtain the hardware decoding configuration parameters of the next frame, and storing the hardware decoding configuration parameters of the next frame into a ping-pong cache; and triggering the hardware decoding of the video data to be decoded by using the hardware decoding configuration parameters in the ping-pong cache in the interrupt processing function for hardware decoding.
Description
Technical Field
The present invention relates to the field of video decoding, and in particular, to a decoding method and apparatus, a storage medium, and a processor.
Background
In recent years, the trend of video applications towards the following several directions is becoming more and more obvious: high definition (HigherDefinition): the application formats of the digital videos are comprehensively upgraded from 720P to 1080P, and even the digital video formats of 4K × 2K and 8K × 4K appear in some video application fields; high frame rate (Higher frame rate): the digital video frame rate is upgraded from 30fps to application scenes of 60fps, 120fps and even 240 fps; high compression ratio (high compression rate): transmission bandwidth and storage space have always been the most critical resources in video applications, and therefore, obtaining an optimal video experience in limited space and pipelines has always been a constant pursuit by users.
Based on the above application development trend and the limitation of h.264, the High Efficiency Video Coding (HEVC) protocol standard oriented to higher definition, higher frame rate and higher compression rate is produced. The core objective of H.265 is that on the basis of H.264/AVC high profile, the code rate of a video stream is reduced by 50% on the premise of ensuring the same video quality; the method allows the encoding end to increase complexity (three times of computational complexity) properly while improving the compression efficiency. The current standard h.265 decoding adopts the flow shown in fig. 1, analyzes a frame slice header, applies for an idle frame buffer to start decoding, and finally starts analyzing a new frame slice header after the decoding is finished. This approach has the following problems: (1) due to the high complexity of H.265 coding, the adoption of the serial decoding flow can cause the slow decoding speed and the phenomenon of playing pause; (2) this serial decoding flow results in hardware processing idle states for long periods of time, which is not useful for fully exploiting hardware performance.
Disclosure of Invention
The embodiment of the invention provides a decoding method and device, a storage medium and a processor, which are used for optimizing decoding processes in related technologies.
According to an aspect of an embodiment of the present application, there is provided a decoding method including: detecting the state of a state machine set in the decoding process in the process of decoding a current frame in video data to be decoded, wherein the state is used for indicating actions executed in the decoding process; executing the action corresponding to the state and switching the state of the state machine to execute the following operations: storing hardware decoding configuration parameters in a ping-pong cache mode; analyzing the slice header of the next frame to obtain the hardware decoding configuration parameters of the next frame, and storing the hardware decoding configuration parameters of the next frame into a ping-pong cache; and triggering the hardware decoding of the video data to be decoded by using the hardware decoding configuration parameters in the ping-pong cache in the interrupt processing function for hardware decoding.
Optionally, the executing operation by executing the action corresponding to the state and switching the state of the state machine includes: when the state machine is detected to be in a first state, analyzing the slice header of the next frame, and switching to a second state; in the second state, judging whether an idle frame buffer exists, if so, switching the state machine to a third state, otherwise, judging whether the hardware is in an idle state; starting hardware decoding when the hardware is in an idle state; when the state machine is switched to a third state, judging whether an idle command queue memory exists, and if not, judging whether the hardware is in an idle state; hardware decoding is started while the hardware is in an idle state.
Optionally, when the state machine is in the third state and there is a free command queue memory, the method further includes: and storing the hardware decoding configuration parameters of the next frame into an idle command queue memory.
Optionally, the method further comprises: releasing a command queue memory in an interrupt processing function for hardware decoding; and judging whether a command queue in a readable state exists or not, and if so, starting hardware decoding.
According to another aspect of the embodiments of the present application, there is provided another decoding method, including: in the process of decoding the current frame, detecting the states of a first buffer area and a second buffer area, wherein the states comprise: a read-only state and a writable state; reading hardware decoding configuration parameters for hardware decoding of the current frame from the first buffer area when the first buffer area is in a read-only state and the second buffer area is in a writable state; acquiring the hardware decoding configuration parameter of the next frame, and storing the hardware decoding configuration parameter of the next frame into a second buffer area; and when the hardware equipment for decoding is in an idle state, performing hardware decoding on the current frame by using the hardware decoding configuration parameters read from a specified buffer area, wherein the specified buffer area is the buffer area which is currently in a read-only state in the first buffer area and the second buffer area.
Optionally, before detecting the states of the first buffer and the second buffer, the method further includes: and analyzing the slice header of the current frame to obtain the hardware decoding configuration parameters of the current frame.
Optionally, before the hardware decoding the current frame using the hardware decoding configuration parameters read from the designated buffer, the method further includes: triggering to detect whether the hardware equipment is in an idle state by at least one of the following modes: detecting that the frame buffer area is failed to apply, wherein the frame buffer area is used for storing image data obtained after decoding a current frame; detecting that a command queue memory application for storing hardware decoding configuration parameters fails; and detecting the following: in the interrupt processing function for hardware decoding, a command queue memory for storing hardware decoding configuration parameters is released, and the command queue memory is changed from a writable state to a read-only state.
Optionally, storing the hardware decoding configuration parameters of the next frame into the second buffer includes: when detecting that the frame buffer area is successfully applied, triggering an application command queue memory; and when the command queue memory application is detected to be successful, storing the hardware decoding configuration parameters of the next frame into the command queue memory.
Optionally, the method further comprises: when the first buffer area is changed from a read-only state to a writable state, the second buffer area is changed from a writable state to a read-only state, and when the hardware device for decoding is in an idle state, hardware decoding is performed on a next frame using the hardware decoding configuration parameters of the next frame read from the second buffer area.
According to still another aspect of embodiments of the present application, there is provided a decoding apparatus including: the device comprises a detection module, a decoding module and a processing module, wherein the detection module is used for detecting the state of a state machine set in the decoding process in the process of decoding a current frame in video data to be decoded, and the state is used for indicating actions executed in the decoding process; the execution module is used for executing the following operations by executing the action corresponding to the state and switching the state of the state machine: storing hardware decoding configuration parameters in a ping-pong cache mode; analyzing the slice header of the next frame to obtain the hardware decoding configuration parameters of the next frame, and storing the hardware decoding configuration parameters of the next frame into a ping-pong cache; and triggering the hardware decoding of the video data to be decoded by using the hardware decoding configuration parameters in the ping-pong cache in the interrupt processing function for hardware decoding.
According to still another aspect of embodiments of the present application, there is provided a storage medium including a stored program, wherein a device on which the storage medium is located is controlled to perform the above decoding method when the program is executed.
According to a further aspect of the embodiments of the present application, there is provided a processor for executing a program, wherein the program executes to perform the above decoding method.
In the embodiment of the invention, the state of the state machine set in the decoding process is detected in the process of decoding the current frame in the video data to be decoded, and the action corresponding to the state and the state of the state machine are executed, so that the configuration parameters used for hardware decoding of the next frame can be configured in advance while hardware decoding is realized, the waste of hardware idle resources is reduced, the hardware performance can be fully exerted, the decoding speed is accelerated, the smoothness of video playing is improved, the playing of a video file with high code rate is supported, and the technical problem of optimizing the decoding process in the related technology is solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
fig. 1 is a flowchart illustrating a decoding method according to the related art;
FIG. 2 is a flow chart of a decoding method according to an embodiment of the present invention;
FIG. 3a is a flow chart illustrating a decoding process according to an embodiment of the present invention;
FIG. 3b is a flow diagram illustrating another decoding process according to an embodiment of the present invention;
fig. 4 is a block diagram of a decoding apparatus according to an embodiment of the present invention;
FIG. 5 is a flow chart illustrating another decoding method according to an embodiment of the present invention;
fig. 6 is a block diagram of another decoding apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
For a better understanding of the embodiments of the present application, technical terms referred to in the embodiments of the present application are explained below:
hardware decoding: the scheme is that a graphic chip manufacturer provides a scheme for decoding video stream by using GPU resources, namely, a soft solution is adopted, namely, the traditional scheme for using a CPU to undertake decoding work;
frame buffer (video memory): the image buffer is a two-dimensional array formed by pixels, each storage unit corresponds to one pixel on a screen, and the whole frame buffer corresponds to one frame of image, namely a current screen picture.
In accordance with an embodiment of the present invention, there is provided a method embodiment of a decoding method, it should be noted that the steps illustrated in the flowchart of the figure may be performed in a computer system such as a set of computer executable instructions, and that while a logical order is illustrated in the flowchart, in some cases the steps illustrated or described may be performed in an order different than here.
Fig. 2 is a flowchart illustrating a decoding method according to an embodiment of the present invention. As shown in fig. 2, the method includes:
step S202, in the process of decoding the current frame in the video data to be decoded, detecting the state of the state machine set in the decoding process, where the state is used to indicate the action executed in the decoding process.
In an alternative embodiment, the state of the state machine may include, but is not limited to, PARSE _ NEW _ SLICE for parsing a NEW SLICE header, REQ _ FB for requesting a frame buffer, REQ _ CQ for requesting a command queue, and HW _ DECODING for performing hardware DECODING.
Step S204, by executing the action corresponding to the state and switching the state of the state machine, executing the following operations: storing hardware decoding configuration parameters in a ping-pong cache mode; analyzing the slice header of the next frame to obtain the hardware decoding configuration parameter of the next frame, and storing the hardware decoding configuration parameter of the next frame into a ping-pong cache; and triggering the hardware decoding configuration parameters in the ping-pong cache to perform hardware decoding on the video data to be decoded in an interrupt processing function for hardware decoding.
Alternatively, the operations may be performed by performing the actions corresponding to the states and switching the states of the state machine, and may be implemented by, but not limited to: when the state machine is detected to be in a first state, analyzing the slice header of the next frame, and switching to a second state;
under the second state, judging whether an idle frame buffer exists, if so, switching the state machine to a third state, otherwise, judging whether the hardware is in an idle state; starting hardware decoding when the hardware is in an idle state;
when the state machine is switched to a third state, judging whether an idle command queue memory exists, and if not, judging whether hardware is in an idle state; and starting hardware decoding when the hardware is in an idle state.
Optionally, when the state machine is in the third state and there is an idle command queue memory, the hardware decoding configuration parameter of the next frame is stored in the idle command queue memory. As an optional embodiment of the present application, the command queue memory is released in an interrupt processing function for hardware decoding; and judging whether a command queue in a readable state exists or not, and if so, starting hardware decoding.
To facilitate understanding of the above embodiments, the following detailed description is made with reference to fig. 3a and 3 b. The following embodiments adopt a state machine method, and use two command queues as ping-pong buffers, store data configuring a hardware register, parse a frame of slice header in advance, then start hardware decoding in an interrupt processing function when the hardware decoding ends, reduce hardware idle time, thereby achieving the purpose of accelerating decoding speed. Specifically, the method comprises the following steps:
as shown in FIG. 3a, four states including PARSE _ NEW _ SLICE, REQ _ FB, REQ _ CQ, and HW _ DECODING are set by using a state machine; the state machine is then switched by the interrupt handling function at the end of the decode task and frame decode.
And in the decoding task, completing the corresponding flow according to the state machine. If the current state machine is PARSE _ NEW _ SLICE, a frame SLICE header is analyzed, then the state machine is switched to REQ _ FB, whether a vacant frame buffer area is used for decoding is judged, if the frame buffer area is successfully applied, the state machine is switched to REQ _ CQ, and whether a vacant command queue memory exists is judged; if the application frame buffer fails, whether the hardware is in an idle state and whether a prepared command queue exists is inquired, and if both conditions are met, hardware decoding is started.
If the current state machine is REQ _ CQ, starting to judge that no idle command queue memory exists, and if the command queue memory is successfully applied, storing parameters needing to be configured with hardware decoding into a command queue; if the memory of the application command queue fails, whether the hardware is in an idle state and whether a prepared command queue exists is inquired, and if the two conditions are met, hardware decoding is started.
As shown in fig. 3b, in the hardware frame decoding ending interrupt processing function, the memory of the command queue storing the parameters of the currently decoded frame is released, and then whether the command queue is ready is inquired, if yes, the hardware decoding is started.
Fig. 4 is a block diagram of a decoding apparatus according to an embodiment of the present invention. As shown in fig. 4, the apparatus includes:
a detecting module 40, configured to detect, in a process of decoding a current frame in video data to be decoded, a state of a state machine set in the decoding process, where the state is used to indicate an action performed in the decoding process;
an executing module 42, coupled to the detecting module 40, configured to execute the following operations by executing the action corresponding to the state and switching the state of the state machine: storing hardware decoding configuration parameters in a ping-pong cache mode; analyzing the slice header of the next frame to obtain the hardware decoding configuration parameters of the next frame, and storing the hardware decoding configuration parameters of the next frame into a ping-pong cache; and triggering the hardware decoding configuration parameters in the ping-pong cache to perform hardware decoding on the video data to be decoded in an interrupt processing function for hardware decoding.
It should be noted that, the above modules may be implemented by software or hardware, and for the latter, the following implementation may be presented, but is not limited to this: the modules are positioned in the same processor; alternatively, the modules may be located in different processors in any combination.
It should be noted that, reference may be made to the description related to the method embodiment shown in fig. 2 for a preferred embodiment of the apparatus shown in fig. 4, and details are not described here again.
Fig. 5 is a flowchart illustrating another decoding method according to an embodiment of the present invention, as shown in fig. 5, the method includes the following steps:
step S502, detecting the states of the first buffer and the second buffer during decoding the current frame, wherein the states include: a read-only state and a writable state; optionally, before detecting the states of the first buffer area and the second buffer area, the slice header of the current frame may be analyzed to obtain the first configuration parameter; in an alternative embodiment, the first configuration parameter may also be obtained from another device, where the other device is a device having a function of parsing the frame image.
Step S504, when the first buffer area is in a read-only state and the second buffer area is in a writable state, reading a hardware decoding configuration parameter for hardware decoding of a current frame from the first buffer area; acquiring the hardware decoding configuration parameter of the next frame, and storing the hardware decoding configuration parameter of the next frame into a second buffer area;
the hardware decoding configuration parameters include, but are not limited to: compression ratio, video format, etc.
Step S506, when the hardware device for decoding is in an idle state, performing hardware decoding on the current frame by using the hardware decoding configuration parameter read from the designated buffer area, where the designated buffer area is a buffer area currently in a read-only state in the first buffer area and the second buffer area.
Triggering and detecting whether the hardware equipment is in an idle state or not by at least one of the following modes: detecting a frame buffer area application failure, wherein the frame buffer area is used for storing image data obtained after decoding the current frame; detecting that a command queue memory application for storing hardware decoding configuration parameters fails; and detecting the following: in the interrupt processing function for hardware decoding, a command queue memory for storing hardware decoding configuration parameters is released, and the command queue memory is changed from a writable state to a read-only state.
In an alternative embodiment, the hardware decoding configuration parameter storage value of the next frame may be stored in the command queue memory in the following manner, and specifically, may be implemented in the following manner, but is not limited to this: triggering and applying the command queue memory when detecting that the frame buffer area is successfully applied; and when the command queue memory application is detected to be successful, storing the hardware decoding configuration parameters of the next frame into the command queue memory.
Optionally, when the first buffer is changed from a read-only state to a writable state, the second buffer is changed from a writable state to the read-only state, and when the hardware device for decoding is in an idle state, the hardware decoding configuration parameters of the next frame read from the second buffer are used to perform hardware decoding on the next frame.
It should be noted that the states of the first buffer and the second buffer may be changed, and the actions involved in the different states are also different, for example: and when the first buffer area is changed from a read-only state to a writable state, the second buffer area is changed from a writable state to the read-only state, and when the hardware device for decoding is in an idle state, performing hardware decoding on a next frame of the current frame using the second configuration parameter read from the second buffer area. It can be seen from the above that, since the configuration parameters of the next frame can be obtained in advance when the current frame is decoded, the idle time of the hardware is reduced, which is helpful for improving the decoding efficiency.
An embodiment of the present invention further provides a decoding apparatus, where the decoding apparatus is configured to implement the decoding method shown in fig. 5, and fig. 6 is a block diagram of another decoding apparatus according to an embodiment of the present invention. As shown in fig. 6, the apparatus includes:
a detecting module 60, configured to detect states of the first buffer and the second buffer during decoding a current frame, where the states include: a read-only state and a writable state;
a processing module 62, configured to read a hardware decoding configuration parameter for hardware decoding a current frame from the first buffer area when the first buffer area is in a read-only state and the second buffer area is in a writable state; acquiring the hardware decoding configuration parameter of the next frame, and storing the hardware decoding configuration parameter of the next frame into a second buffer area;
and a decoding module 66, configured to perform hardware decoding on the current frame by using the hardware decoding configuration parameters read from a specified buffer when the hardware device for decoding is in an idle state, where the specified buffer is a buffer currently in a read-only state in the first buffer and the second buffer.
It should be noted that, the above modules may be implemented by software or hardware, and for the latter, the following implementation may be presented, but is not limited to this: the modules are positioned in the same processor; alternatively, the modules may be located in different processors in any combination.
It should be noted that, reference may be made to the description related to the method embodiments shown in fig. 2 and 5 for a preferred embodiment of the apparatus shown in fig. 6, and details are not repeated here.
The present embodiment also provides a storage medium, where the storage medium includes a stored program, and when the program runs, the device where the storage medium is located is controlled to execute the decoding method shown in fig. 2 or fig. 6.
Taking the method shown in fig. 2 as an example, the storage medium is at least used for storing a program for executing the following functions: detecting the state of a state machine set in the decoding process in the process of decoding a current frame in video data to be decoded, wherein the state is used for indicating actions executed in the decoding process; executing the action corresponding to the state and switching the state of the state machine to execute the following operations: storing hardware decoding configuration parameters in a ping-pong cache mode; analyzing the slice header of the next frame to obtain the hardware decoding configuration parameters of the next frame, and storing the hardware decoding configuration parameters of the next frame into a ping-pong cache; and triggering the hardware decoding of the video data to be decoded by using the hardware decoding configuration parameters in the ping-pong cache in the interrupt processing function for hardware decoding.
Optionally, the storage medium is further configured to execute a program for: when the state machine is detected to be in a first state, analyzing the slice header of the next frame, and switching to a second state; in the second state, judging whether an idle frame buffer exists, if so, switching the state machine to a third state, otherwise, judging whether the hardware is in an idle state; starting hardware decoding when the hardware is in an idle state; when the state machine is switched to a third state, judging whether an idle command queue memory exists, and if not, judging whether the hardware is in an idle state; hardware decoding is started while the hardware is in an idle state.
Optionally, the storage medium is further configured to store a program that performs the following functions: and when the state machine is in the third state and an idle command queue memory exists, storing the hardware decoding configuration parameters of the next frame into the idle command queue memory.
The present embodiment further provides a processor, where the processor is configured to execute a program, where the program executes the decoding method shown in fig. 2 or fig. 4 when the program is executed
Taking the method shown in fig. 2 as an example, the processor executes the following program when running: detecting the state of a state machine set in the decoding process in the process of decoding a current frame in video data to be decoded, wherein the state is used for indicating actions executed in the decoding process; executing the action corresponding to the state and switching the state of the state machine to execute the following operations: storing hardware decoding configuration parameters in a ping-pong cache mode; analyzing the slice header of the next frame to obtain the hardware decoding configuration parameters of the next frame, and storing the hardware decoding configuration parameters of the next frame into a ping-pong cache; and triggering the hardware decoding of the video data to be decoded by using the hardware decoding configuration parameters in the ping-pong cache in the interrupt processing function for hardware decoding.
Optionally, the processor is further configured to execute a program for: when the first buffer area is changed from a read-only state to a writable state, the second buffer area is changed from a writable state to a read-only state, and when the hardware device for decoding is in an idle state, hardware decoding is performed on a next frame of the current frame using the second configuration parameters read from the second buffer area.
Optionally, the processor is further configured to execute a program for: when the state machine is detected to be in a first state, analyzing the slice header of the next frame, and switching to a second state; in the second state, judging whether an idle frame buffer exists, if so, switching the state machine to a third state, otherwise, judging whether the hardware is in an idle state; starting hardware decoding when the hardware is in an idle state; when the state machine is switched to a third state, judging whether an idle command queue memory exists, and if not, judging whether the hardware is in an idle state; hardware decoding is started while the hardware is in an idle state.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (9)
1. A method of decoding, comprising:
detecting the state of a state machine set in a decoding process in the process of decoding a current frame in video data to be decoded, wherein the state is used for indicating actions executed in the decoding process;
executing the action corresponding to the state and switching the state of the state machine to execute the following operations: storing hardware decoding configuration parameters in a ping-pong cache mode; analyzing the slice header of the next frame to obtain the hardware decoding configuration parameters of the next frame, and storing the hardware decoding configuration parameters of the next frame into a ping-pong cache; triggering and using the hardware decoding configuration parameters in the ping-pong cache to perform hardware decoding on the video data to be decoded in an interrupt processing function for hardware decoding;
executing the operation by executing the action corresponding to the state and switching the state of the state machine, including: when the state machine is detected to be in a first state, analyzing the slice header of the next frame, and switching to a second state; in the second state, judging whether an idle frame buffer exists, if so, switching the state machine to a third state, otherwise, judging whether the hardware is in an idle state; starting hardware decoding when the hardware is in an idle state; when the state machine is switched to a third state, judging whether an idle command queue memory exists, and if not, judging whether hardware is in an idle state; starting hardware decoding while the hardware is in an idle state.
2. The method of claim 1, wherein when the state machine is in a third state and there is free command queue memory, the method further comprises: and storing the hardware decoding configuration parameters of the next frame into the idle command queue memory.
3. The method of claim 1, further comprising: releasing a command queue memory in an interrupt processing function for hardware decoding; and judging whether a command queue in a readable state exists or not, and if so, starting hardware decoding.
4. A method of decoding, comprising:
detecting the states of a first buffer area and a second buffer area in the process of decoding a current frame, wherein the states comprise: a read-only state and a writable state;
reading hardware decoding configuration parameters for hardware decoding of a current frame from the first buffer area when the first buffer area is in a read-only state and the second buffer area is in a writable state; acquiring the hardware decoding configuration parameter of the next frame, and storing the hardware decoding configuration parameter of the next frame into a second buffer area;
when the hardware equipment for decoding is in an idle state, performing hardware decoding on the current frame by using the hardware decoding configuration parameters read from a specified buffer area, wherein the specified buffer area is the buffer area which is currently in a read-only state in the first buffer area and the second buffer area;
before hardware decoding the current frame using the hardware decoding configuration parameters read from the designated buffer, the method further comprises: triggering detection of whether the hardware device is in an idle state by at least one of: detecting a frame buffer area application failure, wherein the frame buffer area is used for storing image data obtained after decoding the current frame; detecting that a command queue memory application for storing hardware decoding configuration parameters fails; and detecting the following: in an interrupt processing function for hardware decoding, releasing a command queue memory for storing hardware decoding configuration parameters, and changing the command queue memory from a writable state to a read-only state;
storing the hardware decoding configuration parameters of the next frame into a second buffer, comprising: triggering and applying the command queue memory when detecting that the frame buffer area is successfully applied; and when the command queue memory application is detected to be successful, storing the hardware decoding configuration parameters of the next frame into the command queue memory.
5. The method of claim 4, wherein prior to detecting the status of the first buffer and the second buffer, the method further comprises:
and analyzing the slice header of the current frame to obtain the hardware decoding configuration parameters of the current frame.
6. The method according to any one of claims 4 to 5, further comprising: when the first buffer area is changed from a read-only state to a writable state, the second buffer area is changed from a writable state to the read-only state, and when the hardware device for decoding is in an idle state, hardware decoding is performed on a next frame using the hardware decoding configuration parameters of the next frame read from the second buffer area.
7. A decoding apparatus, comprising:
the device comprises a detection module, a decoding module and a processing module, wherein the detection module is used for detecting the state of a state machine set in the decoding process in the process of decoding a current frame in video data to be decoded, and the state is used for indicating actions executed in the decoding process;
the execution module is used for executing the action corresponding to the state and switching the state of the state machine to execute the following operations: storing hardware decoding configuration parameters in a ping-pong cache mode; analyzing the slice header of the next frame to obtain the hardware decoding configuration parameters of the next frame, and storing the hardware decoding configuration parameters of the next frame into a ping-pong cache; triggering and using the hardware decoding configuration parameters in the ping-pong cache to perform hardware decoding on the video data to be decoded in an interrupt processing function for hardware decoding;
the execution module is further configured to, when it is detected that the state machine is in the first state, parse the slice header of the next frame, and switch to the second state; in the second state, judging whether an idle frame buffer exists, if so, switching the state machine to a third state, otherwise, judging whether the hardware is in an idle state; starting hardware decoding when the hardware is in an idle state; when the state machine is switched to a third state, judging whether an idle command queue memory exists, and if not, judging whether hardware is in an idle state; starting hardware decoding while the hardware is in an idle state.
8. A storage medium, characterized in that the storage medium comprises a stored program, wherein when the program runs, a device in which the storage medium is located is controlled to execute the decoding method according to any one of claims 1 to 3; or, performing the decoding method of any one of claims 4-6.
9. A processor, characterized in that the processor is configured to run a program, wherein the program is configured to execute the decoding method according to any one of claims 1 to 3 when the program is run; or, performing the decoding method of any one of claims 4-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710826776.2A CN107613302B (en) | 2017-09-13 | 2017-09-13 | Decoding method and device, storage medium and processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710826776.2A CN107613302B (en) | 2017-09-13 | 2017-09-13 | Decoding method and device, storage medium and processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107613302A CN107613302A (en) | 2018-01-19 |
| CN107613302B true CN107613302B (en) | 2020-10-02 |
Family
ID=61063649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710826776.2A Active CN107613302B (en) | 2017-09-13 | 2017-09-13 | Decoding method and device, storage medium and processor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107613302B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111124577B (en) * | 2019-12-23 | 2021-12-07 | 威创集团股份有限公司 | Screen display control method and electronic equipment |
| CN111683253A (en) * | 2020-06-12 | 2020-09-18 | 浪潮(北京)电子信息产业有限公司 | Parameter set decoding method and device |
| CN111768609B (en) * | 2020-06-29 | 2021-07-23 | 珠海格力电器股份有限公司 | Infrared signal processing method and device |
| CN116737248B (en) * | 2023-08-09 | 2023-11-14 | 武汉凌久微电子有限公司 | Dormancy and awakening method of hard decoder |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102487439A (en) * | 2010-12-01 | 2012-06-06 | 安凯(广州)微电子技术有限公司 | Audio and video acquisition and play processing method with whole embedding of memory |
| CN204697189U (en) * | 2015-07-06 | 2015-10-07 | 深圳市聚视安技术有限公司 | A kind of AHD simulates HD video transducer |
| CN105992005A (en) * | 2015-03-04 | 2016-10-05 | 广州市动景计算机科技有限公司 | Video decoding method and device and terminal device |
| CN106375767A (en) * | 2015-07-24 | 2017-02-01 | 联发科技股份有限公司 | Hybrid video decoder and associated hybrid video decoding method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9148670B2 (en) * | 2011-11-30 | 2015-09-29 | Freescale Semiconductor, Inc. | Multi-core decompression of block coded video data |
-
2017
- 2017-09-13 CN CN201710826776.2A patent/CN107613302B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102487439A (en) * | 2010-12-01 | 2012-06-06 | 安凯(广州)微电子技术有限公司 | Audio and video acquisition and play processing method with whole embedding of memory |
| CN105992005A (en) * | 2015-03-04 | 2016-10-05 | 广州市动景计算机科技有限公司 | Video decoding method and device and terminal device |
| CN204697189U (en) * | 2015-07-06 | 2015-10-07 | 深圳市聚视安技术有限公司 | A kind of AHD simulates HD video transducer |
| CN106375767A (en) * | 2015-07-24 | 2017-02-01 | 联发科技股份有限公司 | Hybrid video decoder and associated hybrid video decoding method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107613302A (en) | 2018-01-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US12003743B2 (en) | Video stream decoding method and apparatus, terminal device, and storage medium | |
| CN107613302B (en) | Decoding method and device, storage medium and processor | |
| US20210076051A1 (en) | Coding apparatus, coding method, decoding apparatus, and decoding method | |
| CN110557670B (en) | Method, device, terminal and storage medium for playing video in webpage | |
| EP2517470B1 (en) | Systems and methods for video-aware screen capture and compression | |
| CN110636346B (en) | Code rate self-adaptive switching method and device, electronic equipment and storage medium | |
| CN112087633B (en) | Video decoding method, device and storage medium | |
| CN104837052A (en) | Playing method of multimedia data and device | |
| EP3410302B1 (en) | Graphic instruction data processing method, apparatus | |
| WO2019184822A1 (en) | Multi-media file processing method and device, storage medium and electronic device | |
| JP7186877B2 (en) | Video decoding control method, device, electronic device and storage medium | |
| WO2020038127A1 (en) | Decoding method and apparatus, electronic device, and storage medium | |
| CN110401866B (en) | Live video display method, device, terminal and storage medium | |
| CN114339412A (en) | Video quality enhancement method, mobile terminal, storage medium and device | |
| CN116450149B (en) | Hardware decoding method, device and storage medium | |
| CN117130749A (en) | Method for improving hardware decoding capability of Web player based on WebGPU | |
| CN112203097A (en) | Adaptive video decoding method and device, terminal equipment and storage medium | |
| WO2020038071A1 (en) | Video enhancement control method, device, electronic apparatus, and storage medium | |
| CN105992055B (en) | video decoding method and device | |
| CN112019858B (en) | Video playing method and device, computer equipment and storage medium | |
| CN114694007A (en) | Video structuring processing method and video structuring engine | |
| US20200137134A1 (en) | Multi-session low latency encoding | |
| CN117135364B (en) | Video decoding method and system | |
| CN115379236B (en) | Video processing method, device, medium and equipment | |
| CN114666514B (en) | Data processing method, device, electronic equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |