CN107612324B - DC converter and method thereof - Google Patents
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- CN107612324B CN107612324B CN201710751594.3A CN201710751594A CN107612324B CN 107612324 B CN107612324 B CN 107612324B CN 201710751594 A CN201710751594 A CN 201710751594A CN 107612324 B CN107612324 B CN 107612324B
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Abstract
the application discloses a direct current converter and a method thereof. The direct current converter includes: the circuit comprises a power switch circuit, a current-voltage converter, a proportional-integral circuit, a voltage-current converter and a logic control circuit. The DC converter eliminates overshoot of the output voltage during system transients.
Description
Technical Field
The present invention relates to an electronic circuit, and more particularly, to a dc converter and a method thereof.
Background
Most electronic products, such as notebook computers, desktop computers, PDAs, etc., require a Direct Current (DC) power supply to provide regulated power to the respective functional modules. The dc converter using Constant On Time (COT) has the advantages of fast transient response speed, simple structure, and the like, and is widely applied to the above fields. COT dc converters typically require slope compensation to stabilize the output voltage.
in the prior art, the slope compensation signal has a fixed slope. When a main power switch of the converter is conducted, the slope compensation signal is reset to zero and then rises with a fixed slope; when the output voltage drops to the sum of the slope compensation signal and the reference voltage, the slope signal is reset to zero again. This is changed over and over.
however, when the load jumps, the output voltage will drop sharply and fall below the reference voltage in a short time. Fig. 1 shows a timing waveform diagram (inductor current IL, switch control signal PWM, output voltage VO, ramp signal VSL, reference voltage VREF, output current IO) of a dc converter employing a conventional ramp compensation technique when a load suddenly jumps to a heavy load. As shown in fig. 1, when the ramp signal VSL is reset to zero for a short time several times, the switching control signal PWM generates a series of pulses. The series of pulses causes the inductor current IL to rise sharply so that when the output voltage VO starts to stabilize the load jump, the energy stored in the inductor will be greater than actually needed. The redundant energy charges the output capacitor after the output current IO is balanced, so that the output voltage VO is pumped high, and an overshoot phenomenon is generated. In some worst case scenarios, even a ring back of the output voltage is generated.
Disclosure of Invention
it is therefore an object of the present invention to solve the above-mentioned problems of the prior art and to provide an improved dc converter and method thereof.
According to an embodiment of the present invention, there is provided a dc converter including: a power switching circuit that is periodically turned on and off to convert an input voltage to an output voltage to supply power to a load; the current-voltage converter is used for converting the difference value of the current sampling signal and the current compensation signal into a voltage compensation signal, wherein the current sampling signal represents the current flowing through the power switch circuit; the proportional-integral circuit is used for integrating the voltage compensation signal to obtain an integral signal; the voltage-current converter is used for converting the integral signal into the current compensation signal; and the logic control circuit generates a switch control signal according to the sum of the voltage compensation signal and the differential voltage representing the output voltage so as to control the power switch circuit.
According to an embodiment of the present invention, there is also provided a dc converter including: a power switching circuit that is periodically turned on and off to convert an input voltage to an output voltage to supply power to a load; a resistor, wherein a difference between a current sample signal and a current compensation signal flows through the resistor, wherein the current sample signal is representative of a current flowing through the power switch circuit; the proportional-integral circuit is used for integrating the voltages at two ends of the resistor to obtain an integral signal; the voltage-current converter is used for converting the integral signal into the current compensation signal; and the logic control circuit receives the differential voltage representing the output voltage through the resistor and generates a switch control signal to control the power switch circuit.
There is also provided, in accordance with an embodiment of the present invention, a method for a dc converter including a power switching circuit receiving an input voltage and generating an output voltage for powering a load, the method including: providing a differential signal representing the output voltage, a current sampling signal representing the current flowing through the power switch circuit; detecting whether the direct current converter is in a steady state: if the direct current converter is in a stable state, generating a current compensation signal which is counteracted with the current sampling signal; controlling the power switch circuit according to the differential signal; and if the direct current converter is in a transient state, controlling the power switch according to the sum of the differential signal and the current sampling signal.
According to the direct current converter and the method thereof in the aspects of the invention, overshoot of the output voltage in the transient process of the system is eliminated, and the stability of the system is ensured.
Drawings
FIG. 1 is a timing waveform diagram of a DC converter employing a prior art slope compensation technique when a load suddenly jumps to a heavy load;
Fig. 2 shows a schematic circuit diagram of the dc converter 100 according to an embodiment of the invention;
fig. 3 is a schematic diagram of a circuit structure of the transient response unit 104 in the dc converter 100 shown in fig. 2 according to an embodiment of the invention;
Fig. 4 is a schematic diagram of a circuit structure of the transient response unit 104 in the dc converter 100 shown in fig. 2 according to an embodiment of the invention;
fig. 5 is a schematic diagram of a circuit structure of the comparison circuit 105 in the dc converter 100 shown in fig. 2 according to an embodiment of the invention;
fig. 6 shows a circuit schematic of a dc converter 200 according to an embodiment of the invention;
fig. 7 is a schematic diagram of the circuit structure of the comparison circuit 105 in the dc converter 200 shown in fig. 6 according to the embodiment of the invention;
Fig. 8 is a schematic diagram showing a circuit configuration of the power switch circuit 103 in the dc converter according to the embodiment of the present invention;
FIG. 9 schematically illustrates a flow chart 300 of a method for a DC converter according to an embodiment of the invention;
Fig. 10 shows a circuit configuration diagram of a dc converter 400 according to an embodiment of the invention;
Fig. 11 shows a circuit configuration diagram of a dc converter 500 according to an embodiment of the invention;
Fig. 12 shows a circuit configuration diagram of a dc converter 600 according to an embodiment of the invention;
Fig. 13 shows a circuit configuration diagram of a dc converter 700 according to an embodiment of the invention;
Fig. 14 shows a circuit configuration diagram of a dc converter 800 according to an embodiment of the invention;
Fig. 15 schematically illustrates a flow chart 900 of a method for a dc converter according to an embodiment of the invention.
Detailed Description
Specific embodiments of the present invention will be described in detail below, and it should be noted that the embodiments described herein are only for illustration and are not intended to limit the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that: it is not necessary to employ these specific details to practice the present invention. In other instances, well-known circuits, materials, or methods have not been described in detail in order to avoid obscuring the present invention.
throughout the specification, reference to "one embodiment," "an embodiment," "one example," or "an example" means: the particular features, structures, or characteristics described in connection with the embodiment or example are included in at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," "one example" or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples. Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. It will be understood that when an element is referred to as being "coupled" or "connected" to another element, it can be directly coupled or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, there are no intervening elements present. Like reference numerals refer to like elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Fig. 2 shows a schematic circuit diagram of the dc converter 100 according to the embodiment of the present invention. In the embodiment shown in fig. 2, the dc converter 100 includes: an input port 101 receiving an input voltage Vin; an output port 102 for providing an output voltage VO; a power switch circuit 103 coupled between the input port 101 and the output port 102; a control circuit providing a switching control signal PWM for controlling the operation of the power switching circuit 103, the control circuit comprising: a transient response unit 104 receiving a sampling signal ICS representing the current flowing through the power switch circuit 103, and generating a transient current signal Vtra; the comparison circuit 105 receives a reference voltage VREF, a feedback voltage VFB representing an output voltage VO, a slope compensation signal VSL and a transient current signal Vtra, and generates a set signal S; the logic control circuit 106 receives the setting signal S, generates the switching control signal PWM, and controls the operation of the power switching circuit 103; when the sum of the output voltage VO and the transient current signal Vtra is less than the sum of the reference voltage VREF and the ramp signal VSL, i.e. when the sum of the output voltage VO and the transient current signal Vtra is less than the sum of the reference voltage VREF and the ramp signal VSL
V+V<V+V (1)
The set signal S triggers the switch control signal PWM.
in one embodiment, the sampling signal ICS may be a current signal; or a voltage signal (e.g., a current flowing through a sampling resistor, thereby causing a corresponding voltage drop across the sampling resistor), where the sampling signal may be represented as VCS. For the sake of uniform expression, the sampled signal is denoted as ICS herein uniformly.
In one embodiment, the transient response unit 104 receives the sampling signal ICS and outputs a transient current signal Vtra reflecting transient information of the sampling signal ICS.
when the load changes (e.g., the load jumps to a heavy load), the output voltage VO decreases, the pulse frequency of the switching control signal PWM increases, the current flowing through the power switch circuit 103 increases, that is, the sampling signal ICS increases, and the transient current signal Vtra also increases. Therefore, according to equation (1), when the change of the output voltage VO becomes gentle, the set signal S triggers the switching control signal PWM with a delay, so that the switching control signal PWM has a reduced number of pulses compared to the related art. Therefore, the energy stored on the inductor in the process of load jump is reduced, the overshoot phenomenon is eliminated, and the system stability is guaranteed.
Fig. 3 is a schematic diagram of a circuit structure of the transient response unit 104 in the dc converter 100 shown in fig. 2 according to an embodiment of the invention. In the embodiment shown in fig. 3, the transient response unit 104 includes: a resistor 41 having a first terminal and a second terminal, the first terminal of which receives the sampling signal ICS; a capacitor 42 coupled between the second terminal of resistor 41 and ground; the operational amplifier 43 is connected across the resistor 41, receives the voltage across the resistor 41, and outputs a transient current signal Vtra.
during system operation, if a load jump (such as a jump to a heavy load) occurs, the sampling signal ICS increases, the voltage across the resistor 41 also increases, and the transient current signal Vtra becomes large. According to equation (1), the set signal S delays triggering the switching control signal PWM as compared to the prior art in which the change of the output voltage VO becomes gentle at this time, so that the number of pulses of the switching control signal PWM is reduced. Therefore, the energy stored in the inductor during the load jump is reduced, and the overshoot phenomenon is eliminated. In the steady state, the average value of the voltage across the resistor 41 is zero due to the capacitor 42. Therefore, the transient response unit 104 provides the transient current signal Vtra reflecting the transient information of the sampling signal ICS, that is, the transient current signal Vtra reflecting the transient information (ac information) of the current flowing through the power switch circuit 103.
Fig. 4 is a schematic circuit diagram of the transient response unit 104 in the dc converter 100 shown in fig. 2 according to an embodiment of the invention. The embodiment shown in fig. 4 is similar to the embodiment shown in fig. 3, and different from the embodiment shown in fig. 3, in the embodiment shown in fig. 4, the transient response unit 104 further includes: a current-to-voltage converter 44, said resistor 41 receiving the sampling signal ICS via the current-to-voltage converter 44. When the sampling signal ICS is a current signal, the current-voltage converter 44 converts the current form into a voltage form, and transmits the voltage form to the first terminal of the resistor 41.
Fig. 5 is a schematic diagram of a circuit structure of the comparison circuit 105 in the dc converter 100 shown in fig. 2 according to an embodiment of the invention. In the embodiment shown in fig. 5, the comparison circuit 105 includes: a comparator 51 having a first input, a second input and an output; a first adder 52, receiving the transient current signal Vtra and the feedback voltage VFB, performing an addition operation on the transient current signal Vtra and the feedback voltage VFB, and then transmitting the result to a first input terminal of the comparator 51; a second adder 53, receiving the reference voltage VREF and the ramp signal VSL, performing an addition operation on the reference voltage VREF and the ramp signal VSL, and then transmitting a result to a second input terminal of the comparator 51; the comparator 51 compares the magnitudes of the first input terminal and the second input terminal thereof to generate the set signal S.
fig. 6 shows a schematic circuit diagram of the dc converter 200 according to the embodiment of the present invention. In the embodiment shown in fig. 6, the dc converter 200 includes: an input port 101 receiving an input voltage Vin; an output port 102 for providing an output voltage VO; a power switch circuit 103 coupled between the input port 101 and the output port 102; a control circuit providing a switching control signal PWM for controlling the operation of the power switching circuit 103, the control circuit comprising: a resistor 41 having a first terminal and a second terminal, the first terminal of which receives a sampling signal ICS representing a current flowing through the power switch circuit 103; a capacitor 42 coupled between the second terminal of the resistor 41 and a reference ground, wherein a voltage across the capacitor 42 is a steady-state current signal Vste; the comparison circuit 105 receives a reference voltage VREF, a feedback voltage VFB representing the output voltage VO, a slope compensation signal VSL, a sampling signal ICS and a steady-state current signal Vste, and generates a set signal S; the logic control circuit 106 receives the set signal S and generates the switching control signal PWM to control the operation of the power switching circuit 103.
in one embodiment, when the sampling signal ICS is in the form of a current, the dc converter 200 further comprises a current-to-voltage converter as shown in fig. 4, the resistor 41 receiving the sampling signal ICS via the current-to-voltage converter.
Fig. 7 is a schematic diagram of the circuit structure of the comparison circuit 105 in the dc converter 200 shown in fig. 6 according to the embodiment of the invention. In the embodiment shown in fig. 7, the comparison circuit 105 includes: a comparator 51 having a first input, a second input and an output; a first adder 52, receiving the sampling signal ICS and the feedback voltage VFB, performing an addition operation on the sampling signal ICS and the feedback voltage VFB, and transmitting a result to a first input terminal of the comparator 51; a second adder 53, receiving the reference voltage VREF, the ramp signal VSL, and the steady-state current signal Vste, performing an addition operation on the three, and then transmitting the result to a second input terminal of the comparator 51; the comparator 51 compares the magnitudes of the first input terminal and the second input terminal thereof to generate the set signal S.
During operation of the dc converter 200, in a steady state, the sampling signal ICS is supplied to a first input of the comparator 53 via the first adder 51, and is supplied to a second input of the comparator 53 via the resistor 41, the capacitor 42 and the second adder 42. Therefore, in a steady state situation, the sampling signal ICS is cancelled by the comparator 53. In a transient state, such as a sudden load jump to a heavy load, the sampling signal ICS increases, and due to the capacitor 42, the potential of the second terminal of the resistor 41 (i.e., the steady-state current signal Vste) cannot suddenly change, so that transient information of the sampling signal ICS is transmitted to the first input terminal of the comparator 53. Therefore, compared with the prior art that the change of the output voltage VO is gradual at this time, the set signal S triggers the switch control signal PWM in a delayed manner, so that the pulse number of the switch control signal PWM is reduced. The energy stored in the inductor during the load jump is reduced and the overshoot phenomenon is eliminated.
Fig. 8 is a schematic diagram showing a circuit configuration of the power switch circuit 103 in the dc converter according to the embodiment of the present invention. In the embodiment shown in fig. 8, the power switch circuit 103 includes a typical buck circuit, that is, includes: the structures of the pull-up power switch 31, the pull-down power switch 32, the inductor 33 and the output capacitor 34 are well known to those skilled in the art, and will not be described in detail for brevity.
Fig. 9 schematically illustrates a flow diagram 300 of a method for a dc converter including a power switching circuit that receives an input voltage and generates an output voltage, in accordance with an embodiment of the present invention.
Step 301, providing a feedback voltage representing the output voltage and a sampling signal representing the current flowing through the power switch circuit;
step 302, determining whether the dc converter is in a steady state: if the DC converter is in a steady state, go to step 303; if the dc converter is in transient state, go to step 305;
Step 303, comparing the sum (VSL + VREF) of the ramp signal VSL and the reference voltage VREF with the magnitude of the feedback voltage VFB, and generating a set signal based on the comparison result;
step 304, generating a transient current signal Vtra representing transient information of the sampling signal;
Step 305, comparing the magnitude of the sum (VSL + VREF) of the ramp signal VSL and the reference voltage VREF with the magnitude of the sum (VFB + Vtra) of the feedback voltage VFB and the transient current signal Vtra, and generating a set signal based on the comparison result;
In step 306, a switch control signal is generated in response to the set signal to control the operation of the power switch circuit.
fig. 10 shows a schematic circuit diagram of a dc converter 400 according to an embodiment of the invention. In the embodiment shown in fig. 10, the dc converter 400 includes: a power switch circuit 401 that is periodically turned on and off to convert the input voltage VIN to an output voltage VO for powering a load (e.g., a central processing unit CPU); a current-voltage converter 402, which converts the difference between the current sampling signal Idroop and the current compensation signal IEA into a voltage compensation signal Vdroop, wherein the current sampling signal Idroop represents the current flowing through the power switch circuit 401; a proportional-integral circuit 403, which integrates the voltage compensation signal Vdroop to obtain an integral signal VEA; a voltage-to-current converter 404 for converting the integrated signal VEA into the current compensation signal IEA; the logic control circuit 405 generates a switching control signal PWM according to a sum of the voltage compensation signal Vdroop and a differential voltage Vdiff representing the output voltage VO to control the power switching circuit 401.
in the embodiment shown in fig. 10, the power switch circuit 401 includes at least a main power switch 4011. When the main power switch 4011 is turned on, the current flowing through the power switch circuit 401 increases; and when the main power switch 4011 is turned off, the current flowing through the power switch circuit 401 decreases. The power switch circuit 401 may further include a second power switch (not shown in fig. 10) controlled to conduct complementarily with the main power switch 4011.
In one embodiment, the dc converter 400 further includes: the adder 406 adds the voltage compensation signal Vdroop and the differential signal Vdiff to generate a voltage feedback signal Vf, wherein the voltage feedback signal Vf is transmitted to the logic control circuit 405 to generate the switching control signal PWM.
In one embodiment, the dc converter 400 further includes: the differential amplifier 407 receives the output voltage VO and generates a differential voltage Vdiff.
In a steady state, when the main power switch 4011 is turned on, the current sampling signal Idroop increases with an increase in current flowing through the power switch circuit 401, and the proportional-integral circuit 403 integrates a change in the current sampling signal Idroop and generates an integral signal VEA reflecting the change in the current sampling signal Idroop. The integrated signal VEA is then converted into a current compensation signal IEA and fed to the current-to-voltage converter 402 together with the current sampling signal Idroop. Since the current-voltage converter 402 converts the difference between the current sampling signal Idroop and the current compensation signal IEA, the current sampling signal Idroop is cancelled by the current compensation signal IEA in a steady state.
In a transient condition (e.g., the load rapidly jumps from a light load to a heavy load in a short time), the output voltage VO decreases. The frequency of the switching control signal PWM increases and the current flowing through the power switching circuit 401 (i.e., the current sampling signal Idroop) rapidly increases. The proportional-integral circuit 403 continues to integrate the change in the current sampling signal Idroop. Due to the rapid change of the current sampling signal Idroop, the integration speed of the proportional-integral circuit 403 is far behind the change of the current sampling signal Idroop, so that the proportional-integral circuit 403 cannot integrate the change of the current sampling signal Idroop in time. At this time, the current sampling signal Idroop cannot be cancelled by the current compensation signal IEA. Therefore, in a transient situation, the current sampling signal Idroop is converted into a voltage compensation signal Vdroop, added to the feedback control loop, and sent to the logic control circuit 405 together with the differential voltage Vdiff to control the operation of the power switch circuit 401. Therefore, the voltage compensation signal Vdroop reflects the transient information of the load current, and the function of the voltage compensation signal Vdroop is the same as that of the transient current signal Vtra in the dc converter 100 of the foregoing fig. 2-5 embodiments. Accordingly, according to equation (1), the change of the output voltage VO becomes gentle, and the switching control signal PWM is triggered with a delay, so that the number of pulses of the switching control signal PWM is reduced. Therefore, the energy stored on the inductor in the process of load jump is reduced, the overshoot phenomenon is eliminated, and the system stability is guaranteed.
Fig. 11 shows a circuit configuration diagram of the dc converter 500 according to the embodiment of the invention. In the embodiment shown in fig. 11, the current-to-voltage converter 402 comprises a resistor. Specifically, in the embodiment shown in fig. 11, the dc converter 500 includes: a power switch circuit 401 that is periodically turned on and off to convert the input voltage VIN to an output voltage VO for powering a load (e.g., a central processing unit CPU); a resistor rdoop, wherein a difference between the current sampling signal Idroop and the current compensation signal IEA flows through the resistor rdoop, wherein the current sampling signal Idroop represents a current flowing through the power switch circuit 401; a proportional-integral circuit 403, which integrates the voltage Vdroop at the two ends of the resistor rdoop to obtain an integral signal VEA; a voltage-to-current converter 404 for converting the integrated signal VEA into the current compensation signal IEA; the logic control circuit 405 generates a switching control signal PWM according to a sum of the voltage compensation signal Vdroop and a differential voltage Vdiff representing the output voltage VO (i.e., the differential voltage Vdiff is supplied to the logic control circuit 405 via a resistor rdoop) to control the power switching circuit 401.
in one embodiment, the current sampling signal Idroop is in the form of a current source and the current compensation signal IEA is in the form of a current sink. The difference flows through resistor rdoop. The resistor rdoop has the function of the current-voltage converter 402, and the voltage at both ends of the resistor rdoop is the voltage compensation signal Vdroop. When the current sampling signal Idroop increases slowly (e.g., when the DC converter 500 is in a steady state condition), the voltage Vdrop across the resistor Rdroop increases accordingly. Accordingly, the integrated signal VEA also increases, so that the current compensation signal IEA also increases. Therefore, the variation of the current sampling signal Idroop is offset by the variation of the current compensation signal IEA. Thus, in steady state conditions, the voltage Vdroop across the resistor rdoop is very small and little current is added to the feedback control loop. However, when the current sampling signal Idroop changes rapidly (such as when the dc converter 500 is in a transient state), the current compensation signal IEA cannot follow the change of the current sampling signal Idroop due to the slow reaction of the proportional-integral circuit 403. At this time, the difference between the current sampling signal Idroop and the current compensation signal IEA starts to be significant and is likely to have the same voltage level as the differential signal Vdiff. Accordingly, the voltage compensation signal Vdroop is added to the differential signal Vdiff and is supplied to the logic control circuit 405. Thus, in the transient case, the feedback control loop contains current information. As described above, the energy stored in the inductor during the load jump is reduced, the overshoot phenomenon is eliminated, and the system stability is guaranteed.
fig. 12 shows a schematic circuit diagram of the dc converter 600 according to the embodiment of the present invention. In the embodiment shown in fig. 12, the circuit configuration of the proportional-integral circuit 403 is schematically shown. Specifically, in the embodiment shown in fig. 12, the proportional-integral circuit 403 includes: and the error amplifier EA is used for amplifying the voltage compensation signal Vdrop and integrating the amplified voltage compensation signal to the capacitor Ci, wherein the voltage at two ends of the capacitor Ci is an integration signal VEA. In one embodiment, the proportional-integral circuit 403 further includes an integral resistor Ri.
Other circuit configurations and operation principles of the dc converter 600 shown in fig. 12 are similar to those of the dc converter 500 shown in fig. 11, and for brevity, detailed descriptions thereof will be omitted.
in one embodiment, the proportional-integral circuit 403 of the dc converter 400 shown in fig. 10 has the same circuit structure as the proportional-integral circuit 403 of the dc converter 600 shown in fig. 12. In other embodiments, the proportional-integral circuit 403 of the dc converter 400 shown in fig. 10 has other circuit configurations.
Fig. 13 shows a circuit schematic of a dc converter 700 according to an embodiment of the invention. The dc converter 700 shown in fig. 13 specifically shows the acquisition of the current sampling signal Idroop. In the embodiment shown in fig. 13, the power switching circuit 401 includes a buck (buck) topology. Like the dc converters 400, 500, and 600 of fig. 10 to 12, the dc converter 700 includes a power switching circuit 401, a current-to-voltage converter 402, a proportional-integral circuit 403, a voltage-to-current converter 404, and a logic control circuit 405, and in the embodiment shown in fig. 13, the dc converter 700 further includes: a sampling switch 4012 for providing a current sampling signal Idroop, wherein the current flowing through the sampling switch 4012 is in mirror proportion to the current flowing through the power switch circuit 401 (i.e., the current flowing through the main power switch 4011). That is, the sampling switch 4012 forms a current mirror with the main power switch 4011 to provide a current sampling signal Idroop for a standard current flowing through the power switch circuit 401.
In one embodiment, the ratio of the current flowing through the sampling switch 4012 to the current flowing through the main power switch 4011 is 1: 10000. Those skilled in the art will appreciate that the current flowing through the sampling switch 4012 may be in any other suitable proportional relationship to the current flowing through the main power switch 4011. In the embodiment shown in fig. 13, the main power switch 4011 and the sampling switch 4012 are both Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), but those skilled in the art will recognize that both Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are used, but those skilled in the art will recognize that other suitable switching devices (such as triode BJT, etc.) may be used for the synchronous rectifier and the switching tube. Other suitable switching devices (e.g., triode BJT, etc.) may be employed.
other circuit configurations and operation principles of the dc converter 700 shown in fig. 13 are similar to those of the dc converter 400 shown in fig. 10, and for brevity, detailed descriptions thereof will be omitted.
Fig. 14 shows a circuit configuration diagram of the dc converter 800 according to the embodiment of the invention. In the embodiment shown in fig. 14, the circuit configuration of the logic control circuit 405 is schematically shown. Specifically, in the embodiment shown in fig. 14, the logic control circuit 405 includes: the comparator 5011 compares the voltage feedback signal Vf (e.g., the sum of the voltage across the resistor rdoop and the differential voltage Vdiff or the sum of the voltage compensation signal Vdroop and the differential voltage Vdiff) with the sum of the reference voltage VREF and the slope compensation signal VSL to generate the set signal S. When the voltage feedback signal Vf is lower than the sum of the reference voltage VREF and the slope compensation signal VSL, the power switch circuit 401 is controlled to be turned on.
in one embodiment, the voltage feedback signal Vf is the sum of the differential signal Vdiff and the voltage compensation signal Vdroop. When the dc converter 800 is in a steady state, the voltage compensation signal Vdroop is very small (e.g., close to zero); when the dc converter 800 is in a transient state, the voltage compensation signal Vdroop may have the same voltage level as the differential signal Vdiff, so that a transient current signal is added to the feedback control loop to improve the system performance.
In the embodiment shown in fig. 14, the dc converter 800 further includes: the RS flip-flop 5012, set by the set signal S, is reset by the constant on-time signal COT to generate the switching control signal PWM.
in one embodiment, the logic control circuit 405 of the dc converter 400 shown in fig. 10 and the logic control circuit 405 of the dc converter 500 shown in fig. 11 have the same circuit configuration as the logic control circuit 405 of the dc converter 800 shown in fig. 14. In other embodiments, the logic control circuit 405 of the dc converter 400 shown in fig. 10 and the logic control circuit 405 of the dc converter 500 shown in fig. 11 have other circuit configurations.
Fig. 15 schematically illustrates a flow chart 900 of a method for a dc converter including a power switching circuit that receives an input voltage and generates an output voltage to power a load (e.g., a CPU), according to an embodiment of the invention, the method comprising:
step 901 provides a differential signal representing the output voltage and a current sampling signal representing the current flowing through the power switch circuit.
step 902, determining whether the dc converter is in a steady state: if the DC converter is in a steady state, go to step 903; otherwise, if the dc converter is in a transient state, step 905 is entered.
step 903, generating a current compensation signal which is cancelled with the current sampling signal.
and 904, controlling the power switch circuit according to the differential signal.
Step 905, controlling the power switch according to the sum of the differential signal and the current sampling signal.
In one embodiment, the current sampling signal is a mirror current of the current flowing through the power switch circuit.
In one embodiment, the method further comprises: the sum of the differential signal and the current sample signal is compared to the sum of the reference voltage and the slope compensation signal. When the sum of the differential signal and the current sampling signal is less than the sum of the reference voltage and the slope compensation signal, the power switch circuit is controlled to be turned on.
While the present invention has been described with reference to several exemplary embodiments, it is understood that the terminology used is intended to be in the nature of words of description and illustration, rather than of limitation. As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.
Claims (10)
1. a dc converter, comprising:
a power switching circuit that is periodically turned on and off to convert an input voltage to an output voltage to supply power to a load;
The current-voltage converter is used for converting the difference value of the current sampling signal and the current compensation signal into a voltage compensation signal, wherein the current sampling signal represents the current flowing through the power switch circuit;
The proportional-integral circuit is used for integrating the voltage compensation signal to obtain an integral signal;
The voltage-current converter is used for converting the integral signal into the current compensation signal;
And the logic control circuit generates a switch control signal according to the sum of the voltage compensation signal and the differential voltage representing the output voltage so as to control the power switch circuit.
2. The dc converter of claim 1, further comprising:
and the sampling switch is used for providing the current sampling signal, wherein the current flowing through the sampling switch is in mirror proportion to the current flowing through the power switch circuit.
3. The dc converter of claim 1, wherein the proportional-integral circuit comprises:
And the error amplifier amplifies the voltage compensation signal and integrates the amplified voltage compensation signal to a capacitor, wherein the voltage at two ends of the capacitor is the integrated signal.
4. The dc converter of claim 1, wherein the logic control circuit comprises:
The comparator compares the sum of the voltage compensation signal and the differential voltage with the sum of the reference voltage and the slope compensation signal to generate a setting signal; when the sum of the voltage compensation signal and the differential voltage is lower than the sum of the reference voltage and the slope compensation signal, the power switch circuit is controlled to be conducted.
5. A dc converter, comprising:
a power switching circuit that is periodically turned on and off to convert an input voltage to an output voltage to supply power to a load;
a resistor, wherein a difference between a current sample signal and a current compensation signal flows through the resistor, wherein the current sample signal is representative of a current flowing through the power switch circuit;
The proportional-integral circuit is used for integrating the voltages at two ends of the resistor to obtain an integral signal;
the voltage-current converter is used for converting the integral signal into the current compensation signal;
And a logic control circuit receiving the differential voltage representing the output voltage via the resistor to generate a switch control signal to control the power switch circuit according to a sum of a voltage compensation signal and the differential voltage representing the output voltage, wherein the voltage compensation signal is a voltage across the resistor.
6. The dc converter of claim 5, further comprising:
And the sampling switch is used for providing a current sampling signal, wherein the current flowing through the sampling switch is in a mirror proportion relation with the current flowing through the power switch circuit.
7. The dc converter of claim 5, wherein the proportional-integral circuit comprises:
and the error amplifier amplifies the voltage compensation signal and integrates the amplified voltage compensation signal to a capacitor, wherein the voltage at two ends of the capacitor is the integrated signal.
8. The dc converter of claim 5, wherein the logic control circuit comprises:
The comparator compares the sum of the voltage compensation signal and the differential voltage with the sum of the reference voltage and the slope compensation signal to generate a setting signal; when the sum of the voltage compensation signal and the differential voltage is lower than the sum of the reference voltage and the slope compensation signal, the power switch circuit is controlled to be conducted.
9. a method for use in a dc converter including a power switching circuit that receives an input voltage and generates an output voltage to power a load, the method comprising:
Providing a differential signal representing the output voltage, a current sampling signal representing the current flowing through the power switch circuit;
detecting whether the direct current converter is in a steady state:
if the direct current converter is in a stable state, generating a current compensation signal which is counteracted with the current sampling signal;
Controlling the power switch circuit according to the differential signal;
And if the direct current converter is in a transient state, controlling the power switch according to the sum of the differential signal and the current sampling signal.
10. the method of claim 9, further comprising:
comparing the sum of the differential signal and the current sampling signal with the sum of the reference voltage and the slope compensation signal; when the sum of the differential signal and the current sampling signal is less than the sum of the reference voltage and the slope compensation signal, the power switch circuit is controlled to be turned on.
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|---|---|---|---|
| US15/623,265 | 2017-06-14 | ||
| US15/623,265 US10348197B2 (en) | 2015-11-12 | 2017-06-14 | DC-DC converter with transient control and the method thereof |
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| CN107612324B true CN107612324B (en) | 2019-12-06 |
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