CN107611082A - For the method for the passivation layer for forming the power semiconductor with high reliability - Google Patents
For the method for the passivation layer for forming the power semiconductor with high reliability Download PDFInfo
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- CN107611082A CN107611082A CN201610768930.0A CN201610768930A CN107611082A CN 107611082 A CN107611082 A CN 107611082A CN 201610768930 A CN201610768930 A CN 201610768930A CN 107611082 A CN107611082 A CN 107611082A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3211—Nitridation of silicon-containing layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05H—PLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY-CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
- H05H1/00—Generating plasma; Handling plasma
- H05H1/24—Generating plasma
- H05H1/46—Generating plasma using applied electromagnetic fields, e.g. high frequency or microwave energy
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- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
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- Formation Of Insulating Films (AREA)
Abstract
According to the one side of the disclosure, a kind of method for being used to form the passivation layer of power semiconductor, the top plasma activated chemical vapour deposition ratio being included in plasma-deposited chamber in the metal line of power semiconductor is 400 ± 3%sccm:100 ± 3%sccm:3800 ± 3%sccm SiH4:NH3:N2Gas, to form the silicon nitride film with high index of refraction.
Description
Technical field
A kind of this disclosure relates to method for being used to form the passivation layer of the power semiconductor with high reliability.
Background technology
Passivation layer is formed on the bottom of semiconductor devices and on the top of metal wiring layer, and final metal line is at this
Metal wiring layer is formed to protect internal circuit to be not exposed to external environment condition by semiconductor devices, so as to prevent tracking current,
And the stabilizing device characteristic, breakdown voltage etc. when manufacturing semiconductor.
Passivation layer is also prevented from due to interface short circuit caused by conductive particle and rupture.
Use silica (SiO2)/silicon nitride (Si3N4), PSG (phosphosilicate glass：SiO2/P2O5) material etc. is via CVD side
Method forms the passivation layer of semiconductor devices.
More generally, using compared with silica with more preferable insulation characterisitic, finer and close and with the nitridation of more high rigidity
Silicon forms the passivation layer of semiconductor devices.
With the development of information communicating agent meeting, the large scale integrated circuit of high integration and high speed (LSI) is extremely needed.
As semiconductor devices becomes highly integrated, width and gap between wiring all significantly reduce.Need to have for manufacture
The technology of this semiconductor devices of multilayer wiring is to realize required electrical characteristics and high integration.This silicon-based power semiconductor
Device (such as IGCT, MOSFET and IGBT) has been widely used in various fields, such as industry, consumer electronics and communication neck
Domain.
In addition to high pressure blocking capability, high current transmittability and faster switching characteristics, power semiconductor needs
With high temperature characterisitic and high reliability so that it will not be changed by external environment condition is influenceed.
Because when the measured power semiconductor devices under the conditions of specific external environment, reliability can be by passivation layer shadow
Ring, therefore extremely need to develop and a kind of there is high reliability and good electrical under rough ambient environmental condition such as high temperature
Passivation layer.
Prior art
KR2003-0096831 (a kind of method for forming semiconductor device protecting layer)
The content of the invention
Present invention is provided so as to introduce the hair to hereafter further describing in a specific embodiment in simplified form
The selection of bright design.The content of the invention is not intended to the key feature or inner characteristic for determining claimed subject matter, is also not intended to use
In the scope for assisting in claimed subject matter.
The purpose of the disclosure is that provide one kind has height can for being formed under rough ambient environmental condition such as high temperature
By the method for the power semiconductor passivation layer of property.
It should be appreciated that the purpose of the disclosure is not limited and by specifically describing specific exemplary reality hereafter by above-mentioned purpose
Example is applied, other purposes can become apparent from.
According to the one side of the disclosure, there is provided a kind of to be used to form the power semiconductor passivation layer with high reliability
Method, be included in plasma-deposited chamber power semiconductor metal line top with 400 ± 3%sccm:
100 ± 3%sccm:3800 ± 3%sccm ratio plasma activated chemical vapour deposition SiH4:NH3:N2Gas, have to be formed
The silicon nitride film of high index of refraction.
Plasma activated chemical vapour deposition can be under conditions of 4.25 ± 3% supports and 400 ± 3% DEG C plasma-deposited
Carried out in chamber.
Plasma activated chemical vapour deposition is executable to have thickness up to 12 ± 3% seconds to be formedRolled over height
Penetrate the silicon nitride film of rate.
Plasma activated chemical vapour deposition is executable to have thickness up to 71 ± 3% seconds to be formedRolled over height
Penetrate the silicon nitride film of rate.
The refractive index of silicon nitride film can be 24 ± 0.1.
Confrontation electricity question such as tracking current and breakdown voltage are had according to the silicon nitride film of the embodiment of the present disclosure
High reliability.
Brief description of the drawings
Hereinafter, the embodiment shown in refer to the attached drawing is described.It is identical in accompanying drawing in order to help to understand following description
Reference numeral represents similar elements.It is used for the purpose of describing that the embodiment shown in purpose is described below through the element shown in accompanying drawing
Example, and be not used in limitation scope described below.
Fig. 1 is to show the first silicon nitride film (Si according to the embodiment of the present disclosure3N4) and HR silicon nitride films (HR-Si3N4)
The chart of refractive index.
Fig. 2 is to show the work(with or without passivation layer and dependent on the passivation channel type according to the embodiment of the present disclosure
The electrical characteristics of THE ELECTRICAL DIE SORTING (EDS) TEST (fulgurite core class test) assessment result of rate semiconductor
Distribution map.
Fig. 3 is the electrical characteristics for showing the power semiconductor without passivation layer before high temperature reverse bias (HTRB) test
Table.
Fig. 4 is the electrical characteristics for showing the power semiconductor without passivation layer after high temperature reverse bias (HTRB) test
Table.
Fig. 5 is to show to deposited first according to the embodiment of the present disclosure thereon before high temperature reverse bias (HTRB) is tested
The table of the electrical characteristics of the power semiconductor of silicon nitride film.
Fig. 6 is to show to deposited first according to the embodiment of the present disclosure thereon after high temperature reverse bias (HTRB) is tested
The table of the electrical characteristics of the power semiconductor of silicon nitride film.
Fig. 7 is to show to deposited HR nitrogen according to the embodiment of the present disclosure thereon before high temperature reverse bias (HTRB) is tested
The table of the electrical characteristics of the power semiconductor of SiClx film.
Fig. 8 is to show to deposited HR nitrogen according to the embodiment of the present disclosure thereon after high temperature reverse bias (HTRB) is tested
The table of the electrical characteristics of the power semiconductor of SiClx film.
Embodiment
Terminology used herein is meant only to describe some embodiments, and does not limit the disclosure in any way.Unless
Clearly use in addition, the expression of odd number includes plural reference.In this manual, such as " comprising " or " by ... form " expression
Be intended to specify a feature, quantity, step, operation, element, part or its combination, and it is not considered that exclude it is one or more its
His feature, quantity, step, operation, element, appearance or the possibility of part or its combination.Moreover, the term used in the disclosure
" on " mean on the top of an object or on bottom.It does not mean that is only located on top based on gravity direction.
Hereinafter, will be described in detail according to method of the disclosure for forming the power semiconductor passivation layer with high reliability
Preferred embodiment.
In accordance with an embodiment of the present disclosure, there is the silicon nitride film (Si of high reliability, switching characteristic and insulating properties3N4)
Formed as passivation layer on the bottom of power semiconductor and on the top of the last wiring layer of power semiconductor.
With silicon oxide film (SiO2) compare, silicon nitride film is finer and close and has more high rigidity so that silicon nitride film is more suitable for
Passivation layer is to prevent impurity or physical damage.
Use SiH4、NH3And N2Admixture of gas via chemical vapor deposition (CVD) method formed silicon nitride film.
CVD method is the method that solid product is deposited on power semiconductor, via by the way that chemical deposition is reacted
Gas is injected into the chemical reaction occurred in plasma-deposited chamber and produces the solid product.
The physical characteristic of silicon nitride film can be with SiH4、NH3And N2Blending ratio change.
For example, after it will form the semiconductor devices positioning in the chamber of metal line thereon, via plasma
Chemical gaseous phase depositing process is with 260sccm:130sccm:3800sccm ratio is by SiH4、NH3And N2Mixed gas be injected into
On the metal wiring layer of power semiconductor, to form the first silicon nitride film with refractive index 1.9 ± 0.1.
When performing depositing operation up to 11.4 seconds, formation has thicknessThe first silicon nitride film.
In the case of power MOSFET device, due to raw material, with the increase of leakage current under high temperature, breakdown potential
Pressure (BV) characteristic can change, it is therefore desirable to which provide has the passivation layer for stablizing electrical characteristics at high temperature.
In accordance with an embodiment of the present disclosure, by controlling SiH during the first silicon nitride film preparation technology4:NH3:N2Gas
Combination ratio, may be formed under high temperature there are high reliability, high index of refraction and stable electrical characteristics high refraction silicon nitride film (with
Under, it is referred to as " HR silicon nitride films ").
By via depositing operation with 400 ± 3%sccm:100 ± 3%sccm:3800 ± 3%sccm combination ratio note
Enter SiH4:NH3:N2Gas, according to the HR silicon nitride films (HR-Si of the embodiment of the present disclosure3N4) power semiconductor can be formed on
On metal wiring layer top.
HR silicon nitride films can have 2.4 ± 0.1 refractive index.
In accordance with an embodiment of the present disclosure, when via plasma activated chemical vapour deposition technique in 4.25 ± 3% supports, 400 ±
400 ± 3%sccm is injected under the conditions of 3% DEG C:100 ± 3%sccm:The SiH of 3800 ± 3%sccm combination ratios4:NH3:N2Gas
Body into deposition chambers up to 12 ± 3% seconds when, HR silicon nitride films (HR-Si3N4) metal line of power semiconductor can be formed on
With with thickness on layer top
According to another embodiment of the disclosure, when via plasma activated chemical vapour deposition technique in 4.25 ± 3% supports,
400 ± 3%sccm is injected under the conditions of 400 ± 3% DEG C:100 ± 3%sccm:The SiH of 3800 ± 3%sccm combination ratios4:NH3:
N2Gas into deposition chambers up to 171 ± 3% seconds when, HR silicon nitride films (HR-Si3N4) gold of power semiconductor can be formed on
Belong on wiring layer top with thickness
As injection SiH4When gas flow is more than 400+3%sccm, powder can be produced during film is formed, so that HR nitrogen
The defects of SiClx film, ratio uprised.On the other hand, as injection SiH4When gas flow is less than 400-3%sccm, physical characteristic can become
Poor and to external environment condition repellence reduces.
In accordance with an embodiment of the present disclosure, molecular structure/bonding of film can change according to the combination ratio of gas, this meeting
Further change refractive index.
Fig. 1 is to show the first silicon nitride film (Si according to the embodiment of the present disclosure3N4) and HR silicon nitride films (HR-Si3N4)
The table of refractive index.
With reference to figure 1, it shows the disk 100 that deposited the power semiconductor of silicon nitride film thereon.
As shown in Fig. 1 the first nitride rows, it may be determined that there is thicknessThe first silicon nitride film (Si3N4)
Refractive index, and at 13 points refractive index average value be 1.927.Such as Fig. 1 HR nitrideShown by row,
It can determine that thickness isHR silicon nitride films (HR-Si3N4) refractive index, and the refractive index average value at 13 points is
2.357.Such as Fig. 1 HR nitrideShown in row, it may be determined that thickness isHR silicon nitride films (HR-
Si3N4) refractive index, and at 13 points refractive index average value be 2.399.
In accordance with an embodiment of the present disclosure, do not form the power semiconductor (non-passivation) of passivation layer thereon, formed thereon
The power semiconductor of first silicon nitride film (normal nitride passivation) and the power for foring HR silicon nitride films thereon
The electrical characteristics of semiconductor devices (HR- nitride passivations) are compared to each other, with true by performing high temperature reverse bias (HTRB) test
Determine the reliability of HR silicon nitride films.
High temperature reverse bias (HTRB) test applies the stress higher than rated value with accelerated wear test, so as to assess certain time
Interior degeneration.According to JESD22-A108D HTRB, in the intelligence system of South Korea Zhong Bei Technology Parks (Chungbuk Technopark)
System center, HTRB tests are performed under 150 DEG C of high temperature and backward voltage up to 168 hours.
In the case of power MOSFET device, due to the property of raw material, at high temperature breakdown voltage (BV) characteristic with
Leakage current increase and change, therefore this is an important factor for reducing reliability change at high temperature.
Reliability be defined as power semiconductor under certain condition with appointed interval perform its expectation function can
Can property.
Fig. 2 is to show according to the disclosure to be implemented with or without the passivation layer according to the embodiment of the present disclosure and foundation
The electrical characteristics distribution map of the assessment result of fulgurite core classification (EDS) test of the power semiconductor of the type of the passivation layer of example.
With reference to figure 2, to the power semiconductor with or without passivation layer and the work(with different type passivation layer
Rate semiconductor carries out fulgurite core classification (EDS) test.By result it is noted that all dense distribution in center (avette part),
This means electrical characteristics, tested person does not influence and keeps constant.
Fig. 3 is the electrical characteristics for showing the power semiconductor without passivation layer before high temperature reverse bias (HTRB) test
Table.
Fig. 4 is the electrical characteristics for showing the power semiconductor without passivation layer after high temperature reverse bias (HTRB) test
Table.
With reference to figure 3 and 4, when power semiconductor of the contrast without passivation layer is before high temperature reverse bias (HTRB) test
During electrical characteristics afterwards, compared with before test, the breakdown voltage (BVDSS) after testing averagely reduces 48.42V, and
Drain-source leakage current (IDSS) averagely adds 0.78uA.In addition, gate-source forwards/reverse leakage current (ISGS_F/ISGS_R) is flat
Respectively add 48.05nA/50.76nA.
Fig. 5 is to show to deposited the in accordance with an embodiment of the present disclosure thereon before high temperature reverse bias (HTRB) test
The table of the electrical characteristics of the power semiconductor of one silicon nitride film.Fig. 6 is shown in high temperature reverse bias (HTRB) test after it
On deposited in accordance with an embodiment of the present disclosure the first silicon nitride film power semiconductor electrical characteristics table.
With reference to figure 5 and 6, the power that deposited the first silicon nitride film in accordance with an embodiment of the present disclosure thereon when contrast is partly led
Body compared with before test, tests it when high temperature reverse bias (HTRB) is tested up to electrical characteristics before and after 168 hours
Breakdown voltage (BVDSS) afterwards averagely reduces 31.32V, and drain-source leakage current (IDSS) averagely adds 0.39uA.In addition,
Gate-source forwards/reverse leakage current (ISGS_F/ISGS_R) is average to add 24.0nA/23.526nA respectively.
Fig. 7 is to show to deposited HR in accordance with an embodiment of the present disclosure thereon before high temperature reverse bias (HTRB) test
The table of the electrical characteristics of the power semiconductor of silicon nitride film.Fig. 8 is to show after high temperature reverse bias (HTRB) test thereon
The table of the electrical characteristics of the power semiconductor of HR silicon nitride films is deposited in accordance with an embodiment of the present disclosure.
With reference to figure 7 and 8, when contrast deposited the power semiconductor of HR silicon nitride films in accordance with an embodiment of the present disclosure thereon
High temperature reverse bias (HTRB) test before and after electrical characteristics when, with test before compared with, the breakdown potential after testing
Pressure (BVDSS) averagely reduces 3.71V, and drain-source leakage current (IDSS) averagely adds 0.01uA.In addition, gate-source it is positive/
Reverse leakage current (ISGS_F/ISGS_R) is average to add 3.66nA/1.15nA respectively.
Result is summarized in table 1.
[table 1]
According to table 1, it is noted that compared with it deposited the power semiconductor of the first silicon nitride film thereon, deposited thereon
The power semiconductor of HR silicon nitride films breakdown potential pressure difference before and after 168 hours HTRB are tested reduces 12%.IDSS leaks
Difference between current, which reduces 2.56%, ISGS (F) leakage current difference, reduces 15.2%, and ISGS (R) leakage current difference reduces 4.9%.
It was determined that with depositing other passivation layers or the (nitridation of normal nitride passivation layer on power semiconductor
Silicon fiml) when compare, when HR silicon nitride films as passivation layer deposition when on power semiconductor, its resist external condition change
Change such as high temperature shows higher reliability and electrical property change is very small.
HR silicon nitride films according to embodiments of the present invention can improve moisture resistivity, to protect the circuit of semiconductor devices (chip)
Figure and surface.
HR nitride films according to embodiments of the present invention can specify wire bond area during packaging technology.
HR silicon nitride films according to embodiments of the present invention can provide the reliability higher than conventional passivation layer.
Although it is described by reference to specific embodiment, but it is to be understood that those skilled in the art are not departing from
As various change can be carried out in the case of the spirit and scope of appended claims and its embodiment herein of equivalent restriction
And modification.Therefore, example described herein is only used for explaining and being not intended to limit the disclosure.The scope of the present disclosure should be under
The claim of text is explained, and should be construed as the model that all spiritual equivalents of claims which follow both fall within the disclosure
Enclose.
Claims (5)
1. a kind of method for being used to form the passivation layer of power semiconductor, is included in plasma-deposited chamber and is partly led in power
The top plasma activated chemical vapour deposition ratio of the metal line of body device is 400 ± 3%sccm:100 ± 3%sccm:
3800 ± 3%sccm SiH4:NH3:N2Gas is carried out, to form the silicon nitride film with high index of refraction.
2. the method for claim 1, wherein in 4.25 ± 3% supports and 400 ± 3% in plasma-deposited chamber
Plasma activated chemical vapour deposition is performed under conditions of DEG C.
3. method as claimed in claim 2, wherein plasma activated chemical vapour deposition is performed up to 12 ± 3% seconds, to form thickness
Spend and beAnd the silicon nitride film with high index of refraction.
4. method as claimed in claim 2, wherein plasma activated chemical vapour deposition is performed up to 71 ± 3% seconds, to form thickness
Spend and beAnd the silicon nitride film with high index of refraction.
5. the refractive index of the method as described in claim 1, wherein silicon nitride film is 24 ± 0.1.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2016-0088180 | 2016-07-12 | ||
| KR1020160088180A KR20180007386A (en) | 2016-07-12 | 2016-07-12 | method for forming a passivation layer of a power semiconductor having high reliability |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011187858A (en) * | 2010-03-11 | 2011-09-22 | Shin-Etsu Chemical Co Ltd | Method of manufacturing solar cell, and solar cell |
| CN102804350A (en) * | 2010-03-15 | 2012-11-28 | 应用材料公司 | Silicon nitride passivation layer for covering high aspect ratio features |
| CN103924212A (en) * | 2013-01-10 | 2014-07-16 | 无锡华润上华半导体有限公司 | Preparation method for silicon nitride thin film |
-
2016
- 2016-07-12 KR KR1020160088180A patent/KR20180007386A/en not_active Application Discontinuation
- 2016-08-30 CN CN201610768930.0A patent/CN107611082A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011187858A (en) * | 2010-03-11 | 2011-09-22 | Shin-Etsu Chemical Co Ltd | Method of manufacturing solar cell, and solar cell |
| CN102804350A (en) * | 2010-03-15 | 2012-11-28 | 应用材料公司 | Silicon nitride passivation layer for covering high aspect ratio features |
| CN103924212A (en) * | 2013-01-10 | 2014-07-16 | 无锡华润上华半导体有限公司 | Preparation method for silicon nitride thin film |
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