CN107608843B - Method for verifying successful interconnection of chip interfaces and first chip thereof - Google Patents
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Abstract
The embodiment of the application provides a method for verifying the successful interconnection of chip interfaces, which comprises the following steps: determining that the ith attempt of interconnection of the high-speed interfaces of the first chip and the second chip is successful; and when the number of times of successful interconnection attempts of the high-speed interfaces of the first chip and the second chip reaches a threshold number N, determining that the interconnection of the first chip and the second chip is successful, wherein i is a positive integer smaller than or equal to N, and N is a positive integer. Therefore, the embodiment of the application provides a method for improving the successful interconnection of the high-speed interconnection interface on the premise of not changing the original hardware design aiming at the current situation that the interconnection of the high-speed interconnection interface is easy to fail, and improves the success rate and the reliability of the interconnection of the high-speed interconnection interface.
Description
Technical Field
The invention relates to the technical field of information, in particular to a method for verifying successful interconnection of a high-speed interconnection interface of a chip and a first chip thereof.
Background
With more and more services and more complexity in daily life, the performance requirement on the server is higher and higher, and in order to provide the performance of the server, the requirement of people on the performance of the server cannot be met by improving the performance of a single CPU node, so that the number of paths of CPUs in the server needs to be improved to improve the performance.
The server interconnection chip (CC chip) is a core chip of a multi-path processor shared main memory system, and has the main functions of maintaining the consistency of the global cache and realizing global IO sharing and full system interruption. In order for a system to have good utility performance, the overall performance of a mass-shared storage application is required to grow approximately linearly as the system size increases.
With the increasing scale of chip design, the functions of the chip become more complex, and the verification stage of the chip occupies most of the time of the whole chip development. In order to shorten the verification time, many new verification means, such as Software Driven Verification (SDV), Bus Function Module (BFM), etc., and a prototype verification technology based on Field-Programmable Gate Array (FPGA), are emerging on the basis of the conventional simulation verification.
The development of most chips adopts the FPGA prototype verification technology, and in the process of the FPGA prototype verification of the chips, the whole design of the chips cannot be transplanted to a single chip due to the increasing design scale of the chips, so that the design is reasonably cut and transplanted to each chip respectively. High-speed interfaces between chips need to be interconnected in advance, however, the reliability of verifying whether the interconnection of the high-speed interfaces between the chips is successful is not high, and if data transmission between the chips is in problem, the chips need to be reset or bit streams need to be reloaded, which brings great difficulty to system debugging.
Therefore, a method for verifying the success of chip interface interconnection is needed.
Disclosure of Invention
The embodiment of the invention provides a method for verifying the success of chip interface interconnection, which can improve the reliability of verifying the success of chip interface interconnection.
In a first aspect, an embodiment of the present invention provides a method for verifying successful interconnection of chip interfaces, where the method includes: determining that the ith attempt of interconnection of the high-speed interfaces of the first chip and the second chip is successful; and when the number of times of successful interconnection attempts of the high-speed interfaces of the first chip and the second chip reaches a threshold number N, determining that the interconnection of the first chip and the second chip is successful, wherein i is a positive integer smaller than or equal to N, and N is a positive integer.
With reference to the first aspect, in a first possible implementation manner of the first aspect, the determining that the first chip and the second chip are successfully interconnected in the ith attempt includes: the first chip sends a first training sequence set to the second chip; and after the second chip receives the first training set, the first chip receives a second training sequence set sent by the second chip, and the first training set is a proper subset of the second training set.
With reference to the first aspect and the foregoing implementation manner of the first aspect, in a second possible implementation manner of the first aspect, the determining that the first chip and the second chip are successfully interconnected in the ith attempt includes: the first chip sends a first training sequence set to the second chip; when the first chip does not receive the second chip sending a second training sequence set, the first chip sends the first training set to the second chip again, wherein the first training set is combined into a proper subset of the second training set.
With reference to the first aspect and the foregoing implementation manner of the first aspect, in a third possible implementation manner of the first aspect, the determining that the first chip and the second chip are successfully interconnected in the ith attempt includes: and the first chip determines that the ith attempted interconnection between the first chip and the second chip is successful according to the attempted interconnection success confirmation message sent by the second chip.
With reference to the first aspect and the foregoing implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, the first chip is one of the following chips: an FPGA chip, a Programmable Logic Device (CDLP) in charge; or, the second chip is one of the following chips: FPGA chip, CPLD chip.
With reference to the first aspect and the foregoing implementation manner of the first aspect, in a fifth possible implementation manner of the first aspect, the method further includes:
and when the first chip receives the first training sequence set sent by the second chip, sending a second training sequence set to the second chip.
In a second aspect, a first chip is provided, which includes: the processing unit is used for determining that the ith attempt of interconnection of the high-speed interfaces of the first chip and the second chip is successful; the determining unit determines that the interconnection between the first chip and the second chip is successful when the number of times of successful interconnection attempts of the high-speed interfaces of the first chip and the second chip reaches a threshold number of times N, wherein i is a positive integer smaller than or equal to N, and N is a positive integer.
With reference to the second aspect, in a first possible implementation manner of the second aspect, the processing unit is specifically configured to: sending a first training sequence set to the second chip; after the second chip receives the first training set, the processing unit is further configured to receive a second training sequence set sent by the second chip, where the first training set is a proper subset of the second training set.
With reference to the second aspect and the foregoing implementation manner of the second aspect, in a second possible implementation manner of the second aspect, the processing unit is specifically configured to: sending a first training sequence set to the second chip; when the processing unit does not receive that the second chip sends a second training sequence set, the processing unit sends the first training set to the second chip again, wherein the first training set is combined into a proper subset of the second training set.
With reference to the second aspect and the foregoing implementation manner of the second aspect, in a third possible implementation manner of the second aspect, the processing unit is specifically configured to: and determining that the ith attempted interconnection between the first chip and the second chip is successful according to the attempted interconnection success confirmation message sent by the second chip.
With reference to the second aspect and the foregoing implementation manner of the second aspect, in a third possible implementation manner of the second aspect, the first chip is one of the following chips: FPGA chip, CPLD chip; or, the second chip is one of the following chips: FPGA chip, CPLD chip.
In a third aspect, a controlled terminal is provided, including: a processor; a memory for storing instructions for execution by the processor;
wherein the processor is configured to perform the first aspect or any one of the possible implementations of the first aspect.
Therefore, the embodiment of the application provides a method for improving the successful interconnection of the high-speed interconnection interfaces on the premise of not changing the original hardware design aiming at the current situation that the interconnection of the high-speed interconnection interfaces is easy to fail, a closed loop is formed among the high-speed interconnection interfaces of the chips, the success rate and the reliability of the interconnection of the high-speed interconnection interfaces are improved, the manual participation is reduced, the debugging process is accelerated, and the research and development period of the chips is greatly shortened.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic flow chart diagram of a method of one embodiment of the present application.
Fig. 2 is a schematic diagram of another embodiment of the present application.
Fig. 3 is a schematic flow chart of yet another embodiment of the present application.
Fig. 4 is a schematic block diagram of a first chip of the present application.
Fig. 5 is a schematic structural diagram of a controlled terminal according to an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be understood that the first and second embodiments are only used to distinguish different chips, different training sequences, etc. and the present application is not limited thereto.
It should be further understood that the embodiment of the present invention is illustrated by taking the highspeed interface Aurora of Xilinx as an example, but is not limited to the highspeed interface Aurora of Xilinx, nor to the interconnection of two FPGA chips. Various types of high speed interfaces are suitable for the present invention.
Fig. 1 shows a schematic flow diagram of a method of one embodiment of the present application.
As shown in fig. 1, the main execution body of the method is a chip, and the method includes:
step 210, it is determined that the ith attempt of interconnection of the high-speed interfaces of the first chip and the second chip is successful.
Step 220, when the number of times of successful interconnection attempts of the high-speed interfaces of the first chip and the second chip reaches a threshold number N, determining that the interconnection of the first chip and the second chip is successful, wherein i is a positive integer less than or equal to N, and N is a positive integer.
Specifically, in step 210 or 220, a successful interconnection attempt of the high-speed interfaces of the first chip and the second chip does not mean that the two chips are successfully interconnected, and only after the first chip and the second chip are successfully interconnected through N interconnection attempts, it can be determined that the first chip and the second chip are successfully interconnected.
It should be understood that the training actions of the first chip and the second chip are the same during the interconnection process and are working simultaneously.
After the power is on, the second chip sends the first training sequence while the sending module of the first chip sends the first training. Both the first chip and the second chip operate in a duplex manner.
Alternatively, N may be 1000,2000,5000,10000, etc., and the application is not limited.
Optionally, the determining that the first chip and the second chip are successfully interconnected in the ith attempt includes: the first chip sends a first training sequence set to the second chip; and after the second chip receives the first training set, the first chip receives a second training sequence set sent by the second chip, and the first training set is a proper subset of the second training set.
Specifically, the first training sequence set may include sequence 0 and sequence 1, and the second training sequence set may include sequence 0, sequence 1, sequence 2, and sequence 3.
It should be understood that the training sequences in the first training sequence set may be configured arbitrarily, and are exemplified by 0,1,2, and 3, and the present application is not limited thereto.
That is, after the first chip sends the first training sequence set to the second chip, if the second chip receives the first training sequence set, the second chip sends the second training combination to the first chip, so as to prove that the first chip and the second chip successfully attempt to interconnect at the ith time.
Optionally, as an embodiment of the present application, the determining that the first chip and the second chip are successfully interconnected in the ith attempt includes: the first chip sends a first training sequence set to the second chip; when the first chip does not receive the second chip sending a second training sequence set, the first chip sends the first training set to the second chip again, wherein the first training set is combined into a proper subset of the second training set.
That is, after the first chip sends the first training sequence set to the second chip, if the second chip does not successfully receive the first training sequence set, or the second chip successfully receives the first training sequence set and sends the second training sequence set to the first chip, but the first chip does not receive the second training sequence set, the first chip will resend the first training set to the second chip.
It should be understood that the first chip and the second chip have a pre-agreed protocol or a protocol that knows the first training set and the second training set, and it should be further understood that the first training sequence set transmitted by the first chip each time may be the same or different; it should also be understood that the first training sequence set sent by the second chip each time may be the same or different, and the present application is not limited thereto.
Optionally, as an embodiment of the present application, the determining that the first chip and the second chip attempt to be successfully interconnected at the ith time includes: and the first chip determines that the ith attempted interconnection between the first chip and the second chip is successful according to the attempted interconnection success confirmation message sent by the second chip.
Optionally, as an embodiment of the present application, the first chip is one of the following chips: FPGA chip, CPLD chip; or, the second chip is one of the following chips: FPGA chip, CPLD chip.
Therefore, the embodiment of the application provides a method for improving the successful interconnection of the high-speed interconnection interfaces on the premise of not changing the original hardware design aiming at the current situation that the interconnection of the high-speed interconnection interfaces is easy to fail, a closed loop is formed among the high-speed interconnection interfaces of the chips, the success rate and the reliability of the interconnection of the high-speed interconnection interfaces are improved, the manual participation is reduced, the debugging process is accelerated, and the research and development period of the chips is greatly shortened.
FIG. 2 is a block diagram of a chip interconnect according to one embodiment of the present application. As shown in fig. 2, the first chip includes:
the training module is used for training a training sequence;
the data selection module is used for selecting user data and training data;
and the design module is used for carrying out user design.
The high-speed interface also comprises a sending module and a receiving module, wherein the sending module is used for sending the training sequence; wherein the receiving module is used for receiving the training sequence.
The second chip includes:
the training module is used for training a training sequence;
the data selection module is used for selecting user data and training data;
and the design module is used for carrying out user design.
The high-speed interface also comprises a sending module and a receiving module, wherein the sending module is used for sending the training sequence; wherein the receiving module is used for receiving the training sequence.
Fig. 3 is a flow chart of an embodiment of the present application, and as shown in fig. 3, the method includes:
If the high-speed interconnect interface attempts to interconnect successfully (corresponding to step 302), when the number of successful attempts to interconnect satisfies the threshold number N, step 305 is executed, and the data selection module selects to send the data of the design module.
That is, even if the high-speed interconnection interface between the first chip and the second chip is not successfully interconnected, the receiving module receives the training sequence 0,1,2,3 (the training sequence may be structured arbitrarily, and the present invention takes 0,1,2,3 as an example for description), which indicates that the high-speed interconnection interface is successfully interconnected, and prepares to send the design module data.
Therefore, the embodiment of the application provides a method for improving the successful interconnection of the high-speed interconnection interfaces on the premise of not changing the original hardware design aiming at the current situation that the interconnection of the high-speed interconnection interfaces is easy to fail, a closed loop is formed among the high-speed interconnection interfaces of the chips, the success rate and the reliability of the interconnection of the high-speed interconnection interfaces are improved, the manual participation is reduced, the debugging process is accelerated, and the chip research and development period is greatly shortened.
Fig. 4 is a schematic block diagram of a first chip of the present application. The first chip 400 includes:
and the processing unit 410 is configured to determine that the ith attempt to interconnect the high-speed interfaces of the first chip and the second chip is successful.
A determining unit 420, configured to determine that the interconnection between the first chip and the second chip is successful when the number of times of successful interconnection attempts of the high-speed interfaces of the first chip and the second chip reaches a threshold number of times N, where i is a positive integer less than or equal to N, and N is a positive integer.
Optionally, the processing unit 410 is specifically configured to send a first training sequence set to the second chip; and after the second chip receives the first training set, the first chip receives a second training sequence set sent by the second chip, and the first training set is a proper subset of the second training set.
Optionally, the processing unit 410 is configured to send a first training sequence set to the second chip; when the first chip does not receive the second chip sending a second training sequence set, the first chip sends the first training set to the second chip again, wherein the first training set is combined into a proper subset of the second training set.
Optionally, the processing unit 410 is configured to determine that the ith interconnection attempt between the first chip and the second chip is successful according to an interconnection attempt success confirmation message sent by the second chip.
Optionally, the processing unit 410 is configured to send a second set of training sequences to the second chip when the first chip receives the first set of training sequences sent by the second chip.
The same and similar parts in the various embodiments in this specification may be referred to each other. Especially, for the terminal embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant points can be referred to the description in the method embodiment.
The above-described embodiments of the present application do not limit the scope of the present application.
Fig. 5 is a schematic structural diagram of a controlled terminal according to an embodiment of the present invention, and as shown in fig. 5, the controlled terminal 500 may include: a processor 510, a memory 520, and a communication unit 530. The components communicate via one or more buses, and those skilled in the art will appreciate that the architecture of the servers shown in the figures is not limiting of the application, and may be a bus architecture, a star architecture, a combination of more or fewer components than those shown, or a different arrangement of components.
The controlled terminal shown in fig. 5 can implement the method shown in the embodiments of fig. 1 to fig. 3, and for brevity, the description is omitted here.
The communication unit 530 is configured to establish a communication channel so that the storage device can communicate with other devices. And receiving user data sent by other equipment or sending the user data to other equipment.
The processor 510, which is a control center of the storage device, connects various parts of the entire electronic device using various interfaces and lines, and performs various functions of the electronic device and/or processes data by operating or executing software programs and/or modules stored in the memory 520 and calling data stored in the memory. The processor may be composed of an Integrated Circuit (IC), for example, a single packaged IC, or a plurality of packaged ICs connected with the same or different functions. For example, processor 510 may include only a Central Processing Unit (CPU). In the embodiments of the present application, the CPU may be a single arithmetic core or may include multiple arithmetic cores.
The memory 520 may be implemented by any type of volatile or non-volatile storage device or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk.
The executable instructions in memory 520, when executed by processor 510, enable terminal 500 to perform some or all of the steps in the method embodiments described below.
In specific implementation, the present application further provides a computer storage medium, where the computer storage medium may store a program, and the program may include some or all of the steps in the embodiments provided in the present application when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a Random Access Memory (RAM).
Those skilled in the art will clearly understand that the techniques in the embodiments of the present application may be implemented by way of software plus a required general hardware platform. Based on such understanding, the technical solutions in the embodiments of the present application may be essentially implemented or a part contributing to the prior art may be embodied in the form of a software product, which may be stored in a storage medium, such as a ROM/RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the embodiments or some parts of the embodiments of the present application.
The same and similar parts in the various embodiments in this specification may be referred to each other. Especially, for the terminal embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant points can be referred to the description in the method embodiment.
The above-described embodiments of the present application do not limit the scope of the present application.
Claims (6)
1. A method for verifying successful interconnection of chip interfaces is characterized by comprising the following steps:
determining that the ith attempt of interconnection of the high-speed interfaces of the first chip and the second chip is successful;
when the number of times of successful interconnection attempts of the high-speed interfaces of the first chip and the second chip reaches a threshold number N, determining that the first chip and the second chip are successfully interconnected, wherein i is a positive integer smaller than or equal to N, and N is a positive integer;
the determining that the first chip and the second chip are successfully interconnected in the ith attempt includes:
the first chip sends a first training sequence set to the second chip;
after the second chip receives the first training sequence set, the second chip sends a second training sequence set to the first chip, the first chip receives the second training sequence set sent by the second chip, and the first training sequence set is a proper subset of the second training sequence set;
when the second chip does not successfully receive the first training sequence set or when the first chip does not receive the second training sequence set sent by the second chip, the first chip sends the first training sequence set to the second chip again.
2. The method of claim 1, wherein the determining that the first chip and the second chip successfully interconnected in the ith attempt comprises:
and the first chip determines that the ith attempted interconnection between the first chip and the second chip is successful according to the attempted interconnection success confirmation message sent by the second chip.
3. The method of claim 1 or 2, wherein the first chip is one of the following: FPGA chip, CPLD chip;
or, the second chip is one of the following chips: FPGA chip, CPLD chip.
4. A first chip, comprising:
the processing unit is used for determining that the ith attempt of interconnection of the high-speed interfaces of the first chip and the second chip is successful;
the determining unit determines that the interconnection between the first chip and the second chip is successful when the number of times of successful interconnection attempts of the high-speed interfaces of the first chip and the second chip reaches a threshold number of times N, wherein i is a positive integer smaller than or equal to N, and N is a positive integer;
the processing unit is specifically configured to:
sending a first training sequence set to the second chip;
after the second chip receives the first training sequence set, the processing unit is further configured to receive a second training sequence set sent by the second chip, where the first training sequence set is a proper subset of the second training sequence set;
when the second chip does not successfully receive the first training sequence set or when the processing unit does not receive the second chip and sends the second training sequence set, the processing unit sends the first training sequence set to the second chip again.
5. The first chip of claim 4, wherein the processing unit is specifically configured to:
and determining that the ith attempted interconnection between the first chip and the second chip is successful according to the attempted interconnection success confirmation message sent by the second chip.
6. The first chip according to claim 4 or 5, wherein the first chip is one of the following chips: FPGA chip, CPLD chip;
or, the second chip is one of the following chips: FPGA chip, CPLD chip.
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| CN1447570A (en) * | 2002-03-26 | 2003-10-08 | 华为技术有限公司 | Network access faciity based on protocol 802.1X and method for realizing handshake at client end |
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