CN107591339B - Test structure and test method - Google Patents
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- CN107591339B CN107591339B CN201610531759.1A CN201610531759A CN107591339B CN 107591339 B CN107591339 B CN 107591339B CN 201610531759 A CN201610531759 A CN 201610531759A CN 107591339 B CN107591339 B CN 107591339B
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Abstract
A kind of test structure and test method, test structure includes: substrate, and the substrate includes chip area；Laminated conductive structure in the substrate, the laminated conductive structure includes bottom conductive layer, interconnection layer structure and top layer conductive layer from the bottom to top, wherein, the bottom conductive layer, interconnection layer structure and top layer conductive layer are sequentially connected with the chain structure to be formed around the chip area；Several discrete test layers above the top layer conductive layer, each test layer correspondence is electrically connected with a top layer conductive layer, and several discrete test layers are around the chip area；Dielectric layer in the laminated conductive structure and on test layer side wall；Passivation layer at the top of the dielectric layer and at the top of test layer.The present invention improves the certainty of positioning chip layered position, to improve successfully tested rate.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, in particular to a kind of test structure and test method.
Background technique
Wafer is cut into several chips (chip or die) after carrying out, by wafer, this is that integrated circuit produced
One of vital link in journey.But chip easily occurs being layered in subsequent cutting process and seminess, cutting are drawn
Then the layering risen extends to intermediate chip usually at chip edge, seriously threatens the integrality of function element on chip
And yield rate.
In order to avoid or reduce chip lamination problem, protection ring usually is set in the external zones of chip, the protection ring is used
Come not damaged when protecting chip cutting.In the prior art, the protection ring of chip periphery is around entire chip, the protection ring packet
Include the first protection ring and the second protection ring around first protection ring, wherein the first protection ring is SR (Seal Ring)
Structure, the second protection ring is CAS (Crack Stop Structure) structure, in general, second protection ring is positioned at described
The periphery of first protection ring.
Chip is protected in spite of two layers of protection ring, but still has crackle in encapsulation process across protection ring
Into chip, cause chip that layering (delamination) occurs, once being layered, last test will fail, therefore need
The position of chip layering is confirmed by various failure analysis means.In order to be monitored to manufacturing process, guarantee that technique can
By property, it is common practice to form test structure (test key), the test of some key parameters for chip in the chips
And simulation, to guarantee the quality of chip factory.
However, the prior art is big using the difficulty of test structural confirmation chip layered position, the general of chip failure point is found
Rate is to be improved.
Summary of the invention
Problems solved by the invention is to provide a kind of test structure and test method, improves successfully tested rate.
To solve the above problems, the present invention provides a kind of test structure, comprising: substrate, the substrate include chip area；
Laminated conductive structure in the substrate, the laminated conductive structure include bottom conductive layer, interconnection layer from the bottom to top
Structure and top layer conductive layer, wherein the bottom conductive layer, interconnection layer structure and top layer conductive layer are sequentially connected with to form ring
Around the chain structure of the chip area；Several discrete test layers above the top layer conductive layer, each test layer
Correspondence is electrically connected with a top layer conductive layer, and several discrete test layers are around the chip area；Positioned at the layer
Dielectric layer on folded conductive structure and on test layer side wall；Passivation at the top of the dielectric layer and at the top of test layer
Layer.
Optionally, the distance between adjacent described test layer is less than or equal to 10 μm.
Optionally, on being parallel to the test layer orientation, the width dimensions of the test layer are greater than or equal to 1 μ
m。
Optionally, bottom conductive layer is shared between the adjacent stacked structure.
Optionally, the quantity of the test layer is identical as the quantity of the top layer conductive layer.
Optionally, the chip area of the substrate has chip；The laminated conductive structural top is lower than the chip top
Portion；With the chip top flush or above the chip top at the top of the test layer.
Optionally, the chip area of the substrate has chip, and the chip includes: positioned at chip bottom segment thickness
It is layered district occurred frequently and the area layering Di Fa above the layering district occurred frequently；Wherein, the laminated conductive structural top with
It is flushed at the top of the layering district occurred frequently.
Optionally, the test structure further include: the first protection ring and the second protection ring in the substrate, and
The laminated conductive structure is between first protection ring and the second protection ring.
Optionally, the laminated conductive structural top is lower than the first protection ring top；Laminated conductive structure top
Portion is lower than the second protection ring top；At the top of the test layer and at the top of first protection ring and at the top of the second protection ring
It flushes.
Optionally, the test structure further include: conductive plunger, the conductive plunger are conductive for being electrically connected the bottom
Layer, interconnection layer structure and top layer conductive layer.
Optionally, the interconnection layer structure includes: the intermediate conductive layer that several layers stack, and will by the conductive plunger
The electrical connection of intermediate conductive layer described in adjacent layer.
Optionally, the test layer includes bottom test layer and the top layer test layer above bottom test layer, and
It is electrically connected between the top layer test layer and the bottom test layer by test plug.
Optionally, the substrate further includes around the Cutting Road region of the chip area, and the laminated conductive structure
Positioned at the Cutting Road region.
The present invention also provides a kind of test methods, comprising: provides test structure above-mentioned；The passivation layer is removed, until
Expose several discrete test layers；Electrical testing is carried out to the test layer, obtains and is produced in the laminated conductive structure
The region of raw open circuit；According to the region for generating open circuit in the laminated conductive structure, the position that chip area is layered is obtained.
Optionally, the method for obtaining the position that the chip area is layered includes: in the laminated conductive structure
The region for generating open circuit carries out physical verification analysis, positions the position that the laminated conductive structure is opened a way, the stacking is led
Electric structure generates the position that the corresponding layer in position of open circuit is layered for chip area.
Optionally, the electrical testing includes: and carries out voltage contrast to several discrete test layers to compare analysis, obtains
Obtain the corresponding voltage contrast of each test layer；When the corresponding voltage contrast brightness of each test layer has otherness, according to obtaining
The corresponding voltage contrast of each test layer taken, carries out FIB cross-section analysis to the lamination conductive structure, to obtain the layer
The region of open circuit is generated in folded conductive structure；When the corresponding voltage contrast brightness of each test layer is identical, to the test
Layer carries out open test.
Optionally, the electrical testing includes carrying out open test to the test layer, and the open test includes: by institute
It states several discrete test layers and is divided into multiple test groups, each test group includes first test layer, tail test layer and is located at head
Several test layers between test layer and tail test layer；First test layer and tail test layer to each test group carry out whole electrical
Test, judges whether the corresponding laminated conductive structure of the test group opens a way；When detect the test group it is corresponding stacking lead
When electric structure is not opened a way, first test layer and tail test layer to next test group carry out whole electrical testing；When judging the survey
When the corresponding laminated conductive structure of examination group is opened a way, the test group is carried out using dichotomy to limit electrical testing, until positioning
The region of open circuit is generated into the corresponding laminated conductive structure of the test group.
Optionally, the method for using dichotomy to carry out limiting electrical testing to the test group includes: the first test: with institute
The test layer for stating test group center is ground zero test layer, the ground zero test layer, first test layer and is located at new rise
Test layer between point test layer and first test layer constitutes the first new test group, to the ground zero test layer and first test layer into
Row entirety electrical testing, judges whether the corresponding laminated conductive structure of the described first new test group opens a way；Second test: with described
The test layer of test group center be ground zero test layer, the ground zero test layer, tail test layer and be located at ground zero
Test layer between test layer and tail test layer constitutes the second new test layer, carries out to the ground zero test layer and tail test layer
Whole electrical testing, judges whether the corresponding lamination conductive structure of the described second new test group opens a way；When the described first new test
When group corresponding laminated conductive structure open circuit, first test and the second test are carried out to the described first new test group, until
Navigate to the region that open circuit is generated in the corresponding laminated conductive structure of the described first new test group；When the described second new test group pair
When the laminated conductive structure open circuit answered, first test and the second test are carried out to the described second new test group, until positioning
The region of open circuit is generated into the corresponding laminated conductive structure of the described second new test group.
Optionally, the shape of the chip area is rectangular；Several discrete test layers are divided into 4 test groups.
Optionally, before removing the passivation layer, further includes: carry out routine test to the test structure, judge institute
Whether state in test structure has abnormal point；If noting abnormalities a little, physical verification analysis is carried out to the test structure, obtains layer
The region of open circuit is generated in folded conductive structure；If no abnormal, the passivation layer is removed, the test layer is carried out electrically
Test.
Compared with prior art, technical solution of the present invention has the advantage that
In the technical solution of test structure provided by the invention, the test structure is in addition to including laminated conductive structure, also
It is provided with the test layer being located in laminated conductive structure, and passivation layer is located at the top of the test layer；It is provided using the present invention
Test structure when being tested, test layer can be exposed for removal passivation layer, therefore required when exposure test layer go
The thickness removed is thin, enable removal passivation layer after test layer be uniformly exposed, so as to the test layer into
Row electrical testing.By the electrical property tested between different test layers, you can learn that being located at the laminated conductive knot below test layer
Whether open circuit is led to the problem of in structure；Also, since test layer is easily exposed, by testing between different test layers
Electrical property also easily knows the region that corresponding laminated conductive structure is opened a way between which two test layer, thus accurately fixed
Position goes out the corresponding position being layered of chip area, improves the accuracy that failure analysis is carried out to chip.
In optinal plan, the distance between adjacent described test layer be less than or equal to 10 μm, thus avoid to test layer into
The unnecessary interference problem being subject to when row electrical testing, improves the accuracy of test.
In the technical solution of test method provided by the invention, the test layer is easy uniformly to be exposed, thus
Electrical testing can be carried out to several discrete test layers, to obtain the region for generating open circuit in laminated conductive structure；
According to the region for generating open circuit in the laminated conductive structure, the position that chip area is layered is obtained, so that finding chip
The accuracy rate that layered position occurs for region is significantly improved.
In optinal plan, the test group is carried out using dichotomy to limit electrical testing, can shorten and get stacking
Time needed for generating the region of open circuit in conductive structure improves testing efficiency.
Detailed description of the invention
It includes the semiconductor structure the schematic diagram of the section structure for testing structure that Fig. 1 and Fig. 2, which is a kind of,；
Fig. 3 to Fig. 5 is the structural schematic diagram for the test structure that one embodiment of the invention provides；
Fig. 6 and Fig. 7 is using schematic diagram when testing the present embodiment provides test method test structure；
Fig. 8 is the local overlooking schematic diagram in test method provided in this embodiment including a test group.
Specific embodiment
It can be seen from background technology that the prior art confirms that the difficulty of chip layered position is big, finds the accurate of chip failure point
Rate is to be improved.When being electrically able to confirm that chip failure, it is difficult to the analysis in physical property is carried out to chip, to obtain chip mistake
Specific location is imitated, that is, is difficult to navigate to the specific location that chip is layered.
Through analyzing, it includes the semiconductor structure the schematic diagram of the section structure for testing structure that Fig. 1 and Fig. 2, which are a kind of,.Wherein, scheme
1 is the cross-sectional view cut along chip cutting road region, and Fig. 2 is that the cross-section structure cut perpendicular to chip cutting road region is illustrated
Figure, the semiconductor structure includes: substrate 101, and the substrate 101 includes chip area and the side around the chip area
Edge region (edge area)；There is chip 102 on 101 chip area of substrate；It is formed on 101 fringe region of substrate
There is laminated conductive structure 103, the laminated conductive structure 103 includes the metal layer of multiple-level stack, wherein laminated conductive structure
103 include top top layer metallic layers 30 and the bottom bottom metal layer 10, further include be located at top layer metallic layer 30 with
Intermediate metal layer 20 between bottom metal layer 10, adjacent layer metal layer are electrically connected by conductive plunger 11, the discrete top
Layer metal layer 30 is around the chip area.
Whether opened a way by the metal layer tested in the laminated conductive structure 103, obtains and whether sent out in the chip 102
Raw lamination problem.
However, whether being opened using the semiconductor structure of above-mentioned offer by the metal layer in the laminated conductive structure 103
Whether road is layered in available chip, i.e., the presence of lamination problem electrically can be confirmed, it can be difficult to from physical property
On lamination problem is analyzed, be mainly reflected in be difficult to obtain and occur the position being layered in chip.
Found through analysis, due in chip lamination problem often have chip 102 have first thickness bottom section (not
Mark) in, for this purpose, the laminated conductive that setting overhead height is consistent with the bottom section overhead height of first thickness or difference is less
Structure 103, it can by laminated conductive structure 103 from being confirmed in chip 102 in electrical property whether with lamination problem.
The first thickness is small more compared with the integral thickness of chip, thus cause 103 top of laminated conductive structure with
The distance between 102 top of chip differs greatly.In order to find out 102 layered position of chip, need to carry out chip 102 to grind straight
30 surface of top layer metallic layer of laminated conductive structure 103 is removed to exposure.However, due to 102 top of chip and top layer metallic layer 30
The distance between it is big, therefore the thickness for grinding removal is thick, and the uncontrollable factor for grinding the thicker technique of thickness of removal is more；And layer
For folded conductive structure 103 around the chip 102, the thickness for grinding removal is thicker, is more difficult to ensure laminated conductive after grinding
All discrete top layer metallic layers 30 in structure 103 are uniformly exposed, it is possible to cause the top layer gold of some regions
Belong to layer 30 by complete grinding removal, it is also possible to which the top layer metallic layer 30 for other regions occur does not expose also, so as to cause difficulty
To be positioned by laminated conductive structure 103 to 102 layered position of chip.
To solve the above problems, the present invention provides a kind of test structure, Fig. 3 to Fig. 5 is what one embodiment of the invention provided
Test the structural schematic diagram of structure.Wherein, Fig. 3 is top view, and Fig. 4 is the cross-sectional view in Fig. 3 along the direction AA1, in Fig. 5 bitmap 3
The schematic diagram of the section structure along the direction BB1, it should be noted that for the ease of illustration and illustrate, be not shown in Fig. 3 and completely bow
Depending on structural schematic diagram.
The test structure includes:
Substrate 200, the substrate 200 include chip area I；
Laminated conductive structure in the substrate 200, the laminated conductive structure include that bottom from the bottom to top is led
Electric layer 210, interconnection layer structure and top layer conductive layer 230, wherein the bottom conductive layer 210, interconnection layer structure and top
Layer conductive layer 230 is sequentially connected with cyclization around the chain structure of the chip area I；
Several discrete test layers above the top layer conductive layer 230, each test layer it is corresponding and at least one
Top layer conductive layer 230 is electrically connected, and several discrete test layers are around the chip area I；
Dielectric layer 204 in the laminated conductive structure and on test layer side wall；
Passivation layer 205 at the top of 204 top of dielectric layer and test layer.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
The substrate 200 is silicon base, germanium substrate, SiGe substrate, silicon carbide substrate, GaAs substrate or gallium indium base
Bottom, the substrate 200 can also be the silicon base on insulator.In order to improve semiconductor structure performance, 200 surface of substrate
Several one functional layers can also be formed with, such as form interfacial TCO layer on 200 surface of substrate.
The substrate 200 includes chip area I, in the present embodiment, by taking the shape of the chip area I is rectangular as an example,
In other embodiments, the shape of the chip area can also be round, ellipse or other irregular shapes.The chip
The substrate 200 further includes the Cutting Road region II around the chip area I, and the chip area I is effective
Region, the Cutting Road region II is can be by the region of cutting removal after completing detection, ineffectiveness analysis to chip.This implementation
In example, in order to save space, laminated conductive structure is avoided to occupy chip position, the laminated conductive structure is located at Cutting Road region
On II.In other embodiments, the laminated conductive structure can also be set on chip area.
The chip area I of the substrate 200 has chip 201, and the chip 201 includes: positioned at 201 bottom of chip
The layering district occurred frequently H of the segment thickness and layering Di Fa area L above the layering district occurred frequently H.
It should be noted that layering district occurred frequently H herein is that the two compares with the "high" in the layering area Di Fa L with " low "
For, the chip 201 of the layering district occurred frequently H is easy to happen lamination problem, and the chip 201 of the layering area the Di Fa L is opposite
Lamination problem is less likely to occur.
The thickness of the layering district occurred frequently H is less than or equal to the thickness of the layering area the Di Fa L.In general, the chip
Thickness of 201 integral thickness much larger than the layering district occurred frequently H.For example, the integral thickness of the chip 201 is the layering
1.5 times of the thickness of district occurred frequently H~500 times.
The laminated conductive structural top is lower than 201 top of chip.In the present embodiment, the laminated conductive knot is set
It is flushed at the top of structure at the top of the layering district occurred frequently H, the laminated conductive structure is enabled effectively to perceive layering district occurred frequently H
Chip 201 lamination problem.When the chip 201 for being layered district occurred frequently H is layered, laminated conductive structure can accordingly be caused to be sent out
Layer estranged makes laminated conductive structure generate open circuit.It is subsequent the laminated conductive structure to be described in detail.
The conductive layer of the bottom is bottom conductive layer 210 in the laminated conductive structure, is located at the laminated conductive
The conductive layer of top is top layer conductive layer 230 in structure, and the conductive layer between the bottom and top is interconnection
Layer structure, the interconnection layer structure include: the intermediate conductive layer 220 that several layers stack, and the number of plies of the intermediate conductive layer 220 is big
In equal to 1.
The number of plies that whether can be layered detected is needed in the number of plies of conductive layer and chip 201 in the laminated conductive structure
It is related.In one embodiment, whether sending out for detection needed in the number of plies of conductive layer and chip 201 in the laminated conductive structure
The number of plies of layer estranged is identical.In another embodiment, in the laminated conductive structure conductive layer the number of plies be greater than chip 201 in need
The number of plies that whether can be layered of detection.
The quantity of the bottom conductive layer 210 of same layer is according to width dimensions, the laminated conductive of the bottom conductive layer 210
The gradient of the number of plies of structure, chip area I perimeter and chain structure is determined.In the present embodiment, the top layer conductive
The quantity of layer 230 is identical as the quantity of the bottom conductive layer 210；The quantity of the intermediate conductive layer 220 of same layer is described
2 times of the quantity of bottom conductive layer 210.
The bottom conductive layer 210, interconnection layer structure and top layer conductive layer 230 are sequentially connected with to be formed around the chip
The chain structure (stack chain) of region I, when lamination problem does not occur for chip 201, the chain structure is to be closed back
Road；When the chip 201 is layered, it will the chain structure is caused to be opened a way.
The chain structure includes the several groups stacked structure being sequentially electrically connected, and each group of stacked structure includes: at least one
A bottom conductive layer 210, at least one top layer conductive layer 230 and it is located at the bottom conductive layer 210 and top layer conductive layer
Interconnection layer structure between 230.Adjacent stacked structure shares the bottom conductive layer 230.
In the present embodiment, with each group of stacked structure include: two bottom conductive layers, 210, top layer conductive layers 230,
For interconnection layer structure between top layer conductive layer 230 and bottom conductive layer 210, top is shared between adjacent stacked structure
Layer conductive layer 230, makes the stacked structure be sequentially connected with to form chain structure by bottom conductive layer 210.In other embodiments
In, in the present embodiment, along the II extending direction of Cutting Road region, the section shape of each group of stacked structure is triangle, phase
It answers, the chain structure is in triangular wave waveform.
In other embodiments, along the extending direction of Cutting Road region, the section shape of each group of stacked structure may be used also
Think it is rectangular, correspondingly, the chain structure be in rectangular waveform.
In addition, the chain structure is closed annular in the present embodiment, the laminated conductive structure can comprehensively be felt
Know the lamination problem generated in chip 201, layered position is occurred using the test structure positioning chip area I to improve
Accuracy rate.
In the present embodiment, in order to be protected to chip 201, the test structure further include: be located in the substrate 201
The first protection ring 202 and the second protection ring 203, and the laminated conductive structure is located at first protection ring 202 and
Between two protection rings 203.
First protection ring 202 is around the chip area I and is located on the II of Cutting Road region, second protection ring
203 around the chip area I and on the II of Cutting Road region.
In the present embodiment, first protection ring 202 is located between chip area I and the second protection ring 203, and described first
Protection ring 202 is SR structure, and second protection ring is CAS structure.In other embodiments, can be with the first protection ring
CAS structure, the second protection ring are SR structure.
In the present embodiment, first protection ring, 202 top with flushed at the top of chip 201, the top of the second protection ring 203
It is flushed at the top of portion and the chip 201.In other embodiments, it can be above the chip top at the top of first protection ring
Portion, the second protection ring top can be above at the top of chip.
Correspondingly, the laminated conductive structural top is lower than 202 top of the first protection ring, i.e., the described top layer conductive layer
230 tops are lower than 202 top of the first protection ring；The laminated conductive structural top is pushed up lower than second protection ring 203
Portion, i.e., lower than 203 top of the second protection ring at the top of the described top layer conductive layer 230.
The test structure further include: conductive plunger 211, the conductive plunger 211 are conductive for being electrically connected the bottom
Layer 210, interconnection layer structure and top layer guided missile layer 230；In the present embodiment, also pass through the conductive plunger 211 for adjacent layer
Intermediate conductive layer 220 is electrically connected.
The test layer is located at 230 top of top layer conductive layer, each test layer correspondence and a top layer conductive layer 230
Electrical connection, several discrete test layers are around the chip area I.
At the top of the test layer with flushed at the top of the chip 102.In the present embodiment, the test layer top and the core
It is flushed at the top of piece 102；It is also neat with 202 top of the first protection ring and 203 top of the second protection ring at the top of the test layer
It is flat.In other embodiments, it can be above at the top of the chip at the top of the test layer.
The thickness of the test layer is greater than the laminated conductive structure integral thickness.In one embodiment, the test layer
1~10 times with a thickness of the laminated conductive structure；In another embodiment, the thickness of the test layer can also be
Even hundreds times of the decades of times of the laminated conductive structure integral thickness.In addition, needing to remove when testing test structure
Passivation layer 205, to guarantee that influence of the technical process of the removal passivation layer 205 to test layer is small, the thickness of the test layer
It is thicker.In one embodiment, the thickness of the test layer is more than or equal to 200 μm.
If the distance between adjacent test layer l is excessive, unnecessary interference can be introduced when carrying out failure analysis.
In order to guarantee the distance between adjacent test layer l using be suitble to failure analysis as criterion, in the present embodiment, the adjacent test layer it
Between distance l be less than or equal to 10 μm.
On being parallel to the test layer orientation, the width dimensions w of the test layer is greater than or equal to 1 μm, so that
It is carried out in test process to test structure, test layer is easy to be exposed after removal passivation layer 205；Also, the survey
The width dimensions for trying layer are larger, are conducive to improve the accuracy that test process middle probe is electrically connected with test layer.
In the present embodiment, the test layer includes: bottom test layer 240 and the top above bottom test layer 240
Layer test layer 250, and be electrically connected between the top layer test layer 250 and the bottom test layer 240 by test plug 251.
The test structure further include: the attachment plug 241 between the bottom test layer 240 and top layer conductive layer 230, it is described
Attachment plug 241 is electrically connected the top layer conductive layer 230 with the bottom test layer 240.
Wherein, the distance between adjacent described top layer test layer 250 l is less than or equal to 10 μm；It is being parallel to the top layer
In 250 orientation of test layer, the 250 width dimensions w of top layer test layer is greater than or equal to 1 μm；The top layer test layer 250
Thickness be greater than or equal to 200 μm.
It should be noted that in other embodiments, the test layer can also be including the test of two layers or more of stacking
Layer, and adjacent layer test layer is electrically connected by attachment plug；The test layer may be the test layer of single layer.
The test structure further include: the dielectric layer 204 in the laminated conductive structure and on test layer side wall,
The dielectric layer 204 is also located on 201 side wall of chip.The material of the dielectric layer 204 includes silica, silicon nitride or nitrogen
Silica.
The test structure further include: the passivation layer at the top of 204 top of dielectric layer and test layer
(passivation layer) 205, the passivation layer 205 provide protective effect to chip 201, avoid chip 201 from being exposed to outer
In boundary's environment, and the passivation layer 205 also provides protective effect to the test layer.The material of the passivation layer 205 is oxidation
Silicon, silicon nitride, p-doped silica, boron-doping silica or p-doped and boron silica.
In test structure provided in this embodiment, in addition to including laminated conductive structure, it is additionally provided with positioned at laminated conductive knot
Test layer on structure, and passivation layer is located at the top of the test layer；Therefore it is carried out using test structure provided in this embodiment
When test, test layer can be exposed for removal passivation layer, by the electrical property tested between different test layers, can obtain
Know in underlying laminated conductive structure and whether leads to the problem of open circuit；Also, since test layer is easily exposed, lead to
The electrical property tested between different test layers is crossed, also easily knows corresponding laminated conductive structure is opened between which two test layer
It improves and failure analysis is carried out to chip to accurately orient the corresponding position being layered of chip area in the region on road
Accuracy.
In addition, the test layer being arranged in the present embodiment is located at the top of the laminated conductive structure, therefore the test layer
The layout of the testing cushion (test pad) of vacant chip.
Correspondingly, the present invention also provides a kind of test methods, comprising: provide test structure above-mentioned；Remove the passivation
Layer, until exposing several discrete test layers；Electrical testing is carried out to the test layer, obtains the laminated conductive knot
The region of open circuit is generated in structure；According to the region for generating open circuit in the laminated conductive structure, obtains chip area and be layered
Position.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
With reference to Fig. 4 and Fig. 5, in the present embodiment, in order to reduce difficulty of test and complexity, the passivation layer is being removed
Before 205, routine test is carried out to the test structure, judges whether there is abnormal point in the test structure.
The routine test includes: to detect at optical microscopy (OM) to the test structure, aobvious by optics
Micro mirror judges whether there is lamination problem in the test structure；201 bottom surface of substrate of the test structure is thrown
Light processing carries out bottom laser scanning to the test structure after a polishing process, by described in laser scanning judgement
Whether test in structure has lamination problem.
If being abnormal a little, physical verification analysis (PFA, Physical Failure is carried out to the test structure
Analysis), the region that open circuit is generated in laminated conductive structure, and then the position being layered in positioning chip 201 are obtained；If
No exceptions point removes the passivation layer 205, carries out electrical testing to the test layer.
It should be noted that in other embodiments of the present invention, aforementioned routine test can also be saved, directly to the survey
The test layer for trying structure carries out electrical testing, obtains the region that open circuit is generated in the laminated conductive structure.
The electrical testing is described in detail below with reference to attached drawing.Fig. 6 and Fig. 7 is using the present embodiment provides surveys
Schematic diagram when method for testing tests test structure.
With reference to Fig. 6 and Fig. 7, the passivation layer 205 (with reference to Fig. 4 and Fig. 5) is removed, until exposing described several discrete
Test layer.
In the present embodiment, the passivation layer 205 is removed until exposing several discrete top layer test layers 250.
Using the method for physical etchings, etching removes the passivation layer 205.It is described blunt using the method removal of physical etchings
Change layer 205, is conducive to improve the flatness for testing structure after passivation layer 205 is removed.
In the present embodiment, since 205 bottom surface of passivation layer is in contact with test layer, etching removal passivation layer
Test layer can be exposed after 205, top layer conductive caused by the thickness of etching needed for avoiding or grinding removal is blocked up
Layer is difficult to the problem of being uniformly exposed.
In addition, the thickness of the test layer is thicker in the present embodiment, therefore even if physical etchings can carry out one to test layer
Determine the etching of degree, also still ensures that test layer all after etching removes passivation layer 205 is remained to for electrical testing.
For not in laminated conductive structure formed test layer test structure, to by top layer conductive layer be exposed with
Carry out electrical testing, then in addition to remove passivation layer, it is also necessary to removal be layered the area Di Fa chip, cause top layer conductive layer be difficult to by
Uniformly it is exposed, therefore, it is difficult to carry out electrical testing to top layer conductive layer.
After several discrete test layers are exposed, electrical testing is carried out to the test layer, described in acquisition
The region of open circuit is generated in stepped construction.In the present embodiment, electrical testing is carried out to the top layer test layer 250, described in acquisition
The region of open circuit is generated in stepped construction.
Simplify testing procedure to further decrease difficulty of test, in the present embodiment, the electrical testing includes: to described
Several discrete test layers carry out voltage contrast comparison (VC) analysis, obtain the corresponding voltage contrast of each test layer；When described each
It is right according to the corresponding voltage contrast of each test layer obtained when the corresponding voltage contrast brightness of test layer has otherness
The lamination conductive structure carries out FIB (Focused Ion Beam) cross-section analysis, is produced with obtaining in the laminated conductive structure
The region of raw open circuit.
Specifically, carrying out voltage contrast to several discrete top layer test layers 250 compares analysis, when a certain top layer is surveyed
When opening a way in the examination corresponding laminated conductive structure of layer 250, the corresponding voltage contrast of the top layer test layer 250 will be than other
The corresponding voltage contrast of top layer test layer 250 is dark.The top layer test layer 250 corresponding laminated conductive knot dark to the voltage contrast
Structure region carries out FIB cross-section analysis, obtains the region that open circuit is generated in the laminated conductive structure.
When the corresponding voltage contrast brightness of each test layer is identical, open test is carried out to the test layer.It needs
Illustrate, in other embodiments, may be omitted with voltage contrast above-mentioned and compare analysis, directly the test layer is carried out
Open test.Open-circuit test is described in detail below.
The electrical testing includes carrying out open test to the test layer, and the open test includes: will be described several
A discrete test layer is divided into multiple test groups, and each test group is including first test layer, tail test layer and is located at first test layer
Several test layers between tail test layer；First test layer and tail test layer to each test group carry out whole electrical testing,
Judge whether the corresponding laminated conductive structure of the test group opens a way；When detecting the corresponding laminated conductive structure of the test group
When not opening a way, first test layer and tail test layer to next test group carry out whole electrical testing；When judging the test group pair
When the laminated conductive structure open circuit answered, the test group is carried out using dichotomy to limit electrical testing, until navigating to described
The region of open circuit is generated in the corresponding laminated conductive structure of test group.Wherein, first top layer test in each test group
Layer 250 is used as first test layer, the last one top layer test layer 250 in each test group is used as tail test layer, needs to illustrate
, in contrast the determination of the head test layer and tail test layer is.
In the present embodiment, the shape of the chip area I is rectangular；Several discrete test layers are divided into accordingly
4 test groups.An and side of each test group closely rectangular chip area I.
With reference to Fig. 8, Fig. 8 is the local overlooking signal including a test group in the test method provided in the present embodiment
Figure, tests the top layer test layer 250, and provides electricity to two test layers to be tested using probe (probe) 500
Pressure or electric current, to complete the whole electrical testing to the test group and limit electrical testing.Specifically, using probe
500 provide voltage or electric current to two top layer conductive layers 250 to be tested.
In Fig. 8, by taking the test group includes 5 top layer test layers 250 as an example, the method for the entirety electrical testing are as follows:
A probe 500 is provided to be electrically connected with first top layer test layer 250；Another probe is provided to be electrically connected with tail top layer test layer 250；Using
The probe 500 provides voltage or electric current to described two top layer test layers 250, to complete to the whole electrical of the test group
Test, judges whether the corresponding laminated conductive structure of the test group opens a way.
In the present embodiment, include: using the method that dichotomy carries out limiting electrical testing to the test group
First test: using the test layer of the test group center as ground zero test layer, the ground zero test layer,
First test layer and the test layer between ground zero test layer and first test layer constitute the first new test group, to described new
Point test layer and first test layer carry out whole electrical testing, whether judge the corresponding laminated conductive structure of the described first new test group
Open circuit；
The top layer test layer 250 of described first new test group is tested, using probe to the described first new test group
Top layer test layer 250 voltage or electric current are provided, to complete the whole electrical testing of the described first new test group.
Specifically, by taking each test group includes 5 top layer conductive layers 250 as an example, then the 3rd top layer is led with reference to Fig. 8
Electric layer 250 is ground zero test layer, first top layer conductive layer, 250, second top layer conductive layer 250 and third top
Layer conductive layer 250 constitutes the first new test group.
It should be noted that the quantity of the top layer test layer 250 of each test group is N, the ground zero test layer is n-th
A top layer test layer 250；When N is even number, n is (N/2)+1 or (N/2) -1；When N is odd number, n rounds up for N/2.
Second test: using the test layer of the test group center as ground zero test layer, the ground zero test layer,
Tail test layer and the test layer between ground zero test layer and tail test layer constitute the second new test layer, to described new
Point test layer and tail test layer carry out whole electrical testing, whether judge the corresponding lamination conductive structure of the described second new test group
Open circuit；
The top layer test layer 250 of described second new test group is tested, using probe to the described second new test group
Top layer test layer 250 voltage or electric current are provided, to complete the whole electrical testing of the described second new test group.Specifically
, with reference to Fig. 8, by taking each test group includes 5 top layer conductive layers 250 as an example, then the 3rd top layer conductive layer 250 is new
Starting point test layer, 250, the 4th top layer test layers 250 of the third top layer test layer and the 5th top layer test layer 250
Constitute the second new test layer.
It should be noted that the quantity of the top layer test layer 250 of each test group is N, the ground zero test layer is n-th
A top layer test layer 250；When N is even number, n is (N/2)+1 or (N/2) -1；When N is odd number, n rounds up for N/2.
In addition, in the second test that and then first test carries out, the ground zero test layer of selection and the first test
The ground zero test layer of middle selection is answered identical.
When the corresponding laminated conductive structure open circuit of the described first new test group, the described first new test group is carried out described in
First test and the second test, until navigating to the area for generating open circuit in the corresponding laminated conductive structure of the described first new test group
Domain；
Specifically, the test layer of the described first new test group center is divided the described first new test group for boundary
For two sub- test groups, first test is carried out to one of them sub- test group, described second is carried out to another sub- test group
Test；Repeat first test and the second test, is led until navigating to corresponding be laminated of the described first new test group
The region of open circuit is generated in electric structure.
When the corresponding laminated conductive structure open circuit of the described second new test group, the described second new test group is carried out described in
First test and the second test, until navigating to the area for generating open circuit in the corresponding laminated conductive structure of the described second new test group
Domain.
Specifically, by the described second new test group center place test layer be that boundary will the described second new test group stroke
It is divided into two sub- test groups, first test is carried out to one of them sub- test group, described the is carried out to another sub- test group
Two tests；Repeat first test and the second test, is led until navigating to corresponding be laminated of the described second new test group
The region of open circuit is generated in electric structure.
The test group is carried out using dichotomy to limit electrical testing, any two top layer conductive layers tested for choosing
The purpose of electric property between 250 is strong, obtains the electrical property between top layer conductive layer 250 using the method gradually approached
Can, the time needed for getting the region for generating open circuit in laminated conductive structure can be shortened, improve testing efficiency.
The method for obtaining the position that the chip area is layered includes: to generation open circuit in the laminated conductive structure
Region carry out physical verification analysis, position the position that the laminated conductive structure is opened a way, the laminated conductive structure production
The corresponding layer in position of raw open circuit is the position that chip area I is layered.
Test layer described in the present embodiment is easy uniformly to be exposed, so as to several discrete tests
Layer carries out electrical testing, to obtain the region for generating open circuit in laminated conductive structure；According to being produced in the laminated conductive structure
The region of raw open circuit obtains the position that chip area I is layered, so that finding the accuracy rate that layered position occurs for chip area
It is significantly improved, for example, compared with the test structure of test layer not formed on top layer conductive layer, test provided in this embodiment
The accuracy rate that layered position occurs for structure positioning chip area is promoted even higher to 70% by 0.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (19)
1. a kind of test structure of chip characterized by comprising
Substrate, the substrate include chip area, and the chip area of the substrate has chip, and the chip includes: positioned at core
The layering district occurred frequently of piece bottom part thickness and the area layering Di Fa above the layering district occurred frequently；
Laminated conductive structure in the substrate, the laminated conductive structure include bottom conductive layer from the bottom to top, mutually
Even layer structure and top layer conductive layer, wherein the bottom conductive layer, interconnection layer structure and top layer conductive layer are sequentially connected with shape
Around the chain structure of the chip area, the laminated conductive structural top and layering district occurred frequently top flush cyclization；
Discrete test layer above the top layer conductive layer, the discrete test layer correspondence are electrically connected with top layer conductive layer
It connects, and the discrete test layer is around the chip area；
Dielectric layer in the laminated conductive structure and on test layer side wall；
Passivation layer at the top of the dielectric layer and at the top of test layer.
2. test structure as described in claim 1, which is characterized in that the distance between adjacent described test layer is less than or equal to
10μm。
3. test structure as described in claim 1, which is characterized in that described on being parallel to the test layer orientation
The width dimensions of test layer are greater than or equal to 1 μm.
4. test structure as described in claim 1, which is characterized in that the chain structure is in triangular wave waveform or rectangular wave wave
Shape.
5. test structure as described in claim 1, which is characterized in that the chain structure includes that several groups are sequentially electrically connected
Stacked structure, each group of stacked structure include: at least one bottom conductive layer and at least one top layer conductive layer, further includes:
Interconnection layer structure between bottom conductive layer and top layer conductive layer.
6. test structure as claimed in claim 5, which is characterized in that it is conductive to share bottom between the adjacent stacked structure
Layer.
7. test structure as described in claim 1, which is characterized in that the test structure further include: be located in the substrate
The first protection ring and the second protection ring, and the laminated conductive structure be located at first protection ring and the second protection ring it
Between.
8. test structure as claimed in claim 7, which is characterized in that the laminated conductive structural top is protected lower than described first
At the top of retaining ring；The laminated conductive structural top is lower than the second protection ring top；The test layer top and described first
It is flushed at the top of protection ring and at the top of the second protection ring.
9. test structure as described in claim 1, which is characterized in that the test structure further include: conductive plunger, it is described to lead
Electric plug is for being electrically connected the bottom conductive layer, interconnection layer structure and top layer conductive layer.
10. test structure as claimed in claim 9, which is characterized in that the interconnection layer structure includes: during several layers stack
Between conductive layer, and intermediate conductive layer described in adjacent layer is electrically connected by the conductive plunger.
11. test structure as described in claim 1, which is characterized in that the test layer includes bottom test layer and is located at
Top layer test layer above bottom test layer, and pass through test plug electricity between the top layer test layer and the bottom test layer
Connection.
12. test structure as described in claim 1, which is characterized in that the substrate further includes around the chip area
Cutting Road region, and the laminated conductive structure is located at the Cutting Road region.
13. a kind of test method of chip characterized by comprising
Such as the described in any item test structures of claim 1 ~ 12 are provided；
The passivation layer is removed, until exposing several discrete test layers；
Electrical testing is carried out to several discrete test layers, obtains the region for generating open circuit in the laminated conductive structure；
According to the region for generating open circuit in the laminated conductive structure, the position that chip area is layered is obtained.
14. test method as claimed in claim 13, which is characterized in that obtain the position that the chip area is layered
Method includes: to carry out physical verification analysis to the region for generating open circuit in the laminated conductive structure, positions the laminated conductive
The position that structure is opened a way, the corresponding layer in position that the laminated conductive structure generates open circuit is what chip area was layered
Position.
15. test method as claimed in claim 13, which is characterized in that the electrical testing includes:
Voltage contrast is carried out to several discrete test layers and compares analysis, obtains the corresponding voltage contrast of each test layer；
It is corresponding according to each test layer obtained when the corresponding voltage contrast brightness of each test layer has otherness
Voltage contrast, carries out FIB cross-section analysis to the laminated conductive structure, and open circuit is generated in the laminated conductive structure to obtain
Region；
When the corresponding voltage contrast brightness of each test layer is identical, open test is carried out to the test layer.
16. test method as claimed in claim 13, which is characterized in that the electrical testing includes carrying out to the test layer
Open test, the open test include:
Several described discrete test layers are divided into multiple test groups, each test group include first test layer, tail test layer with
And several test layers between first test layer and tail test layer；
First test layer and tail test layer to each test group carry out whole electrical testing, judge the corresponding stacking of the test group
Whether conductive structure opens a way；
When detecting that the corresponding laminated conductive structure of the test group is not opened a way, the first test layer and tail of next test group are surveyed
It tries layer and carries out whole electrical testing；
When judging that the corresponding laminated conductive structure of the test group is opened a way, the test group is carried out using dichotomy to limit electricity
Property test, until navigate to the region for generating open circuit in the corresponding laminated conductive structure of the test group.
17. test method as claimed in claim 16, which is characterized in that carry out limiting electricity to the test group using dichotomy
Property test method include:
First test: using the test layer of the test group center as ground zero test layer, the ground zero test layer, first survey
It tries layer and the test layer between ground zero test layer and first test layer constitutes the first new test group, the ground zero is surveyed
It tries layer and first test layer carries out whole electrical testing, judge whether the corresponding laminated conductive structure of the described first new test group is opened
Road；
Second test: using the test layer of the test group center as ground zero test layer, the ground zero test layer, tail are surveyed
It tries layer and the test layer between ground zero test layer and tail test layer constitutes the second new test layer, the ground zero is surveyed
It tries layer and tail test layer and carries out whole electrical testing, judge whether the corresponding lamination conductive structure of the described second new test group is opened
Road；
When the corresponding laminated conductive structure open circuit of the described first new test group, described first is carried out to the described first new test group
Test and the second test, until navigating to the region for generating open circuit in the corresponding laminated conductive structure of the described first new test group；
When the corresponding laminated conductive structure open circuit of the described second new test group, described first is carried out to the described second new test group
Test and the second test, until navigating to the region for generating open circuit in the corresponding laminated conductive structure of the described second new test group.
18. test method as claimed in claim 16, which is characterized in that the shape of the chip area is rectangular；It will be described
Several discrete test layers are divided into 4 test groups.
19. test method as claimed in claim 13, which is characterized in that before removing the passivation layer, further includes: to institute
It states test structure and carries out routine test, judge whether there is abnormal point in the test structure；If noting abnormalities a little, to the survey
It tries structure and carries out physical verification analysis, obtain the region for generating open circuit in laminated conductive structure；If no abnormal, institute is removed
Passivation layer is stated, electrical testing is carried out to the test layer.
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