CN107591339A - Test structure and method of testing - Google Patents
Test structure and method of testing Download PDFInfo
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- CN107591339A CN107591339A CN201610531759.1A CN201610531759A CN107591339A CN 107591339 A CN107591339 A CN 107591339A CN 201610531759 A CN201610531759 A CN 201610531759A CN 107591339 A CN107591339 A CN 107591339A
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Abstract
A kind of test structure and method of testing, test structure include：Substrate, the substrate include chip area；Laminated conductive structure in the substrate, the laminated conductive structure includes bottom conductive layer, interconnection layer structure and top layer conductive layer from the bottom to top, wherein, the bottom conductive layer, interconnection layer structure and top layer conductive layer are sequentially connected with the chain structure to be formed around the chip area；Some discrete test layers above the top layer conductive layer, each test layer is corresponding to be electrically connected with a top layer conductive layer, and some discrete test layers are around the chip area；Dielectric layer in the laminated conductive structure and in test layer side wall；Passivation layer at the top of the dielectric layer and at the top of test layer.The present invention improves the certainty of positioning chip layered position, so as to improve successfully tested rate.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of test structure and method of testing.
Background technology
Wafer cuts into some chips (chip or die) after carrying out, by wafer, and this is integrated
One of vital link in circuit manufacturing process.But chip easily goes out in follow-up cutting process
Now layering and seminess, caused layering is cut generally at chip edge, is then prolonged to intermediate chip
Stretch, the integrality and yield rate of function element in serious threat to chip.
In order to avoid or reduce chip lamination problem, generally chip external zones set protection ring, it is described
It is without damage when protection ring is for protecting chip cutting.In the prior art, the protection ring of chip periphery is surround
Whole chip, the protection ring include the first protection ring and the second protection around first protection ring
Ring, wherein, the first protection ring is SR (Seal Ring) structure, and the second protection ring is CAS (Crack Stop
Structure) structure, in general, second protection ring are located at the periphery of first protection ring.
Chip is protected in spite of two layers of protection ring, but crackle is still had in encapsulation process and is worn
Overprotection ring enters chip, causes chip that layering (delamination) occurs, once it is layered, most
Test afterwards will be failed, it is therefore desirable to the position of chip layering is confirmed by various failure analysis means.
In order to be monitored to manufacturing process, ensure reliability of technology, it is common practice to formed survey in the chips
Structure (test key) is tried, for the test and simulation of some key parameters of chip, to ensure that chip goes out
The quality of factory.
However, prior art confirms that the difficulty of chip layered position is big using test structure, chip mistake is found
The probability of effect point has much room for improvement.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of test structure and method of testing, raising successfully tested rate.
To solve the above problems, the present invention provides a kind of test structure, including：Substrate, the substrate bag
Include chip area；Laminated conductive structure in the substrate, the laminated conductive structure are included under
Supreme bottom conductive layer, interconnection layer structure and top layer conductive layer, wherein, the bottom conductive layer,
Interconnection layer structure and top layer conductive layer are sequentially connected with the chain structure to be formed around the chip area；Position
Some discrete test layers above the top layer conductive layer, each test layer is corresponding to lead with a top layer
Electric layer electrically connects, and some discrete test layers are around the chip area；Led positioned at the stacking
Dielectric layer in electric structure and in test layer side wall；At the top of the dielectric layer and at the top of test layer
Passivation layer.
Optionally, the distance between adjacent described test layer is less than or equal to 10 μm.
Optionally, on parallel to the test layer orientation, the width dimensions of the test layer are more than
Or equal to 1 μm.
Optionally, bottom conductive layer is shared between the adjacent stacked structure.
Optionally, the quantity of the test layer is identical with the quantity of the top layer conductive layer.
Optionally, the chip area of the substrate has chip；The laminated conductive structural top is less than institute
State at the top of chip；With chip top flush or above at the top of the chip at the top of the test layer.
Optionally, the chip area of the substrate has chip, and the chip includes：Positioned at chip bottom
The layering district occurred frequently of segment thickness and the layering Di Fa areas above the layering district occurred frequently；Wherein,
The laminated conductive structural top at the top of the layering district occurred frequently with flushing.
Optionally, the test structure also includes：The first protection ring and second in the substrate
Protection ring, and the laminated conductive structure is between first protection ring and the second protection ring.
Optionally, the laminated conductive structural top is less than at the top of first protection ring；The stacking is led
Electric structural top is less than at the top of second protection ring；At the top of the test layer and the first protection ring top
Flushed at the top of portion and the second protection ring.
Optionally, the test structure also includes：Conductive plunger, the conductive plunger are used to electrically connect institute
State bottom conductive layer, interconnection layer structure and top layer conductive layer.
Optionally, the interconnection layer structure includes：If the intermediate conductive layer that dried layer stacks, and by described
Conductive plunger electrically connects intermediate conductive layer described in adjacent layer.
Optionally, the test layer includes bottom test layer and the top layer above bottom test layer is surveyed
Layer is tried, and is electrically connected between the top layer test layer and the bottom test layer by test plug.
Optionally, the substrate is also included around the Cutting Road region of the chip area, and the stacking
Conductive structure is located at the Cutting Road region.
The present invention also provides a kind of method of testing, including：Foregoing test structure is provided；Remove described blunt
Change layer, until exposing some discrete test layers；Electrical testing is carried out to the test layer, obtained
Take the region that open circuit is produced in the laminated conductive structure；Opened a way according to being produced in the laminated conductive structure
Region, obtain the position that is layered of chip area.
Optionally, obtaining the method for the position that the chip area is layered includes：The stacking is led
The region that open circuit is produced in electric structure carries out physical verification analysis, positions the laminated conductive structure and opens
The position on road, the layer that the laminated conductive structure produces the position correspondence of open circuit are layered for chip area
Position.
Optionally, the electrical testing includes：Voltage contrast ratio is carried out to some discrete test layers
To analysis, voltage contrast corresponding to each test layer is obtained；When voltage contrast corresponding to each test layer is bright
When degree has otherness, according to voltage contrast corresponding to each test layer obtained, the lamination is led
Electric structure carries out FIB cross-section analyses, to obtain the region that open circuit is produced in the laminated conductive structure；When
When voltage contrast brightness corresponding to each test layer is identical, open test is carried out to the test layer.
Optionally, the electrical testing includes carrying out open test, the open test to the test layer
Including：Several described discrete test layers are divided into multiple test groups, each test group includes first test
Layer, tail test layer and several test layers between first test layer and tail test layer；To each test
First test layer and the tail test layer of group carries out overall electrical testing, judges that stacking is led corresponding to the test group
Whether electric structure opens a way；When detecting that laminated conductive structure is not opened a way corresponding to the test group, under
First test layer and the tail test layer of one test group carries out overall electrical testing；When judging that the test group is corresponding
Laminated conductive structure open circuit when, the test group is carried out using dichotomy to limit electrical testing, until
Navigate in laminated conductive structure corresponding to the test group and produce the region of open circuit.
Optionally, to the test group limit the method for electrical testing using dichotomy includes：First
Test：Using the test layer of the test group central spot as ground zero test layer, the ground zero test layer,
First test layer and the test layer between ground zero test layer and first test layer form the first newly test
Group, overall electrical testing is carried out to the ground zero test layer and first test layer, judge the described first new survey
Whether laminated conductive structure opens a way corresponding to examination group；Second test：With the survey of the test group central spot
Examination layer is ground zero test layer, the ground zero test layer, tail test layer and positioned at ground zero test layer
Test layer between tail test layer forms the second new test layer, and the ground zero test layer and tail are tested
Layer carries out overall electrical testing, judges whether lamination conductive structure corresponding to the described second new test group opens a way；
When laminated conductive structure corresponding to the described first new test group is opened a way, the described first new test group is carried out
First test and the second test, until navigating to laminated conductive knot corresponding to the described first new test group
The region of open circuit is produced in structure；It is right when laminated conductive structure corresponding to the described second new test group is opened a way
Second new test group progress first test and the second test, are newly surveyed until navigating to described second
The region of open circuit is produced in laminated conductive structure corresponding to examination group.
Optionally, the chip area be shaped as it is square；Some discrete test layers are divided into 4
Individual test group.
Optionally, before the passivation layer is removed, in addition to：Conventional survey is carried out to the test structure
Examination, judges whether there is abnormity point in the test structure；If note abnormalities a little, to the test structure
Physical verification analysis is carried out, obtains the region that open circuit is produced in laminated conductive structure；If no abnormal,
The passivation layer is removed, electrical testing is carried out to the test layer.
Compared with prior art, technical scheme has advantages below：
In the technical scheme of test structure provided by the invention, the test structure, which is removed, includes laminated conductive knot
Outside structure, the test layer that is additionally provided with laminated conductive structure, and passivation layer is located at the test layer top
In portion；When being tested using test structure provided by the invention, removing passivation layer can be by test layer
The thickness of thin of required removal when being exposed, therefore exposing test layer so that remove test layer after passivation layer
Can uniformly it be exposed, so as to carry out electrical testing to the test layer.By testing not
With the electrical property between test layer, you can know in the laminated conductive structure below test layer whether produce
Raw open circuit problem；Also, because test layer is easily exposed, thus by test different test layers it
Between electrical property, also easily know the area that corresponding laminated conductive structure is opened a way between which two test layer
Domain, so as to accurately orient the position being layered corresponding to chip area, improve and chip is lost
Imitate the accuracy of analysis.
In alternative, the distance between adjacent described test layer is less than or equal to 10 μm, so as to avoid pair
Test layer carries out the unnecessary interference problem being subject to during electrical testing, improves the degree of accuracy of test.
In the technical scheme of method of testing provided by the invention, the test layer is easily uniformly exposed
Come, so as to carry out electrical testing to some discrete test layers, so as to obtain laminated conductive knot
The region of open circuit is produced in structure；According to the region that open circuit is produced in the laminated conductive structure, chip is obtained
The position that region is layered so that the accuracy rate for finding chip area generation layered position is significantly carried
Rise.
In alternative, the test group is carried out using dichotomy to limit electrical testing, can shorten and obtain
Get and time needed for the region of open circuit is produced in laminated conductive structure, improve testing efficiency.
Brief description of the drawings
Fig. 1 and Fig. 2 is a kind of semiconductor structure cross-sectional view for including test structure；
Fig. 3 to Fig. 5 is the structural representation for the test structure that one embodiment of the invention provides；
Fig. 6 and Fig. 7 is provides signal when method of testing is tested test structure using the present embodiment
Figure；
Fig. 8 is the local overlooking schematic diagram that the method for testing that the present embodiment provides includes a test group.
Embodiment
From background technology, prior art confirms that the difficulty of chip layered position is big, finds chip failure
The accuracy rate of point has much room for improvement.When being electrically able to confirm that chip failure, it is difficult to carry out physical property to chip
On analysis, to obtain chip failure particular location, that is, be difficult to navigate to the specific position that chip is layered
Put.
Through analysis, Fig. 1 and Fig. 2 are a kind of semiconductor structure cross-section structure signal for including test structure
Figure.Wherein, Fig. 1 is the sectional view cut along chip cutting road region, and Fig. 2 is perpendicular to chip cutting
The cross-sectional view of road region cutting, the semiconductor structure include：Substrate 101, the substrate
101 include chip area and the fringe region (edge area) around the chip area；The substrate
There is chip 102 on 101 chip areas；Formed with laminated conductive structure on the fringe region of substrate 101
103, the laminated conductive structure 103 includes the metal level of multiple-level stack, wherein, laminated conductive structure 103
The bottom metal layer 10 of top layer metallic layer 30 and the bottom including top, in addition to it is located at top layer
Intermediate metal layer 20 between metal level 30 and bottom metal layer 10, adjacent layer metal level are inserted by conduction
The electrical connection of plug 11, the discrete top layer metallic layer 30 is around the chip area.
By testing whether the metal level in the laminated conductive structure 103 opens a way, the chip 102 is obtained
In whether lamination problem occurs.
However, using the semiconductor structure of above-mentioned offer, pass through the gold in the laminated conductive structure 103
Whether whether category layer opens a way, can obtain in chip and be layered, i.e., electrically can confirm that layering is asked
The presence of topic, it can be difficult to being analyzed from physical property lamination problem, it is mainly reflected in and is difficult to obtain core
Occurs the position being layered in piece.
Found through analysis, because lamination problem appears in bottom of the chip 102 with first thickness more in chip
In portion region (not indicating), therefore, setting overhead height and the bottom section overhead height of first thickness
Laminated conductive structure 103 consistent or that difference is less, you can with by laminated conductive structure 103 from electrically
Confirm whether there is lamination problem in chip 102.
The first thickness is small more compared with the integral thickness of chip, so as to cause laminated conductive structure 103
The distance between top of top and chip 102 differs greatly.In order to find out the layered position of chip 102, need
Chip 102 is ground until exposure is except the surface of top layer metallic layer 30 of laminated conductive structure 103.
However, because the top of chip 102 and the distance between top layer metallic layer 30 are big, therefore grind the thickness removed
Degree is thick, and the uncontrollable factor for grinding the thicker technique of thickness of removal is more；And the ring of laminated conductive structure 103
Around the chip 102, it is thicker to grind the thickness of removal, is more difficult to ensure that grinding terminates rear laminated conductive structure
All discrete top layer metallic layers 30 in 103 are uniformly exposed, it is possible to cause some regions
Top layer metallic layer 30 removed by complete grinding, it is also possible to there is the top layer metallic layer 30 in other regions
Do not expose also, so as to cause to be difficult to carry out the layered position of chip 102 by laminated conductive structure 103
Positioning.
To solve the above problems, the present invention provides a kind of test structure, Fig. 3 to Fig. 5 is real for the present invention one
The structural representation of the test structure of example offer is provided.Wherein, Fig. 3 is top view, and Fig. 4 is edge in Fig. 3
The sectional view in AA1 directions, along the cross-sectional view in BB1 directions, it is necessary to illustrate in Fig. 5 bitmaps 3
, for the ease of illustrating and illustrating, complete overlooking the structure diagram not shown in Fig. 3.
The test structure includes：
Substrate 200, the substrate 200 include chip area I；
Laminated conductive structure in the substrate 200, the laminated conductive structure are included from the bottom to top
Bottom conductive layer 210, interconnection layer structure and top layer conductive layer 230, wherein, the bottom is conductive
Layer 210, interconnection layer structure and top layer conductive layer 230 are sequentially connected with chain of the cyclization around the chip area I
Bar structure；
Some discrete test layers above the top layer conductive layer 230, each test layer it is corresponding with
At least one top layer conductive layer 230 electrically connects, and some discrete test layers are around the chip region
Domain I；
Dielectric layer 204 in the laminated conductive structure and in test layer side wall；
Passivation layer 205 at the top of the top of dielectric layer 204 and test layer.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
The substrate 200 is silicon base, germanium substrate, SiGe substrate, silicon carbide substrate, GaAs base
Bottom or gallium indium substrate, the substrate 200 can also be the silicon base on insulator.Partly led to improve
Body structural behaviour, the surface of substrate 200 can also be formed with some one functional layers, such as in substrate 200
Surface forms interfacial TCO layer.
The substrate 200 includes chip area I, in the present embodiment, with being shaped as the chip area I
Exemplified by square, in other embodiments, the shape of the chip area can also be circular, ellipse or
Other irregular shapes.The chip
The substrate 200 also includes the Cutting Road region II around the chip area I, the chip area
I is effective coverage, and the Cutting Road region II is that can be cut after detection, ineffectiveness analysis is completed to chip
Prescind the region removed.In the present embodiment, in order to save space, laminated conductive structure is avoided to occupy chip position
Put, the laminated conductive structure is located on the II of Cutting Road region.In other embodiments, can also be in core
The laminated conductive structure is set in panel region.
The chip area I of the substrate 200 has chip 201, and the chip 201 includes：Positioned at described
The layering district occurred frequently H of the base section thickness of chip 201 and above the layering district occurred frequently H
It is layered Di Fa area L.
It should be noted that " height " and " low " in layering district occurred frequently H herein and layering Di Fa area L
It is that both compare, lamination problem easily occurs for the chip 201 of the layering district occurred frequently H, institute
Lamination problem is less likely to occur relatively for the chip 201 for stating layering Di Fa area L.
The thickness of the layering district occurred frequently H is less than or equal to the thickness of the layering Di Fa areas L.In general,
The integral thickness of the chip 201 is much larger than the thickness of the layering district occurred frequently H.For example, the chip
201 integral thickness is 1.5 times~500 times of the thickness of the layering district occurred frequently H.
The laminated conductive structural top is less than the top of chip 201.In the present embodiment, described in setting
Laminated conductive structural top at the top of the layering district occurred frequently H with flushing so that the laminated conductive structure energy
The lamination problem of enough effective chips 201 for perceiving layering district occurred frequently H.When layering district occurred frequently H chip
201 when being layered, and can accordingly cause laminated conductive structure that layering occurs and the generation of laminated conductive structure is held
Road.The laminated conductive structure will be subsequently described in detail.
The conductive layer of the bottom is bottom conductive layer 210 in the laminated conductive structure, positioned at the layer
The conductive layer of top is top layer conductive layer 230 in folded conductive structure, positioned at the bottom and top it
Between conductive layer be interconnection layer structure, the interconnection layer structure includes：If the intermediate conductive layer that dried layer stacks
220, the number of plies of the intermediate conductive layer 220 is more than or equal to 1.
Whether occurring point for detection is needed in the laminated conductive structure in the number of plies of conductive layer and chip 201
The number of plies of layer is relevant.In one embodiment, in the laminated conductive structure conductive layer the number of plies and chip
Need the number of plies that whether can be layered of detection identical in 201.In another embodiment, the laminated conductive
In structure the number of plies of conductive layer be more than chip 201 in need detection whether the number of plies that can be layered.
With layer the bottom conductive layer 210 quantity according to the width dimensions of the bottom conductive layer 210,
The gradient of the number of plies of laminated conductive structure, chip area I girths and chain structure is determined.This
In embodiment, the quantity of the top layer conductive layer 230 is identical with the quantity of the bottom conductive layer 210；
Quantity with the intermediate conductive layer 220 of layer is 2 times of the quantity of the bottom conductive layer 210.
The bottom conductive layer 210, interconnection layer structure and top layer conductive layer 230 be sequentially connected with to be formed it is circular
The chain structure (stack chain) of the chip area I, when lamination problem does not occur for chip 201, institute
It is closed-loop path to state chain structure；When the chip 201 is layered, it will cause the chain structure
Open circuit.
The chain structure includes some groups of stacked structures sequentially electrically connected, and each group of stacked structure includes：
At least one bottom conductive layer 210, at least one top layer conductive layer 230 and conductive positioned at the bottom
Interconnection layer structure between layer 210 and top layer conductive layer 230.Adjacent stacked structure shares the bottom
Conductive layer 230.
In the present embodiment, included with each group of stacked structure：Two bottom conductive layers, 210, top layers are led
Exemplified by electric layer 230, the interconnection layer structure between top layer conductive layer 230 and bottom conductive layer 210, phase
Top layer conductive layer 230 is shared between adjacent stacked structure, the stacked structure is made by bottom conductive layer 210
It is sequentially connected with to form chain structure.In other embodiments, in the present embodiment, along Cutting Road region II
On bearing of trend, the section shape of each group of stacked structure is triangle, accordingly, the chain structure
In triangular wave waveform.
In other embodiments, along the bearing of trend of Cutting Road region, the section of each group of stacked structure
Shape can also be it is square, accordingly, the rectangular ripple waveform of chain structure.
In addition, in the present embodiment, the chain structure is the annular of closing, and the laminated conductive structure can
Comprehensively to perceive caused lamination problem in chip 201, positioned so as to improve using the test structure
The accuracy rate of layered position occurs for chip area I.
In the present embodiment, in order to be protected to chip 201, the test structure also includes：Positioned at institute
State the first protection ring 202 and the second protection ring 203 in substrate 201, and the laminated conductive structure bit
Between the protection ring 203 of the first protection ring 202 and second.
First protection ring 202 is described around the chip area I and on the II of Cutting Road region
Second protection ring 203 is around the chip area I and on the II of Cutting Road region.
In the present embodiment, first protection ring 202 is located between chip area I and the second protection ring 203,
First protection ring 202 is SR structures, and second protection ring is CAS structures.In other implementations
, can be using the first protection ring as CAS structures in example, the second protection ring is SR structures.
In the present embodiment, the top of the first protection ring 202 flushes with the top of chip 201, and described second
The top of protection ring 203 flushes with the top of chip 201.In other embodiments, first protection
It can be above at the top of the chip, can be above at the top of second protection ring at the top of chip at the top of ring.
Accordingly, the laminated conductive structural top is less than the top of the first protection ring 202, i.e., described
The top of top layer conductive layer 230 is less than the top of the first protection ring 202；The laminated conductive structural top
Less than the top of the second protection ring 203, i.e., the described top of top layer conductive layer 230 is protected less than described second
The top of retaining ring 203.
The test structure also includes：Conductive plunger 211, the conductive plunger 211 are described for electrically connecting
Bottom conductive layer 210, interconnection layer structure and top layer guided missile layer 230；In the present embodiment, also by described
Conductive plunger 211 electrically connects the intermediate conductive layer 220 of adjacent layer.
The test layer corresponds to and a top layer positioned at the top of top layer conductive layer 230, each test layer
Conductive layer 230 electrically connects, and some discrete test layers are around the chip area I.
Flushed at the top of the test layer with the top of chip 102.In the present embodiment, the test layer top
Portion flushes with the top of chip 102；At the top of the test layer also with the top of the first protection ring 202
And the top of the second protection ring 203 flushes.In other embodiments, can be with height at the top of the test layer
At the top of the chip.
The thickness of the test layer is more than the laminated conductive structure integral thickness.In one embodiment, institute
The thickness for stating test layer is 1~10 times of the laminated conductive structure；It is described in another specific embodiment
The thickness of test layer can also be the decades of times of the laminated conductive structure integral thickness or even hundreds times.This
Outside, passivation layer 205 need to be removed when testing test structure, to ensure the removal passivation layer 205
Influence of the technical process to test layer it is small, the thickness of the test layer is thicker.In one embodiment,
The thickness of the test layer is more than or equal to 200 μm.
If the distance between adjacent test layer l is excessive, it is unnecessary to be introduced when carrying out failure analysis
Interference.In order to ensure the distance between adjacent test layer l to be adapted to failure analysis as criterion, the present embodiment
In, the distance between adjacent described test layer l is less than or equal to 10 μm.
On parallel to the test layer orientation, the width dimensions w of the test layer is more than or equal to
1 μm so that in test process is carried out to test structure, remove the easy quilt of test layer after passivation layer 205
It is exposed；Also, the width dimensions of the test layer are larger, be advantageous to improve test process middle probe
The accuracy electrically connected with test layer.
In the present embodiment, the test layer includes：Bottom test layer 240 and positioned at bottom test layer 240
The top layer test layer 250 of top, and lead between the top layer test layer 250 and the bottom test layer 240
Test plug 251 is crossed to electrically connect.The test structure also includes：Positioned at the bottom test layer 240 with
Attachment plug 241 between top layer conductive layer 230, the attachment plug 241 make the top layer conductive layer
230 electrically connect with the bottom test layer 240.
Wherein, the distance between adjacent described top layer test layer 250 l is less than or equal to 10 μm；Parallel
In in the orientation of top layer test layer 250, the width dimensions w of top layer test layer 250 be more than or
Equal to 1 μm；The thickness of the top layer test layer 250 is more than or equal to 200 μm.
It should be noted that in other embodiments, the test layer can also include more than two layers of heap
Folded test layer, and adjacent layer test layer is electrically connected by attachment plug；The test layer can also be single
The test layer of layer.
The test structure also includes：Jie in the laminated conductive structure and in test layer side wall
Matter layer 204, the dielectric layer 204 are also located in the side wall of chip 201.The material of the dielectric layer 204
Material includes silica, silicon nitride or silicon oxynitride.
The test structure also includes：Passivation at the top of the top of dielectric layer 204 and test layer
Layer (passivation layer) 205, the passivation layer 205 provide protective effect to chip 201, avoided
Chip 201 is exposed in external environment, and the passivation layer 205 also provides protection to the test layer and made
With.The material of the passivation layer 205 be silica, silicon nitride, p-doped silica, boron-doping silica or
The silica of p-doped and boron.
In the test structure that the present embodiment provides, in addition to including laminated conductive structure, it is additionally provided with positioned at layer
Test layer on folded conductive structure, and passivation layer is located at the top of the test layer；Therefore this implementation is used
When the test structure that example provides is tested, removing passivation layer, test layer can be exposed, and pass through
The electrical property tested between different test layers, you can know in underlying laminated conductive structure whether produce
Raw open circuit problem；Also, because test layer is easily exposed, thus by test different test layers it
Between electrical property, also easily know the area that corresponding laminated conductive structure is opened a way between which two test layer
Domain, so as to accurately orient the position being layered corresponding to chip area, improve and chip is lost
Imitate the accuracy of analysis.
In addition, the test layer set in the present embodiment is located at the top of the laminated conductive structure, therefore institute
State the layout of the testing cushion (test pad) of the vacant chip of test layer.
Accordingly, the present invention also provides a kind of method of testing, including：Foregoing test structure is provided；Go
Except the passivation layer, until exposing some discrete test layers；The test layer is carried out electrical
Test, obtains the region that open circuit is produced in the laminated conductive structure；According in the laminated conductive structure
The region of open circuit is produced, obtains the position that chip area is layered.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
With reference to figure 4 and Fig. 5, in the present embodiment, in order to reduce difficulty of test and complexity, institute is being removed
Before stating passivation layer 205, to the test structure carry out conventionally test, judge be in the test structure
It is no that there is abnormity point.
The conventionally test includes：The test structure is detected under light microscope (OM),
Judge whether there is lamination problem in the test structure by light microscope；To the test structure
The lower surface of substrate 201 is processed by shot blasting, carries out bottom to the test structure after a polishing process
Laser scanning, judge whether there is lamination problem in the test structure by the laser scanning.
If generation abnormity point, physical verification analysis (PFA, Physical Failure is carried out to the test structure
Analysis), obtain in laminated conductive structure and produce the region of open circuit, and then occur in positioning chip 201
The position of layering；If no exceptions point, removing the passivation layer 205, the test layer is carried out electrical
Test.
It should be noted that in other embodiments of the present invention, foregoing conventionally test can also be saved, directly
Connect and electrical testing is carried out to the test layer of the test structure, obtain to produce in the laminated conductive structure and open
The region on road.
The electrical testing is described in detail below with reference to accompanying drawing.Fig. 6 and Fig. 7 is using this reality
Apply schematic diagram when example offer method of testing is tested test structure.
With reference to figure 6 and Fig. 7, the passivation layer 205 (with reference to figure 4 and Fig. 5) is removed, until exposing institute
State some discrete test layers.
In the present embodiment, the passivation layer 205 is removed until exposing some discrete top layer tests
Layer 250.
Using the method for physical etchings, etching removes the passivation layer 205.Gone using the method for physical etchings
Except the passivation layer 205, be advantageous to improve the flatness that passivation layer 205 is removed rear test structure.
In the present embodiment, because the lower surface of passivation layer 205 is in contact with test layer, therefore etch
Test layer can be exposed after removing passivation layer 205, avoid required etching or the thickness of grinding removal
Spend the problem of top layer conductive layer caused by thickness is difficult to uniformly be exposed.
In addition, in the present embodiment, the thickness of the test layer is thicker, therefore even if physical etchings can be to surveying
Try layer and carry out a certain degree of etching, also still ensure that etching removes all test layers after passivation layer 205
Remain to be used for electrical testing.
Test structure for forming test layer not in laminated conductive structure, to top layer conductive layer is sudden and violent
Expose to carry out electrical testing, then in addition to passivation layer is removed, it is also necessary to the chip in layering Di Fa areas is removed,
Top layer conductive layer is caused to be difficult to uniformly be exposed, therefore, it is difficult to electrically surveyed to top layer conductive layer
Examination.
After some discrete test layers are exposed, electrical testing is carried out to the test layer,
Obtain the region that open circuit is produced in the stepped construction.In the present embodiment, to the top layer test layer 250
Electrical testing is carried out, obtains the region that open circuit is produced in the stepped construction.
Simplify testing procedure, in the present embodiment, the electrical testing bag to further reduce difficulty of test
Include：Voltage contrast comparison (VC) analysis is carried out to some discrete test layers, obtains each test layer
Corresponding voltage contrast；When voltage contrast brightness corresponding to each test layer has otherness, foundation
Voltage contrast corresponding to each test layer obtained, FIB (Focused are carried out to the lamination conductive structure
Ion Beam) cross-section analysis, to obtain the region that open circuit is produced in the laminated conductive structure.
Specifically, carrying out voltage contrast to some discrete top layer test layers 250 compares analysis, when
When being opened a way in laminated conductive structure corresponding to a certain top layer test layer 250, the top layer test layer 250
Corresponding voltage contrast will be darker than voltage contrast corresponding to other top layer test layers 250.The voltage is served as a contrast
Spend laminated conductive structural region corresponding to dark top layer test layer 250 and carry out FIB cross-section analyses, obtain institute
State the region that open circuit is produced in laminated conductive structure.
When voltage contrast brightness corresponding to each test layer is identical, open circuit survey is carried out to the test layer
Examination.It should be noted that in other embodiments, may be omitted with foregoing voltage contrast and compare analysis,
Open test directly is carried out to the test layer.Open-circuit test is described in detail below.
The electrical testing includes carrying out open test to the test layer, and the open test includes：Will
Several described discrete test layers are divided into multiple test groups, and each test group includes first test layer, tail is surveyed
Try layer and several test layers between first test layer and tail test layer；The head of each test group is surveyed
Try layer and tail test layer carries out overall electrical testing, judge that laminated conductive structure is corresponding to the test group
No open circuit；When detecting that laminated conductive structure is not opened a way corresponding to the test group, to next test group
First test layer and tail test layer carry out overall electrical testing；Led when judging to be laminated corresponding to the test group
During electric structure open circuit, the test group is carried out using dichotomy to limit electrical testing, until navigating to institute
State the region that open circuit is produced in laminated conductive structure corresponding to test group.Wherein, in each test group
First top layer test layer 250 is used as first test layer, last top layer test in each test group
Layer 250 is as tail test layer, it is necessary to which explanation, the determination of the first test layer and tail test layer is phase
For.
In the present embodiment, being shaped as the chip area I is square；Accordingly by some discrete surveys
Examination layer is divided into 4 test groups.And each adjacent square chip area I of a test group side.
With reference to figure 8, Fig. 8 is the fragmentary top that the method for testing provided in the present embodiment includes a test group
Depending on schematic diagram, the top layer test layer 250 is tested, and using probe (probe) 500 to treating
Two test layers of test provide voltage or electric current, to complete electrically to survey the entirety of the test group
Try and limit electrical testing.Specifically, using probe 500 to two top layer conductive layers 250 to be tested
Voltage or electric current are provided.
In Fig. 8, so that the test group includes 5 top layer test layers 250 as an example, the entirety is electrically surveyed
The method of examination is：A probe 500 is provided to electrically connect with first top layer test layer 250；There is provided another probe with
Tail top layer test layer 250 electrically connects；Carried using the probe 500 to described two top layer test layers 250
Voltage supplied or electric current, to complete the overall electrical testing to the test group, judge that the test group is corresponding
Laminated conductive structure whether open a way.
In the present embodiment, to the test group limit the method for electrical testing using dichotomy includes：
First test：Using the test layer of the test group central spot as ground zero test layer, described new
Point test layer, first test layer and test layer between ground zero test layer and first test layer form the
One new test group, carries out overall electrical testing to the ground zero test layer and first test layer, described in judgement
Whether laminated conductive structure corresponding to the first new test group opens a way；
The top layer test layer 250 of described first new test group is tested, using probe to described first
The top layer test layer 250 of new test group provides voltage or electric current, to complete the institute of the described first new test group
State overall electrical testing.
Specifically, with reference to figure 8, it is so that each test group includes 5 top layer conductive layers 250 as an example, then described
3rd top layer conductive layer 250 is ground zero test layer, 250, second, first top layer conductive layer
Top layer conductive layer 250 and the 3rd top layer conductive layer 250 form the first new test group.
It should be noted that the quantity of the top layer test layer 250 of each test group is N, the ground zero
Test layer is n-th of top layer test layer 250；When N is even number, n is (N/2)+1 or (N/2)
-1；When N is odd number, n rounds up for N/2.
Second test：Using the test layer of the test group central spot as ground zero test layer, described new
Point test layer, tail test layer and test layer between ground zero test layer and tail test layer form the
Two new test layers, carry out overall electrical testing to the ground zero test layer and tail test layer, described in judgement
Whether lamination conductive structure corresponding to the second new test group opens a way；
The top layer test layer 250 of described second new test group is tested, using probe to described second
The top layer test layer 250 of new test group provides voltage or electric current, to complete the institute of the described second new test group
State overall electrical testing.Specifically, with reference to figure 8,5 top layer conductive layers 250 are included with each test group
Exemplified by, then the 3rd top layer conductive layer 250 is ground zero test layer, the 3rd top layer test
250, the 4th top layer test layer 250 of layer and the 5th top layer test layer 250 form the second new test layer.
It should be noted that the quantity of the top layer test layer 250 of each test group is N, the ground zero
Test layer is n-th of top layer test layer 250；When N is even number, n is (N/2)+1 or (N/2)
-1；When N is odd number, n rounds up for N/2.
In addition, and then it is described first test carry out second test in, the ground zero test layer of selection with
The ground zero test layer chosen in first test should be identical.
When laminated conductive structure corresponding to the described first new test group is opened a way, to the described first new test group
First test and the second test are carried out, is led until navigating to stacking corresponding to the described first new test group
The region of open circuit is produced in electric structure；
Specifically, it is that boundary is newly surveyed described first by the test layer of the described first new test group central spot
Examination group is divided into two sub- test groups, first test is carried out to one of them sub- test group, to another
Sub- test group carries out second test；Repeat first test and the second test, until fixed
Position produces the region of open circuit into laminated conductive structure corresponding to the described first new test group.
When laminated conductive structure corresponding to the described second new test group is opened a way, to the described second new test group
First test and the second test are carried out, is led until navigating to stacking corresponding to the described second new test group
The region of open circuit is produced in electric structure.
Specifically, by the described second new test group center place test layer for boundary it is new by described second
Test group is divided into two sub- test groups, first test is carried out to one of them sub- test group, to another
One sub- test group carries out second test；Repeat first test and the second test, until fixed
Position produces the region of open circuit into laminated conductive structure corresponding to the described second new test group.
The test group is carried out using dichotomy to limit electrical testing, any two top layers tested for choosing
The purpose of electric property between conductive layer 250 is strong, and top layer conductive is obtained using the method gradually approached
Electric property between layer 250, can shorten and get the region institute that open circuit is produced in laminated conductive structure
The time needed, improve testing efficiency.
Obtaining the method for the position that the chip area is layered includes：To in the laminated conductive structure
The region for producing open circuit carries out physical verification analysis, positions the position that the laminated conductive structure is opened a way,
The layer that the laminated conductive structure produces the position correspondence of open circuit is the position that chip area I is layered.
Test layer described in the present embodiment is easily uniformly exposed, so as to described some points
Vertical test layer carries out electrical testing, so as to obtain the region that open circuit is produced in laminated conductive structure；Foundation
The region of open circuit is produced in the laminated conductive structure, obtains the position that chip area I is layered so that
Find chip area occur layered position accuracy rate be significantly improved, for example, with top layer conductive layer
The test structure for not forming test layer is compared, and the test structure positioning chip region that the present embodiment provides occurs
The accuracy rate of layered position is by 0 lifting to 70% even more high.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (20)
- A kind of 1. test structure, it is characterised in that including：Substrate, the substrate include chip area；Laminated conductive structure in the substrate, the laminated conductive structure include bottom from the bottom to top Layer conductive layer, interconnection layer structure and top layer conductive layer, wherein, the bottom conductive layer, interconnection layer knot Structure and top layer conductive layer are sequentially connected with the chain structure to be formed around the chip area；Discrete test layer above the top layer conductive layer, the discrete test layer is corresponding and pushes up Layer conductive layer electrical connection, and the discrete test layer is around the chip area；Dielectric layer in the laminated conductive structure and in test layer side wall；Passivation layer at the top of the dielectric layer and at the top of test layer.
- 2. test structure as claimed in claim 1, it is characterised in that the distance between adjacent described test layer Less than or equal to 10 μm.
- 3. test structure as claimed in claim 1, it is characterised in that parallel to the test layer arrangement side Upwards, the width dimensions of the test layer are more than or equal to 1 μm.
- 4. test structure as claimed in claim 1, it is characterised in that the chain structure is in triangular wave waveform Or square wave waveform.
- 5. test structure as claimed in claim 1, it is characterised in that the chain structure is suitable including some groups The stacked structure of secondary electrical connection, each group of stacked structure include：At least one bottom conductive layer and extremely A few top layer conductive layer, in addition to：Interconnection layer between bottom conductive layer and top layer conductive layer Structure.
- 6. test structure as claimed in claim 5, it is characterised in that between the adjacent stacked structure altogether Enjoy bottom conductive layer.
- 7. test structure as claimed in claim 1, it is characterised in that the chip area of the substrate has core Piece, the chip include：Positioned at the layering district occurred frequently of chip bottom segment thickness and positioned at described The layering Di Fa areas being layered above district occurred frequently；Wherein, the laminated conductive structural top and the layering Flushed at the top of district occurred frequently.
- 8. test structure as claimed in claim 1, it is characterised in that the test structure also includes：It is located at The first protection ring and the second protection ring in the substrate, and the laminated conductive structure is positioned at described Between first protection ring and the second protection ring.
- 9. test structure as claimed in claim 8, it is characterised in that the laminated conductive structural top is less than At the top of first protection ring；The laminated conductive structural top is less than at the top of second protection ring； Flushed at the top of the test layer with the top of first protection ring and at the top of the second protection ring.
- 10. test structure as claimed in claim 1, it is characterised in that the test structure also includes：It is conductive Connector, the conductive plunger are led for electrically connecting bottom conductive layer, interconnection layer structure and the top layer Electric layer.
- 11. test structure as claimed in claim 10, it is characterised in that the interconnection layer structure includes：It is some The intermediate conductive layer that layer stacks, and intermediate conductive layer described in adjacent layer is electrically connected by the conductive plunger Connect.
- 12. test structure as claimed in claim 1, it is characterised in that the test layer includes bottom test layer And the top layer test layer above bottom test layer, and the top layer test layer is surveyed with the bottom Electrically connected between examination layer by test plug.
- 13. test structure as claimed in claim 1, it is characterised in that the substrate is also included around the core The Cutting Road region of panel region, and the laminated conductive structure is located at the Cutting Road region.
- A kind of 14. method of testing, it is characterised in that including：Test structure as described in any one of claim 1~13 is provided；The passivation layer is removed, until exposing some discrete test layers；Electrical testing is carried out to some discrete test layers, obtains and is produced in the laminated conductive structure The region of open circuit；According to the region that open circuit is produced in the laminated conductive structure, the position that chip area is layered is obtained Put.
- 15. method of testing as claimed in claim 14, it is characterised in that obtain the chip area and be layered The method of position include：Physical verification is carried out to the region that open circuit is produced in the laminated conductive structure Analysis, positions the position that the laminated conductive structure is opened a way, and the laminated conductive structure is produced and opened The floor of the position correspondence on road is the position that chip area is layered.
- 16. method of testing as claimed in claim 14, it is characterised in that the electrical testing includes：Voltage contrast is carried out to some discrete test layers and compares analysis, is obtained corresponding to each test layer Voltage contrast；It is described each according to what is obtained when voltage contrast brightness corresponding to each test layer has otherness Voltage contrast corresponding to test layer, FIB cross-section analyses are carried out to the lamination conductive structure, to obtain State the region that open circuit is produced in laminated conductive structure；When voltage contrast brightness corresponding to each test layer is identical, open circuit survey is carried out to the test layer Examination.
- 17. method of testing as claimed in claim 14, it is characterised in that the electrical testing is included to the survey Try layer and carry out open test, the open test includes：Several described discrete test layers are divided into multiple test groups, each test group include first test layer, Tail test layer and several test layers between first test layer and tail test layer；Overall electrical testing is carried out to first test layer and the tail test layer of each test group, judges the test Whether laminated conductive structure opens a way corresponding to group；When detecting that laminated conductive structure is not opened a way corresponding to the test group, to the head of next test group Test layer and tail test layer carry out overall electrical testing；When judging that laminated conductive structure corresponding to the test group is opened a way, using dichotomy to the test Group carries out limiting electrical testing, is opened until navigating to and being produced in laminated conductive structure corresponding to the test group The region on road.
- 18. method of testing as claimed in claim 17, it is characterised in that entered using dichotomy to the test group The method that row limits electrical testing includes：First test：Using the test layer of the test group central spot as ground zero test layer, described new Point test layer, first test layer and test layer between ground zero test layer and first test layer form the One new test group, carries out overall electrical testing to the ground zero test layer and first test layer, described in judgement Whether laminated conductive structure corresponding to the first new test group opens a way；Second test：Using the test layer of the test group central spot as ground zero test layer, described new Point test layer, tail test layer and test layer between ground zero test layer and tail test layer form the Two new test layers, carry out overall electrical testing to the ground zero test layer and tail test layer, described in judgement Whether lamination conductive structure corresponding to the second new test group opens a way；When laminated conductive structure corresponding to the described first new test group is opened a way, to the described first new test group First test and the second test are carried out, is led until navigating to stacking corresponding to the described first new test group The region of open circuit is produced in electric structure；When laminated conductive structure corresponding to the described second new test group is opened a way, to the described second new test group First test and the second test are carried out, is led until navigating to stacking corresponding to the described second new test group The region of open circuit is produced in electric structure.
- 19. method of testing as claimed in claim 17, it is characterised in that being shaped as the chip area is square； Some discrete test layers are divided into 4 test groups.
- 20. method of testing as claimed in claim 14, it is characterised in that before the passivation layer is removed, also Including：Conventionally test is carried out to the test structure, judges whether there is exception in the test structure Point；If noting abnormalities a little, physical verification analysis is carried out to the test structure, obtains laminated conductive knot The region of open circuit is produced in structure；If no abnormal, the passivation layer is removed, to the test layer Carry out electrical testing.
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| CN109712963A (en) * | 2018-12-29 | 2019-05-03 | 上海华力集成电路制造有限公司 | CPI tests structure and the failure analysis method based on the structure |
| CN110571206A (en) * | 2019-09-12 | 2019-12-13 | 芯盟科技有限公司 | Semiconductor structure and forming method thereof and forming method of chip |
| CN110571205A (en) * | 2019-09-12 | 2019-12-13 | 芯盟科技有限公司 | Semiconductor structure and forming method thereof |
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| US20120305916A1 (en) * | 2011-06-03 | 2012-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interposer Test Structures and Methods |
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| US20120049884A1 (en) * | 2008-02-13 | 2012-03-01 | Infineon Technologies Ag | Crack Sensors for Semiconductor Devices |
| US20120305916A1 (en) * | 2011-06-03 | 2012-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interposer Test Structures and Methods |
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| CN109712963A (en) * | 2018-12-29 | 2019-05-03 | 上海华力集成电路制造有限公司 | CPI tests structure and the failure analysis method based on the structure |
| CN110571206A (en) * | 2019-09-12 | 2019-12-13 | 芯盟科技有限公司 | Semiconductor structure and forming method thereof and forming method of chip |
| CN110571205A (en) * | 2019-09-12 | 2019-12-13 | 芯盟科技有限公司 | Semiconductor structure and forming method thereof |
| CN110571206B (en) * | 2019-09-12 | 2022-05-27 | 芯盟科技有限公司 | Semiconductor structure and forming method thereof and forming method of chip |
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