CN107579040A - A kind of mask plate, array base palte and preparation method thereof - Google Patents
A kind of mask plate, array base palte and preparation method thereof Download PDFInfo
- Publication number
- CN107579040A CN107579040A CN201710801200.0A CN201710801200A CN107579040A CN 107579040 A CN107579040 A CN 107579040A CN 201710801200 A CN201710801200 A CN 201710801200A CN 107579040 A CN107579040 A CN 107579040A
- Authority
- CN
- China
- Prior art keywords
- conductive pattern
- layer
- array base
- base palte
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electroluminescent Light Sources (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The present invention provides a kind of mask plate, array base palte and preparation method thereof, and the array base palte includes viewing area and PAD region, and the preparation method of the array base palte includes：Form the conductive pattern of the PAD region；Form the protection figure at least part region for covering the conductive pattern；After the default film layer figure of the viewing area is formed, the protection figure is removed.In the present invention; after the conductive pattern of PAD region is formed; form the protection figure at least part region for covering the conductive pattern; at least part region of conductive pattern is protected; so as to avoid during the default film layer figure of viewing area is formed; the etching liquid damage of default film layer figure is used to form, improves the yield of array base palte.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of mask plate, array base palte and preparation method thereof.
Background technology
Array base palte generally includes viewing area (AA regions) and PAD region, wherein, viewing area generally include grid line,
The component such as data wire equisignal line and thin film transistor (TFT) (TFT).PAD region is crimp region, is for by the letter of viewing area
The region that number line is crimped with the lead of the drive circuit board of outside.PAD region is typically provided only with conductive pattern, conductive pattern
For connecting the lead of drive circuit board and the signal wire of array base palte of outside, thus must not insulated above conductive pattern
Layer covering.
But in actual production, due to being covered above the conductive pattern of PAD region without insulating barrier, PAD region is led
Electrograph shape is exposed, in the subsequent technique of array base palte, such as is carrying out organic electroluminescent LED (OLED) array
During wet etching (Wet Etch) technique of the anode (Anode) of substrate, the exposed conductive pattern of PAD region is easily etched liquid damage
Wound, so as to influence product yield.
The content of the invention
In view of this, the present invention provides a kind of mask plate, array base palte and preparation method thereof, avoids the conduction of PAD region
Figure is damaged, and improves the yield of array base palte.
In order to solve the above technical problems, the present invention provides a kind of mask plate, for forming the PAD region of covering array base palte
Conductive pattern at least part region protection figure, the mask plate includes：
Transmission region and light tight region, the transmission region or the light tight region correspond to the conductive pattern extremely
Small part region.
The present invention also provides a kind of preparation method of array base palte, and the array base palte includes viewing area and PAD region,
Including：
Form the conductive pattern of the PAD region；
Using above-mentioned mask plate, formation covers the protection figure at least part region of the conductive pattern；
After the default film layer figure of the viewing area is formed, the protection figure is removed.
Preferably, the protection figure covers the Zone Full of the conductive pattern, or, cover the conductive pattern
Subregion including side.
Preferably, the step of protection figure at least part region for forming the covering conductive pattern includes：
The first photoresist layer is coated on the conductive pattern；
Using the mask plate, first photoresist layer is exposed and developed, formed and cover the conductive pattern
At least part region the first photoetching offset plate figure, first photoetching offset plate figure is the protection figure.
Preferably, the default film layer figure is the figure of pixel electrode or the figure of anode.
Preferably, it is described after the default film layer figure of the viewing area is formed, remove the step of the protection figure
Suddenly include：
Form conductive film layer；
The second photoresist layer is coated on the conductive film layer；
Second photoresist layer is exposed and developed, forms the second photoetching offset plate figure；
Wet etching is carried out to the conductive film layer not by second photoetching offset plate figure covering, forms the default film layer figure；
First photoetching offset plate figure and the second photoetching offset plate figure are peeled off, expose the conductive pattern and described pre-
If film layer figure.
Preferably, the conductive pattern is Source and drain metal level figure.
Preferably, the Source and drain metal level figure uses Ti, Al and Ti three-decker.
Preferably, the preparation method of the array base palte specifically includes：
The active layer pattern positioned at the viewing area is formed on a underlay substrate；
Form the figure of the first gate insulation layer positioned at the viewing area and PAD region；
First grid metal layer image is formed, the first grid metal layer image includes：First positioned at the viewing area
Barrier metal layer figure and the first grid metal layer image positioned at the PAD region；
Form the figure of the second gate insulation layer positioned at the viewing area and PAD region；
The second gate metal layer image positioned at the viewing area is formed, the second gate metal layer image is located at described
The first grid metal layer image composition electric capacity of the viewing area；
Form the figure of interlayer dielectric layer；
The figure of Source and drain metal level is formed, the figure of the Source and drain metal level includes：Source and drain positioned at the viewing area
Metal layer image and the Source and drain metal level figure positioned at the PAD region, the Source and drain metal level figure positioned at the viewing area
Including source electrode and drain electrode, the source electrode and drain electrode pass through through the interlayer dielectric layer, second gate insulation layer and described the
The via of one gate insulation layer is connected with the figure of the active layer, and the Source and drain metal level figure positioned at the PAD region is by passing through
The via for wearing the interlayer dielectric layer and second gate insulation layer connects with the first grid metal layer image positioned at the PAD region
Connect, the Source and drain metal level figure positioned at the PAD region is the conductive pattern of the PAD region；
The figure of insulating barrier is formed, the figure of the insulating barrier does not cover the Source and drain metal level figure positioned at the PAD region
Shape；
Coat the first photoresist layer；
First photoresist layer is exposed and developed using the mask plate, covering is formed and is located at the PAD areas
First photoetching offset plate figure at least part region of the Source and drain metal level figure in domain；
Form the figure of the default film layer positioned at the viewing area；
Remove first photoetching offset plate figure.
The present invention also provides a kind of array base palte, is made using the preparation method of above-mentioned array base palte.
The above-mentioned technical proposal of the present invention has the beneficial effect that：
In the embodiment of the present invention, after the conductive pattern of PAD region is formed, formed and cover the conductive pattern at least
The protection figure of subregion, at least part region of conductive pattern is protected, so as to avoid forming viewing area
During default film layer figure, the etching liquid damage of default film layer figure is used to form, improves the yield of array base palte.
Brief description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below by institute in the description to the embodiment of the present invention
The accompanying drawing needed to use is briefly described, it should be apparent that, drawings in the following description are only some implementations of the present invention
Example, for those of ordinary skill in the art, without having to pay creative labor, can also be according to these accompanying drawings
Obtain other accompanying drawings.
Fig. 1 is the structural representation of the mask plate of one embodiment of the invention；
Fig. 2 is the structural representation of the mask plate of another embodiment of the present invention；
Fig. 3 is the schematic diagram of the preparation method of the array base palte of one embodiment of the invention；
Fig. 4 is the schematic diagram of the protection figure of one embodiment of the invention；
Fig. 5 is the schematic diagram of the protection figure of another embodiment of the present invention；
Fig. 6 is the schematic diagram of the preparation method of the protection figure of one embodiment of the invention；
Fig. 7 is the schematic diagram of the viewing area of the array base palte of one embodiment of the invention；
Fig. 8 is the schematic diagram of the PAD region of the array base palte shown in Fig. 7.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
Accompanying drawing, the technical scheme of the embodiment of the present invention is clearly and completely described.Obviously, described embodiment is this hair
Bright part of the embodiment, rather than whole embodiments.Based on described embodiments of the invention, ordinary skill
The every other embodiment that personnel are obtained, belongs to the scope of protection of the invention.
Fig. 1 is refer to, the embodiment of the present invention provides a kind of mask plate 10, and the mask plate 10 is used to form covering array base palte
PAD region conductive pattern at least part region protection figure, the mask plate 10 includes transmission region 11 and light tight
Region 12, at least part region of the corresponding conductive pattern of the light tight region 12.
In the embodiment of the present invention, it is preferable that the protection figure is formed using photoresist, and the photoresist is positive-tone photo
Glue, after positive photoresist is exposed, developer solution can be dissolved in.
In the embodiment of the present invention, the Zone Full of the corresponding conductive pattern of the light tight region 12, so as to be used for shape
Into the protection figure for the Zone Full for covering the conductive pattern, conductive pattern is comprehensively protected.
In some other embodiment of the present invention, the light tight region 12 can also correspond to the side of the conductive pattern
Face region, so as to the protection figure for forming the lateral side regions for covering the conductive pattern, the side of conductive pattern is carried out
Protection, or, the light tight region 12 can also correspond to lateral side regions and the portion of upper surface region of the conductive pattern, from
And it is used for the protection figure to form the lateral side regions for covering the conductive pattern and portion of upper surface region, to the side of conductive pattern
Face and portion of upper surface are protected.
Fig. 2 is refer to, the embodiment of the present invention provides a kind of mask plate 20, and the mask plate 20 is used to form covering array base palte
PAD region conductive pattern at least part region protection figure, the mask plate 20 includes transmission region 21 and light tight
Region 22, at least part region of the corresponding conductive pattern of the transmission region 21.
In the embodiment of the present invention, it is preferable that the protection figure is formed using photoresist, and the photoresist is negative photo
Glue, after negative photoresist is exposed, insoluble in developer solution.
In the embodiment of the present invention, the Zone Full of the corresponding conductive pattern of the transmission region 21, so as to for being formed
The protection figure of the Zone Full of the conductive pattern is covered, conductive pattern is comprehensively protected.
In some other embodiment of the present invention, the transmission region 21 can also correspond to the side of the conductive pattern
Region, so as to the protection figure for forming the lateral side regions for covering the conductive pattern, the side of conductive pattern is protected
Shield, or, the transmission region 21 can also correspond to lateral side regions and the portion of upper surface region of the conductive pattern, so as to use
In the protection figure for forming the lateral side regions for covering the conductive pattern and portion of upper surface region, side to conductive pattern and
Portion of upper surface is protected.
Fig. 3 is refer to, the embodiment of the present invention also provides a kind of preparation method of array base palte, and the array base palte includes aobvious
Show region and PAD region, the preparation method of the array base palte includes：
Step 301：Form the conductive pattern of the PAD region of array base palte；
Step 302：Using the mask plate of any of the above-described embodiment, at least part region for covering the conductive pattern is formed
Protection figure；
Step 303：After the default film layer figure of the viewing area is formed, the protection figure is removed.
In the embodiment of the present invention, after the conductive pattern of PAD region is formed, formed and cover the conductive pattern at least
The protection figure of subregion, at least part region of conductive pattern is protected, so as to avoid forming viewing area
During default film layer figure, the etching liquid damage of default film layer figure is used to form, improves the yield of array base palte.
Multiple conductive patterns are generally included in the embodiment of the present invention, on array base palte, the cross section of each conductive pattern leads to
Often is square or rectangular, it is of course also possible to be other figures, such as circle etc..
In some currently preferred embodiments of the present invention, Fig. 4 is refer to, protection figure 43 is an en-block construction, and covering is led
The Zone Full of electrograph shape 42, that is, figure 43 is protected to cover the upper surface and side of conductive pattern 42, so as to comprehensively to conductive pattern
Shape 42 is protected, and the protection graphics art for making an en-block construction requires low, and production cost is low.It 41 is lining that Fig. 4, which is,
Substrate.
In the other embodiment of the present invention, Fig. 5 is refer to, protection figure 43 can also be multiple, be covered each by
The lateral side regions of conductive pattern 42 and portion of upper surface region.It 41 is underlay substrate that Fig. 5, which is,.Protection figure 43 in the embodiment
It is sandwich construction suitable for conductive pattern 42, the conductive layer of top layer is not easy in the default film layer graphic procedure that is continued after its formation
In the embodiment that the conductive layer of the etching liquid etching used, intermediate layer or bottom is easily etched by the etching liquid.Due to leading
The lateral side regions of electrograph shape are protected, thus can be protected positioned at the conductive layer of intermediate layer or bottom.
In the embodiment of the present invention, it is preferable that the protection figure is made using Other substrate materials, so as to make
When, it need to only be exposed and developing process, save processing step and make raw material.
Certainly, in some other embodiment of the present invention, also it is not excluded for protecting figure to be made of other materials.
When the protection figure is made of Other substrate materials, above-mentioned formation covers at least part of the conductive pattern
The step of protection figure in region, can include：
Step 3021：The first photoresist layer is coated on the conductive pattern；
Step 3022：Using the mask plate in above-described embodiment, first photoresist layer is exposed and developed, shape
Into first photoetching offset plate figure at least part region for covering the conductive pattern, first photoetching offset plate figure is the protection
Figure.
In the embodiment of the present invention, first photoresist layer can be formed using positive photoresist, can also use negativity
Photoresist is formed, and when the type difference of the photoresist of use, is formed the mask plate that protection figure uses and is also differed.
Fig. 6 is refer to, Fig. 6 is the schematic diagram of the preparation method of the protection figure of one embodiment of the invention, and the present invention is implemented
In example, first in conductive pattern 42 to the first photoresist layer 43 ' of coating, then, using the mask plate 10 shown in Fig. 1, to described
First photoresist layer 43 ' is exposed and developed, and forms the first photoresist figure of the Zone Full for covering the conductive pattern 42
Shape, first photoetching offset plate figure are the protection figure 43 (refer to Fig. 4).
In the embodiment of the present invention, when array base palte is liquid crystal array substrate, formed pre- after the conductive pattern
If film layer figure can be the figure of pixel electrode.When array base palte is organic electroluminescent LED (OLED) array base palte
When, the default film layer figure formed after the conductive pattern can be the figure of anode.
It is described after the default film layer figure of the viewing area is formed in the embodiment of the present invention, remove the protection
The step of figure, can include：
Step 3031：Form conductive film layer；
Step 3032：The second photoresist layer is coated on the conductive film layer；
Step 3033：Second photoresist layer is exposed and developed, forms the second photoetching offset plate figure；
Step 3034：Wet etching is carried out to the conductive film layer not by second photoetching offset plate figure covering, formed described default
Film layer figure；
Step 3035：First photoetching offset plate figure and the second photoetching offset plate figure are peeled off, expose the conductive pattern
Shape and the default film layer figure.
That is, the photoresist used in the formation default film layer graphic procedure in Peeled display region is same
When, the photoresist for being used to protect the conductive pattern of the PAD region is peeled off, so as to save processing step, reduction is produced into
This.
In the embodiment of the present invention, it is preferable that the conductive pattern is Source and drain metal level figure, and in viewing area
Source electrode, drain electrode and data line is set with layer with material, can be formed by a patterning processes, so as to save technique step
Suddenly, mask plate quantity is reduced, reduces production cost.
In one embodiment of this invention, the Source and drain metal level figure can use Ti, Al and Ti three-decker.
In another embodiment, the array base palte is OLED array, and the Source and drain metal level figure uses Ti, Al
With Ti three-deckers, the etching liquid used in the graphic procedure for forming anode does not have influence on Ti substantially, but Al can be caused
Side etching phenomenon occurs for certain damage, the Al layers of conductive pattern, and in the technical process such as follow-up washing, the Ti on upper strata easily falls
Fall, this can not only influence binding (Bonding) effect of drive circuit board, and the Ti to drop also easily triggers short-circuit (short) existing
As.Thus, in the embodiment of the present invention, the protection figure of formation can only cover the lateral side regions of conductive pattern, or, covering is led
The lateral side regions of conductive pattern are included by the lateral side regions of electrograph shape and portion of upper surface region, avoid being located at Al layer quilts
Etching liquid damages.Certainly, the protection figure of formation can also be the Zone Full for covering conductive pattern, so as to realize more fully
Protection, and the protection figure of an entirety need to be only formed, technological requirement is low, it is easy to accomplish.
Fig. 7 and Fig. 8 are refer to, Fig. 7 is the schematic diagram of the PAD region of the array base palte of one embodiment of the invention, and Fig. 8 is figure
The schematic diagram of the viewing area of array base palte shown in 7, the preparation method of the array base palte include：
Step 701：One underlay substrate 51 is provided；
Underlay substrate 51 can be rigid substrate substrate, such as glass substrate or flexible substrate substrate, such as poly-
Imide resin (PI) substrate.
Step 702：Cushion 52 is formed on underlay substrate 51；
In some embodiments, cushion 52 can also omit.
Step 703：Active layer pattern 53 is formed on cushion 52；Active layer pattern 53 is located at the aobvious of the array base palte
Show region；
The active layer pattern 53 can use the materials such as low temperature polycrystalline silicon (LTPS) to be made.
Step 704：Form the figure 54 of the first gate insulation layer positioned at the viewing area and PAD region；
Step 705：First grid metal layer image is formed, the first grid metal layer image includes：Positioned at the viewing area
The first grid metal layer image 551 in domain and the first grid metal layer image 552 positioned at the PAD region；
Step 706：Form the figure 56 of the second gate insulation layer positioned at the viewing area and PAD region；
Step 707：Form the second gate metal layer image 57 positioned at the viewing area, the second gate metal layer image
57 form electric capacity with the first grid metal layer image 551 positioned at the viewing area；
Step 708：Form the figure 58 of interlayer dielectric layer；
Step 709：The figure of Source and drain metal level is formed, the figure of the Source and drain metal level includes：Positioned at the viewing area
The Source and drain metal level figure 591 in domain and the Source and drain metal level figure 592 positioned at the PAD region, positioned at the viewing area
Source and drain metal level figure 591 includes source electrode and drain electrode, and the source electrode and drain electrode are by through the interlayer dielectric layer, described second
The via of gate insulation layer and first gate insulation layer is connected with the figure 53 of the active layer, positioned at the source of the PAD region
Leakage metal layer image 592 is by through the via of the interlayer dielectric layer and second gate insulation layer and being located at the PAD areas
The first grid metal layer image 552 in domain connects, and the Source and drain metal level figure 592 positioned at the PAD region is the PAD region
Conductive pattern；
Step 710：The figure 510 of insulating barrier is formed, the figure 510 of the insulating barrier is not covered positioned at the PAD region
Source and drain metal level figure 592；
Step 711：Coat the first photoresist layer；First photoresist layer is exposed and shown using a mask plate
Shadow, form first photoetching offset plate figure 511 of the covering positioned at the Zone Full of the Source and drain metal level figure 592 of the PAD region；
Step 712：Form conductive film layer；The second photoresist layer is coated on the conductive film layer；To second photoetching
Glue-line is exposed and developed, and forms the second photoetching offset plate figure 512；To not led by the covering of the second photoetching offset plate figure 512 '
Electrolemma layer carries out wet etching, forms the figure 513 of anode；
Step 713：The photoetching offset plate figure 512 of first photoetching offset plate figure 511 and second is peeled off, exposes described lead
Electrograph shape and the default film layer figure.
In the embodiment of the present invention, after the conductive pattern of PAD region is formed, the whole for covering the conductive pattern is formed
First photoetching offset plate figure in region, is protected to the Zone Full of conductive pattern, so as to avoid forming the sun of viewing area
During the figure of pole, the etching liquid damage of the figure of anode is used to form, improves the yield of array base palte.Also,
After having made the figure of anode, by the first photoetching offset plate figure and make the second photoresist for using of figure of anode while shell
From so that conductive pattern is exposed outside, can normally be connected with the lead of the drive circuit board of outside.
The embodiment of the present invention also provides a kind of array base palte, using the making side of the array base palte in any of the above-described embodiment
Method is made.
Array base palte in the embodiment of the present invention, because in manufacturing process, the conductive pattern of PAD region is protected by protective layer
Shield, thus, it is not easy to be damaged, pattern (Profile) greatly improves the yield of array base palte than more complete.
The array base palte can be liquid crystal array substrate or OLED array.
Unless otherwise defined, the technical term or scientific terminology used in the present invention is should be in art of the present invention
The ordinary meaning that personage with general technical ability is understood." first ", " second " and the similar word used in the present invention
Any order, quantity or importance are not offered as, and is used only to distinguish different parts.Equally, "one" or
The similar word such as " one " does not indicate that quantity limits yet, but represents to exist at least one." connection " or " connected " etc. are similar
Word is not limited to physics or mechanical connection, but can include electrical connection, either directly or between
Connect." on ", " under ", "left", "right" etc. are only used for representing relative position relation, when the absolute position for being described object changes
Afterwards, then the relative position relation also correspondingly changes.
Described above is the preferred embodiment of the present invention, it is noted that for those skilled in the art
For, on the premise of principle of the present invention is not departed from, some improvements and modifications can also be made, these improvements and modifications
It should be regarded as protection scope of the present invention.
Claims (10)
1. a kind of mask plate, it is characterised in that at least part for the conductive pattern for forming the PAD region for covering array base palte
The protection figure in region, the mask plate include：
Transmission region and light tight region, the transmission region or the light tight region correspond at least portion of the conductive pattern
Subregion.
2. a kind of preparation method of array base palte, the array base palte includes viewing area and PAD region, it is characterised in that bag
Include：
Form the conductive pattern of the PAD region；
Using mask plate as claimed in claim 1, formation covers the protection figure at least part region of the conductive pattern；
After the default film layer figure of the viewing area is formed, the protection figure is removed.
3. the preparation method of array base palte according to claim 2, it is characterised in that led described in the protection figure covering
The Zone Full of electrograph shape, or, cover the subregion for including side of the conductive pattern.
4. the preparation method of array base palte according to claim 2, it is characterised in that described formed covers the conductive pattern
The step of protection figure at least part region of shape, includes：
The first photoresist layer is coated on the conductive pattern；
Using the mask plate, first photoresist layer is exposed and developed, formed and cover the conductive pattern extremely
First photoetching offset plate figure in small part region, first photoetching offset plate figure are the protection figure.
5. the preparation method of array base palte according to claim 4, it is characterised in that the default film layer figure is pixel
The figure of electrode or the figure of anode.
6. the preparation method of array base palte according to claim 5, it is characterised in that described to form the viewing area
Default film layer figure after, remove it is described protection figure the step of include：
Form conductive film layer；
The second photoresist layer is coated on the conductive film layer；
Second photoresist layer is exposed and developed, forms the second photoetching offset plate figure；
Wet etching is carried out to the conductive film layer not by second photoetching offset plate figure covering, forms the default film layer figure；
First photoetching offset plate figure and the second photoetching offset plate figure are peeled off, expose the conductive pattern and the default film
Layer pattern.
7. the preparation method of array base palte according to claim 3, it is characterised in that the conductive pattern is source and drain metal
Layer pattern.
8. the preparation method of array base palte according to claim 7, it is characterised in that the Source and drain metal level figure uses
Ti, Al and Ti three-decker.
9. the preparation method of array base palte according to claim 7, it is characterised in that specifically include：
The active layer pattern positioned at the viewing area is formed on a underlay substrate；
Form the figure of the first gate insulation layer positioned at the viewing area and PAD region；
First grid metal layer image is formed, the first grid metal layer image includes：First grid gold positioned at the viewing area
Belong to layer pattern and the first grid metal layer image positioned at the PAD region；
Form the figure of the second gate insulation layer positioned at the viewing area and PAD region；
The second gate metal layer image positioned at the viewing area is formed, the second gate metal layer image is with described positioned at described
The first grid metal layer image composition electric capacity of viewing area；
Form the figure of interlayer dielectric layer；
The figure of Source and drain metal level is formed, the figure of the Source and drain metal level includes：Source and drain metal positioned at the viewing area
Layer pattern and the Source and drain metal level figure positioned at the PAD region, the Source and drain metal level figure positioned at the viewing area include
Source electrode and drain electrode, the source electrode and drain electrode are by through the interlayer dielectric layer, second gate insulation layer and the first grid
The via of insulating barrier is connected with the figure of the active layer, and the Source and drain metal level figure positioned at the PAD region passes through through institute
The via for stating interlayer dielectric layer and second gate insulation layer is connected with the first grid metal layer image positioned at the PAD region,
Source and drain metal level figure positioned at the PAD region is the conductive pattern of the PAD region；
The figure of insulating barrier is formed, the figure of the insulating barrier does not cover the Source and drain metal level figure positioned at the PAD region；
Coat the first photoresist layer；
First photoresist layer is exposed and developed using the mask plate, forms covering positioned at the PAD region
First photoetching offset plate figure at least part region of Source and drain metal level figure；
Form the figure of the default film layer positioned at the viewing area；
Remove first photoetching offset plate figure.
10. a kind of array base palte, it is characterised in that using the making side of the array base palte as described in claim any one of 1-9
Method is made.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710801200.0A CN107579040B (en) | 2017-09-07 | 2017-09-07 | Mask, array substrate and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710801200.0A CN107579040B (en) | 2017-09-07 | 2017-09-07 | Mask, array substrate and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107579040A true CN107579040A (en) | 2018-01-12 |
| CN107579040B CN107579040B (en) | 2020-04-21 |
Family
ID=61031487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710801200.0A Active CN107579040B (en) | 2017-09-07 | 2017-09-07 | Mask, array substrate and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107579040B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108550588A (en) * | 2018-06-08 | 2018-09-18 | 京东方科技集团股份有限公司 | The manufacturing method and display device of display panel, display panel |
| CN109216582A (en) * | 2018-08-27 | 2019-01-15 | 京东方科技集团股份有限公司 | A kind of display panel and preparation method thereof and display device |
| CN109585459A (en) * | 2018-12-05 | 2019-04-05 | 惠科股份有限公司 | Preparation method of array substrate, display panel and display device |
| CN110676217A (en) * | 2019-10-09 | 2020-01-10 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102109713A (en) * | 2009-12-23 | 2011-06-29 | 北京京东方光电科技有限公司 | Liquid crystal display (LCD) panel, array substrate and preparation method of array substrate |
| CN102769040A (en) * | 2012-07-25 | 2012-11-07 | 京东方科技集团股份有限公司 | Thin-film transistor, array substrate, array substrate manufacturing method and display device |
| CN103545378A (en) * | 2013-11-05 | 2014-01-29 | 京东方科技集团股份有限公司 | Oxide thin film transistor, manufacturing method thereof, array substrate and display device |
| CN104393001A (en) * | 2014-10-24 | 2015-03-04 | 京东方科技集团股份有限公司 | Thin film transistor array substrate, manufacturing method thereof, and display device |
| CN104635416A (en) * | 2015-02-06 | 2015-05-20 | 合肥京东方光电科技有限公司 | Manufacturing method of mask plate and array substrate |
| CN105810690A (en) * | 2016-04-01 | 2016-07-27 | 京东方科技集团股份有限公司 | Display substrate, fabrication method thereof and display device |
| CN106298806A (en) * | 2016-09-06 | 2017-01-04 | 京东方科技集团股份有限公司 | A kind of total reflection array base palte and preparation method thereof and display device |
-
2017
- 2017-09-07 CN CN201710801200.0A patent/CN107579040B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102109713A (en) * | 2009-12-23 | 2011-06-29 | 北京京东方光电科技有限公司 | Liquid crystal display (LCD) panel, array substrate and preparation method of array substrate |
| CN102769040A (en) * | 2012-07-25 | 2012-11-07 | 京东方科技集团股份有限公司 | Thin-film transistor, array substrate, array substrate manufacturing method and display device |
| CN103545378A (en) * | 2013-11-05 | 2014-01-29 | 京东方科技集团股份有限公司 | Oxide thin film transistor, manufacturing method thereof, array substrate and display device |
| CN104393001A (en) * | 2014-10-24 | 2015-03-04 | 京东方科技集团股份有限公司 | Thin film transistor array substrate, manufacturing method thereof, and display device |
| CN104635416A (en) * | 2015-02-06 | 2015-05-20 | 合肥京东方光电科技有限公司 | Manufacturing method of mask plate and array substrate |
| CN105810690A (en) * | 2016-04-01 | 2016-07-27 | 京东方科技集团股份有限公司 | Display substrate, fabrication method thereof and display device |
| CN106298806A (en) * | 2016-09-06 | 2017-01-04 | 京东方科技集团股份有限公司 | A kind of total reflection array base palte and preparation method thereof and display device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108550588A (en) * | 2018-06-08 | 2018-09-18 | 京东方科技集团股份有限公司 | The manufacturing method and display device of display panel, display panel |
| US11562973B2 (en) | 2018-06-08 | 2023-01-24 | Boe Technology Group Co., Ltd. | Display panel, manufacturing method of display panel, and display device |
| CN109216582A (en) * | 2018-08-27 | 2019-01-15 | 京东方科技集团股份有限公司 | A kind of display panel and preparation method thereof and display device |
| CN109585459A (en) * | 2018-12-05 | 2019-04-05 | 惠科股份有限公司 | Preparation method of array substrate, display panel and display device |
| US11289516B2 (en) | 2018-12-05 | 2022-03-29 | HKC Corporation Limited | Array substrate fabrication method, array substrate, and display panel |
| CN110676217A (en) * | 2019-10-09 | 2020-01-10 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
| WO2021068805A1 (en) * | 2019-10-09 | 2021-04-15 | 京东方科技集团股份有限公司 | Display panel, manufacturing method therefor, and display device |
| CN110676217B (en) * | 2019-10-09 | 2021-12-10 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107579040B (en) | 2020-04-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20220310693A1 (en) | Micro light emitting diode display substrate and manufacturing method thereof | |
| CN107579040A (en) | A kind of mask plate, array base palte and preparation method thereof | |
| CN104360557B (en) | Array substrate, manufacturing method thereof and display device | |
| CN100388104C (en) | Thin film transistor array substrate and fabricating method thereof | |
| CN105159515B (en) | Touch-control structure and preparation method thereof, touch base plate and display device | |
| CN105161519B (en) | Thin film transistor (TFT) and preparation method, array base palte and preparation method and display device | |
| CN102593126B (en) | Panel and manufacturing method thereof | |
| CN105161499B (en) | A kind of display base plate and preparation method thereof and display device | |
| CN108336100A (en) | A kind of array substrate and preparation method thereof, display panel, display device | |
| CN105068373A (en) | Manufacturing method of TFT (Thin Film Transistor) substrate structure | |
| CN104157613B (en) | A kind of preparation method of array base palte | |
| US20170285430A1 (en) | Array Substrate and Manufacturing Method Thereof, Display Panel and Display Device | |
| CN107452808A (en) | Thin film transistor (TFT) and preparation method thereof, array base palte and display device | |
| CN109616496B (en) | Manufacturing method of OLED touch display screen | |
| CN104793416B (en) | A kind of array base palte and preparation method thereof and display panel | |
| CN110400810A (en) | Display base plate and preparation method thereof and display device | |
| WO2016090886A1 (en) | Array substrate and manufacturing method therefor, and display panel | |
| CN108133932A (en) | Array substrate and preparation method thereof, display panel | |
| CN102468243B (en) | TFT (Thin Film Transistor) array substrate, manufacturing method and liquid crystal display device | |
| US9716117B2 (en) | Method for producing a via, a method for producing an array substrate, an array substrate, and a display device | |
| CN102832226A (en) | Active element array substrate and manufacturing method thereof | |
| CN107195635A (en) | Thin-film transistor array base-plate and preparation method thereof | |
| CN105529274B (en) | Production method, array substrate and the display device of thin film transistor (TFT) | |
| CN111211137B (en) | Display panel and display device | |
| CN107359138A (en) | A kind of metal wire, the preparation method of array base palte and array base palte |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |