CN107566085A - A kind of bit error code method of testing and system based on FC buses - Google Patents
A kind of bit error code method of testing and system based on FC buses Download PDFInfo
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- CN107566085A CN107566085A CN201710783835.2A CN201710783835A CN107566085A CN 107566085 A CN107566085 A CN 107566085A CN 201710783835 A CN201710783835 A CN 201710783835A CN 107566085 A CN107566085 A CN 107566085A
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Abstract
The present invention provides a kind of bit error code method of testing and system based on FC buses, and wherein system includes test data generation module, bit error code test module, data transmission blocks and data reception module interconnection and mutually communication；Wherein module occurs for test data, for test data to be deposited in the payload section of FC data frames, judges whether to need scrambler according to current test rate；Bit error code test module, judge whether to need to descramble according to test rate, then can determine whether synchronization, whether have bit error code, and calculate bit error rate；Data transmission blocks, the FC data frames that test data to that module generation occur are transmitted；Data reception module, for carrying out receiving capture and storage to data frame.Using such scheme, it is possible to achieve reach the bit error code test that various speed are realized on the FC bus test instruments of more than 8.5Gb/s and compatible low rate in a flank speed.
Description
Technical field
The invention belongs to FC bus test technical fields, more particularly to a kind of bit error code test based on FC buses
Method and system.
Background technology
With the development of FC buses, its speed has developed from earliest 1.0625Gb/s, 2.125Gb/s, 4.25Gb/s
To 8.5Gb/s even more highs.Although FC buses have higher stability, but still it cannot be guaranteed that not going out during bus transfer
Existing error code.Bit error code test can actively insert bit error code in data transmission procedure, and ratio is produced during analogue transmission
The situation of special error code, with this judge bus transmission performance and system under test (SUT) to there is the response disposal ability of bit error code.
The principle of error code testing is that sender produces test data, is loaded into standard testing frame, is sent to system under test (SUT), system under test (SUT)
The data received are decoded, test data is taken out, is contrasted with the normal data to prestore by bit, are counted after synchronous
Go out two groups of different bit numbers of data, draw the bit error rate.The existing FC bus test instrument products for supporting bit error code test
Speed is mostly 4.25Gb/s and following, and also no highest test rate can reach 8.5Gb/s and backward compatible a variety of speed,
The FC bus test instrument products that bit error code can also be supported to test simultaneously.
Therefore, the prior art is defective, it is necessary to improve.
The content of the invention
The technical problems to be solved by the invention are in view of the shortcomings of the prior art, there is provided a kind of bit based on FC buses
Error-code testing method and system.
Technical scheme is as follows：
A kind of bit error code test system based on FC buses, wherein, including module occurs for test data, bit error code is surveyed
Die trial block, data transmission blocks and data reception module are connected with each other and mutually communication；Wherein module occurs for test data, is used for
Test data is deposited in the payload section of FC data frames, judge whether to need scrambler according to current test rate；Bit error code
Test module, judge whether to need to descramble according to test rate, then can determine whether synchronization, whether have bit error code, and count
Calculate bit error rate；Data transmission blocks, the FC data frames that test data to that module generation occur are transmitted；Data receiver
Module, for carrying out receiving capture and storage to data frame.
Furthermore, module occurs for the test data, and the FC data frame frame lengths of FC consensus standards are met for producing
Degree can be set, and test data includes pseudo-random binary sequence, full 0, complete 1 or any customized data, and test data is deposited
It is put in the payload section of FC data frames, judges whether to need scrambler according to current test rate.
Furthermore, the resolution chart of the bit error code test module is identical with test data generation module, comprising
Pseudo-random binary sequence, full 0, complete 1 or any customized data.
Furthermore, the transmission process of the data transmission blocks will meet FC agreements.
Furthermore, the data reception module：It is additionally operable to carry out FC protocol-decodings to the data of capture.
A kind of method of testing of the bit error code test system based on FC buses, comprises the following steps：
Step 101：Test data occurs module and produces test data, and test data is deposited in into FC data
The payload section of frame, while bit error code test module sets identical test data as pre-stored data；
Step 102：Test data occurs module and current test rate is judged；
Step 103：If speed be 8.5Gb/s and more than, into step 104；If speed is 4.25Gb/s
And it is following, then without scrambler, into step 105；
Step 104：Data frame is subjected to scrambler；
Step 105：Then data frame is sent according to FC agreements by data transmission blocks；Now by
Examining system should be arranged to direct mode operation, that is, the data for needing to receive are then forwarded to bit error code test
Module；
Step 106：Data reception module captures to data frame；
Step 107：Bit error code test module is judged current test rate；
Step 108：If speed be 8.5Gb/s and more than, into step 109；If speed is 4.25Gb/s and following,
Into step 110；
Step 109：The data frame of capture is descrambled；
Step 110：Data reception module is decoded according to FC agreements to data frame, and frame head is peeled off, by payload
Area's data are taken out；
Step 111：Bit error code test module sets synchronous thresholding, by the data of the payload section separated in step 110
Contrasted with the pre-stored data in step 101, judge whether synchronization, if synchronous unsuccessful, continue to judge, until synchronization into
Untill work(；If synchronous success, into step 112；
Step 112：After synchronously success, by the data of payload section and pre-stored data by every bit one by one compared with,
Count bit error code number；
Step 113：Calculate bit error rate, the number of the bit error code for being calculated as counting of bit error rate divided by
The bit total number of payload section data in the data frame received after synchronous.
Using such scheme, it is possible to achieve the FC for reaching more than 8.5Gb/s and compatible low rate in a flank speed is total
The bit error code test of various speed is realized on line tester.
Brief description of the drawings
Fig. 1 is one of embodiments of the invention flow chart.
Fig. 2 is the two of embodiments of the invention flow chart.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
Embodiment 1
As shown in figure 1,
Sending module of the present invention is deposited in test data in the payload section of FC standard frames, is carried out according to current test rate
Judge, if 8.5Gb/s and more than, then to send data frame carry out scrambler, otherwise directly transmit data frame；Receiving module is by phase
Same test data is judged, if 8.5Gb/s and the above then to receiving as pre-stored data after receiving data according to speed
Data descrambled.
The present invention proposes a kind of bit error code test system based on FC buses, and it comprises at least following functional module：
1) module occurs for test data：The FC data frames frame length that generation meets FC consensus standards can set (payload section length
Can not be that 0), test data includes pseudo-random binary sequence, full 0, complete 1 or any customized data, by test data
Deposit in the payload section of FC data frames, judge whether to need scrambler according to current test rate.
2) bit error code test module：This module judges whether to need to descramble according to test rate, then can determine whether
Synchronously, whether there is bit error code, and calculate bit error rate.The resolution chart of bit error code test module is sent out with test data
Raw module is identical, also comprising pseudo-random binary sequence, full 0, complete 1 or any customized data, is surveyed by bit error code
After trying resume module, bit error rate can be calculated.
3) data transmission blocks：The FC data frames that test data to that module generation occur are transmitted, and test rate can be set
Put, transmission process will meet FC agreements.
4) data reception module：For carrying out receiving capture and storage to data frame, FC can be carried out to the data of capture
Protocol-decoding.
Bit error code method of testing proposed by the present invention based on FC buses, such as Fig. 1 and as shown in Figure 2：
Step 101：Test data occurs module and produces test data, and test data is deposited in the payload of FC data frames
Area, while bit error code test module sets identical test data as pre-stored data；
Step 102：Test data occurs module and current test rate is judged；
Step 103：If speed be 8.5Gb/s and more than, into step 104；If speed is 4.25Gb/s and following,
Without scrambler, into step 105；
Step 104：Data frame is subjected to scrambler；
Step 105：Then data frame is sent according to FC agreements by data transmission blocks；Now system under test (SUT) should be set
Direct mode operation is set to, that is, the data for needing to receive are then forwarded to bit error code test module；
Step 106：Data reception module captures to data frame；
Step 107：Bit error code test module is judged current test rate；
Step 108：If speed be 8.5Gb/s and more than, into step 109；If speed is 4.25Gb/s and following,
Into step 110；
Step 109：The data frame of capture is descrambled；
Step 110：Data reception module is decoded according to FC agreements to data frame, and frame head is peeled off, by payload
Area's data are taken out；
Step 111：Bit error code test module sets synchronous thresholding, by the data of the payload section separated in step 110
Contrasted with the pre-stored data in step 101, judge whether synchronization, if synchronous unsuccessful, continue to judge, until synchronization into
Untill work(；If synchronous success, into step 112；
Step 112：After synchronously success, by the data of payload section and pre-stored data by every bit one by one compared with,
Count bit error code number；
Step 113：Calculate bit error rate, the number of the bit error code for being calculated as counting of bit error rate divided by
The bit total number of payload section data in the data frame received after synchronous.
Using such scheme, it is possible to achieve the FC for reaching more than 8.5Gb/s and compatible low rate in a flank speed is total
The bit error code test of various speed is realized on line tester.
It should be appreciated that for those of ordinary skills, can according to the above description be improved or converted,
And all these modifications and variations should all belong to the protection domain of appended claims of the present invention.
Claims (6)
1. a kind of bit error code test system based on FC buses, it is characterised in that module occurs including test data, bit misses
Code test module, data transmission blocks and data reception module are connected with each other and mutually communication；Wherein module occurs for test data,
For test data to be deposited in the payload section of FC data frames, judge whether to need scrambler according to current test rate；Bit
Error code testing module, judge whether to need to descramble according to test rate, then can determine whether synchronization, whether have bit error code,
And calculate bit error rate；Data transmission blocks, the FC data frames that test data to that module generation occur are transmitted；Data
Receiving module, for carrying out receiving capture and storage to data frame.
2. the bit error code test system based on FC buses as claimed in claim 1, it is characterised in that the test data hair
Raw module, the FC data frames frame length of FC consensus standards is met for producing to be set, and test data includes pseudo-random binary sequence
Row, full 0, complete 1 or any customized data, test data are deposited in the payload section of FC data frames, are surveyed according to current
Examination speed judges whether to need scrambler.
3. the bit error code test system based on FC buses as claimed in claim 1, it is characterised in that the bit error code is surveyed
It is identical that module occurs for the resolution chart of die trial block and test data, comprising pseudo-random binary sequence, full 0, complete 1 or it is any from
The data of definition.
4. the bit error code test system based on FC buses as claimed in claim 1, it is characterised in that the data send mould
The transmission process of block will meet FC agreements.
5. the bit error code test system based on FC buses as claimed in claim 1, it is characterised in that the data reception
Block：It is additionally operable to carry out FC protocol-decodings to the data of capture.
A kind of 6. method of testing of the bit error code test system based on FC buses as claimed in claim 1, it is characterised in that
Comprise the following steps：
Step 101：Test data occurs module and produces test data, test data is deposited in the payload section of FC data frames, together
When bit error code test module identical test data is set as pre-stored data；
Step 102：Test data occurs module and current test rate is judged；
Step 103：If speed be 8.5Gb/s and more than, into step 104；If speed is 4.25Gb/s and following, do not enter
Row scrambler, into step 105；
Step 104：Data frame is subjected to scrambler；
Step 105：Then data frame is sent according to FC agreements by data transmission blocks；Now system under test (SUT) should be arranged to
Direct mode operation, that is, the data for needing to receive are then forwarded to bit error code test module；
Step 106：Data reception module captures to data frame；
Step 107：Bit error code test module is judged current test rate；
Step 108：If speed be 8.5Gb/s and more than, into step 109；If speed is 4.25Gb/s and following, enter
Step 110；
Step 109：The data frame of capture is descrambled；
Step 110：Data reception module is decoded according to FC agreements to data frame, and frame head is peeled off, by payload section number
According to taking-up；
Step 111：Bit error code test module sets synchronous thresholding, by the data and step of the payload section separated in step 110
Pre-stored data in rapid 101 is contrasted, and judges whether synchronization, if synchronous unsuccessful, continues to judge, until being successfully synchronously
Only；If synchronous success, into step 112；
Step 112：After synchronously success, by the data of payload section and pre-stored data by every bit one by one compared with, count
Go out bit error code number；
Step 113：Calculate bit error rate, the number of the bit error code for being calculated as counting of bit error rate divided by synchronization
The bit total number of payload section data in the data frame received afterwards.
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| CN108900244A (en) * | 2018-06-27 | 2018-11-27 | 电子科技大学 | A kind of FC optical interface data and its method of related data monitoring and test |
| CN109787723A (en) * | 2019-01-04 | 2019-05-21 | 武汉邮电科学研究院有限公司 | A kind of detection method of the bit error rate, detection system and high order modulation communication system |
| CN111722832A (en) * | 2020-06-19 | 2020-09-29 | 西安微电子技术研究所 | Satellite load data simulation source testing method and device |
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Application publication date: 20180109 |