CN107527947B - Semiconductor device, manufacturing method thereof and electronic device - Google Patents
Semiconductor device, manufacturing method thereof and electronic device Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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- General Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, wherein the semiconductor device comprises: the semiconductor device comprises a semiconductor substrate, a main grid electrode, a channel, a source electrode, a drain electrode, n sub-grid electrodes and a control circuit, wherein the main grid electrode is positioned on the semiconductor substrate, the channel is positioned below the main grid electrode, the source electrode and the drain electrode are positioned on two sides of the main grid electrode and the channel, the n sub-grid electrodes are arranged between the source electrode and the drain electrode, the main grid electrode and the n sub-grid electrodes are separated from each other, different voltages can be independently applied to the main grid electrode and the n sub-grid electrodes so as to adjust the voltage applied to the channel, and n is. The semiconductor device can accurately control the saturation current and is convenient to debug. The electronic device has similar advantages.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method thereof and an electronic device.
Background
With the development of semiconductor technology and the demand of the market, there are various products that are implemented by using integrated circuit manufacturing technology. For many new chip (tape out) products, such as analog high voltage devices, accurate saturated source-drain current (Idsat) control is necessary because obtaining accurate saturated source-drain current is very useful for fast response during the initial debug phase. However, it is generally very difficult to obtain accurate saturated source-drain current after the first time the device is shipped, which is very disadvantageous for early device debugging.
Therefore, it is desirable to provide a new semiconductor device and a method for fabricating the same to at least partially solve the above problems.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
Aiming at the defects of the prior art, the invention provides a semiconductor device and a manufacturing method thereof, which can realize accurate control on saturation current.
An aspect of the present invention provides a semiconductor device, including: a semiconductor device, comprising: the semiconductor device comprises a semiconductor substrate, a main grid electrode, a channel, a source electrode, a drain electrode, n sub-grid electrodes and a control circuit, wherein the main grid electrode is positioned on the semiconductor substrate, the channel is positioned below the main grid electrode, the source electrode and the drain electrode are positioned on two sides of the main grid electrode and the channel, the n sub-grid electrodes are arranged between the source electrode and the drain electrode, the main grid electrode and the n sub-grid electrodes are separated from each other, different voltages can be independently applied to the main grid electrode and the n sub-grid electrodes so as to adjust the voltage applied to the channel, and n is.
Further, each of the sub-gates is disposed in a direction of a source and a drain.
Further, the n sub-gates are arranged in parallel.
Further, the main gate includes n openings, and one sub-gate is disposed in each of the openings.
Further, the main gate includes n +1 fingers, and one sub-gate is disposed between two adjacent fingers.
Further, the main gate and the n sub-gates are arranged in parallel.
Further, the main gate is disposed over a middle region of the channel, and the sub-gates are disposed at both sides of the main gate.
Furthermore, n is an even number, and the n sub-gates are symmetrically distributed on two sides of the main gate.
Further, the semiconductor device is an NMOS device or a PMOS device.
The semiconductor device provided by the invention comprises a main grid and n sub-grids which are separated from each other, different voltages can be applied to a channel by controlling the number of the grids with the voltages applied to the main grid 101 and the n sub-grids, in the semiconductor device provided by the embodiment, the grids in n +1 are connected, so that the voltages applied to the channel have a very large regulation range, and different saturation currents can be obtained by applying different voltages in communication.
Another aspect of the present invention provides a method for manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate, and forming a grid material layer and a source electrode and a drain electrode which are positioned at two sides of the grid material layer on the semiconductor substrate; patterning the grid electrode material layer to form a main grid electrode and n sub grid electrodes separated from the main grid electrode; and forming contacts of the main gate, the n sub-gates, the source and the drain, wherein the main gate and the n sub-gates can be respectively applied with different voltages to adjust the voltage applied to the channel, and n is an integer greater than or equal to 1.
Further, each of the sub-gates is disposed in a direction of a source and a drain.
Further, the n sub-gates are arranged in parallel.
Further, the main gate includes n openings, and one sub-gate is disposed in each of the openings.
Further, the main gate includes n +1 fingers, and one sub-gate is disposed between two adjacent fingers.
Further, the main gate and the n sub-gates are arranged in parallel.
Further, the main gate is disposed over a middle region of the channel, and the sub-gates are disposed at both sides of the main gate.
Furthermore, n is an even number, and the n sub-gates are symmetrically distributed on two sides of the main gate.
According to the manufacturing method of the semiconductor, the main grid and the n sub-grids separated from the main grid are formed on the semiconductor substrate, so that n +1 grid connection modes are obtained, and the voltage applied to a channel can be adjusted through different grid connection modes, so that the saturation current of a device can be accurately controlled.
A further aspect of the invention provides an electronic device comprising a semiconductor device as described above and an electronic component connected to the semiconductor device.
The electronic device provided by the invention has similar advantages due to the semiconductor device.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1A is a schematic layout of a semiconductor device according to an embodiment of the present invention;
FIG. 1B is a cross-sectional view of the semiconductor device shown in FIG. 1A taken along the A-A direction;
FIG. 1C is a cross-sectional view of the semiconductor device shown in FIG. 1A taken along the direction B-B;
FIG. 2A is a schematic layout of a semiconductor device according to another embodiment of the present invention;
fig. 2B is a cross-sectional view of the semiconductor device shown in fig. 2A taken along a-a direction;
fig. 2C is a cross-sectional view of the semiconductor device shown in fig. 2A taken along the direction B-B;
FIG. 3A is a schematic layout of a semiconductor device according to another embodiment of the present invention;
fig. 3B is a cross-sectional view of the semiconductor device shown in fig. 3A taken along a-a direction;
fig. 3C is a cross-sectional view of the semiconductor device shown in fig. 3A taken along the direction B-B;
FIG. 4 is a flow chart illustrating steps in a method of fabricating a semiconductor device according to an embodiment of the present invention;
fig. 5 shows a schematic view of an electronic device according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity to indicate like elements throughout.
It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Example one
FIG. 1A is a schematic layout of a semiconductor device according to an embodiment of the present invention; FIG. 1B is a cross-sectional view of the semiconductor device shown in FIG. 1A taken along the A-A direction; fig. 1C is a cross-sectional view of the semiconductor device shown in fig. 1A taken along the direction B-B, and a detailed description will be given below of the semiconductor device according to an embodiment of the present invention with reference to fig. 1A to 1C.
As shown in fig. 1A to 1C, the semiconductor device proposed in the present embodiment includes: a semiconductor substrate 100, a main gate 101 on the semiconductor substrate 100 and a channel under the main gate 101, and a source S and a drain D on both sides of the main gate 101 and the channel, n sub-gates 1021, 1022, 1023 … 102n are further disposed between the source S and the drain D, n is an integer greater than or equal to 1, the main gate 101 and the n sub-gates are separated from each other, a main gate contact 101A is provided on the main gate 101, for applying a voltage to the main gate 101, sub-gate contacts 1021A, 1022A, 1023A … 102nA are respectively arranged on the n sub-gates 1021, 1022, 1023 … 102n, and are used for respectively applying voltages to the n sub-gates, a source contact 103A and a drain contact 104A are provided at the source S and the drain D, respectively, to apply voltages to the source S and the drain D, respectively.
The semiconductor substrate 100 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). In the present embodiment, the constituent material of the semiconductor substrate 100 is monocrystalline silicon.
The source S and the drain D are doped differently according to the type of the semiconductor device, for example, when the semiconductor device is an NMOS device, the source S and the drain D are doped N-type, for example, phosphorus; when the semiconductor device is a PMOS device, the source S and drain D are P-type doped, for example, with boron. The specific dopant amount or concentration may be determined according to the design requirements of the device, and the embodiment is not particularly limited.
The main gate 101 and the n sub-gates may be made of a common gate material, such as a polysilicon material. In this embodiment, the main gate 101 and the n sub-gates, and the n sub-gates are separated from each other, i.e. electrically isolated, so that the main gate 101 and the n sub-gates can each apply different voltages independently, which is equivalent to adding n independent sub-gates on the semiconductor substrate, and the voltage applied to the channel can be adjusted by the main gate 101 and the n sub-gates, and the voltage applied to the channel has a larger adjustment range. For example, a voltage of 10V is applied to the main gate, a voltage of 1V is applied to each sub-gate, which is equivalent to a voltage of 10+ nV applied to the channel, and different voltages can be applied to the channel by controlling the number of gates to which voltages are applied in the main gate 101 and the n sub-gates.
In the present embodiment, in order to facilitate the control of the saturation current, the n sub-gates 1021, 1022, 1023 … 102n are preferably arranged in the direction of the channel or in the source-drain direction (i.e., the direction indicated by the arrow in fig. 1C) as shown in fig. 1C. Further, preferably, the n sub-gates 1021, 1022, 1023 … 102n are arranged in parallel along the source-drain direction.
Further, as shown in fig. 1A and 1B, in the present embodiment, the main gate 101 is provided over the entire channel region, and in the main gate 101, n openings are provided, one sub-gate 102n being provided in each opening.
It will be appreciated that when the sub-gate is not used to apply a voltage to the channel, the sub-gate is biased at a corresponding voltage state (off-state), for example at ground for NMOS devices and at operating Voltage (VDD) for PMOS devices.
The semiconductor device of the present embodiment can achieve accurate saturation current control.
Example two
FIG. 2A is a schematic layout of a semiconductor device according to another embodiment of the present invention; fig. 2B is a cross-sectional view of the semiconductor device shown in fig. 2A taken along a-a direction; fig. 2C is a cross-sectional view of the semiconductor device shown in fig. 2A taken along the direction B-B, and the semiconductor device according to an embodiment of the present invention will be described in detail with reference to fig. 2A to 2C.
As shown in fig. 2A to fig. 2C, the semiconductor device proposed in this embodiment has a structure similar to that of the semiconductor device in the first embodiment, including: a semiconductor substrate 200, a main gate 201 on the semiconductor substrate 200 and a channel under the main gate 201, and a source S and a drain D on both sides of the main gate 201 and the channel, n sub-gates 2021, 2022, 2023 … 202n are further disposed between the source S and the drain D, where n is an integer greater than or equal to 1, the main gate 201 and the n sub-gates are separated from each other, a main gate contact 201A is provided on the main gate 201, for applying a voltage to the main gate 201, sub-gate contacts 2021A, 2022A, 2023a … 202nA are respectively disposed on the n sub-gates 2021, 2022, 2023 … 202n for applying voltages to the n sub-gates, a source contact 203A and a drain contact 204A are provided at the source S and the drain D, respectively, to apply voltages to the source S and the drain D, respectively.
Also, in the present embodiment, in order to facilitate the control of the saturation current, the n sub-gates 2021, 2022, 2023 … 202n are disposed in the channel direction or in the source-drain direction (i.e., the direction indicated by the arrow in fig. 2C) as shown in fig. 2C. Further, preferably, the n sub-gates 1021, 1022, 1023 … 102n are arranged in parallel along the source-drain direction.
The semiconductor device proposed in this embodiment is different from the semiconductor device in the first embodiment in that, as shown in fig. 2A to 2C, in this embodiment, the main gate 101 is in a finger shape and includes n +1 fingers, and one sub-gate is disposed between two adjacent fingers.
It will be appreciated that when the sub-gate is not used to apply a voltage to the channel, the sub-gate is biased at a corresponding voltage state (off-state), for example at ground for NMOS devices and at operating Voltage (VDD) for PMOS devices.
The semiconductor device of the present embodiment can also obtain accurate saturation current control.
EXAMPLE III
FIG. 3A is a schematic layout of a semiconductor device according to another embodiment of the present invention; fig. 3B is a cross-sectional view of the semiconductor device shown in fig. 3A taken along a-a direction; fig. 3C is a cross-sectional view of the semiconductor device shown in fig. 3A taken along the direction B-B, and the semiconductor device according to an embodiment of the present invention will be described in detail with reference to fig. 3A to 3C.
As shown in fig. 3A to fig. 3C, the semiconductor device proposed in this embodiment has a structure similar to that of the semiconductor device in the first embodiment, including: a semiconductor substrate 300, a main gate 301 on the semiconductor substrate 300 and a channel under the main gate 301, and a source S and a drain D at both sides of the main gate 301 and the channel, n sub-gates 2021, 2022, 2023 … 202n are further disposed between the source S and the drain D, n is an integer greater than or equal to 1, the main gate 301 and the n sub-gates are separated from each other, a main gate contact 301A is provided on the main gate 301, for applying a voltage to the main gate 301, sub-gate contacts 3021A, 3022A, 3023a … 302nA are provided at the n sub-gates 3021, 3022, 3023 … 302n, respectively, for applying voltages to the n sub-gates, a source contact 303A and a drain contact 304A are provided at the source S and the drain D, respectively, to apply voltages to the source S and the drain D, respectively.
Also, in the present embodiment, in order to facilitate the control of the saturation current, the n sub-gates 3021, 3022, 3023 … 302n are disposed in the channel direction or in the source-drain direction (i.e., the direction indicated by the arrow in fig. 2C). Further, preferably, the n sub-gates 3021, 3022, 3023 … 302n are juxtaposed in the along-source-drain direction.
The semiconductor device proposed in this embodiment is different from the semiconductor device in the first embodiment in that, as shown in fig. 3A to 3C, in this embodiment, the main gate 101 is disposed in the middle region of the channel, and the sub-gates are disposed on both sides of the main gate. Optionally, n is an even number, for example, 2, 4, and 6, when n is an even number, the number of the sub-gates on both sides of the main gate is the same, that is, the sub-gates are symmetrically distributed on both sides of the main gate.
It will be appreciated that when the sub-gate is not used to apply a voltage to the channel, the sub-gate is biased at a corresponding voltage state (off-state), for example at ground for NMOS devices and at operating Voltage (VDD) for PMOS devices.
The semiconductor device of the present embodiment can also obtain accurate saturation current control.
Example four
A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to fig. 4.
As shown in fig. 4, the method for manufacturing a semiconductor device according to this embodiment includes the following steps:
step 401: providing a semiconductor substrate, and forming a grid material layer and a source electrode and a drain electrode which are positioned at two sides of the grid material layer on the semiconductor substrate.
Wherein the semiconductor substrate may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). As an example, in the present embodiment, the constituent material of the semiconductor substrate is single crystal silicon.
The gate material layer may be formed by a method commonly used in the art, for example, first forming a gate oxide layer on the semiconductor substrate by a method such as a thermal oxidation method, PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), etc., then forming a gate material layer such as polysilicon on the gate oxide layer by one of selective Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD), and Selective Epitaxial Growth (SEG), and finally patterning the gate oxide layer and the gate material layer by a photolithography and etching process to form the gate material layer on the semiconductor substrate.
After the gate material layer is formed, offset spacers may be formed on both sides of the gate material layer, and then an LDD implantation process is performed, where the implanted ions are determined according to the device type. For example, NMOS devices are implanted with N-type ions and PMOS devices are implanted with P-type ions. And then forming a gap wall on the offset side wall, and doping by taking the gap as a mask to form a source S and a drain D.
Step 402: and patterning the grid electrode material layer to form a main grid electrode and n sub grid electrodes which are separated from the main grid electrode.
Specifically, the gate material layer is patterned by a photolithography and etching method commonly used in the art, a main gate and n sub-gates separated from the main gate are formed between the source and the drain, and n is an integer greater than or equal to 1. Preferably, the n sub-gates are arranged along the source-drain direction, and the n sub-gates are arranged in parallel, so that applying a voltage to each of the sub-gates is equivalent to applying a voltage to the channel.
Illustratively, as shown in fig. 1A to 1C, the main gate includes n openings, and one sub-gate is disposed in each of the openings.
Illustratively, as shown in fig. 2A to 2C, the main gate includes n +1 fingers, and one sub-gate is disposed between two adjacent fingers.
Illustratively, as shown in fig. 3A to 3C, the main gate and the n sub-gates are arranged in parallel. Optionally, the main gate is disposed over a middle region of the channel, and the sub-gates are disposed on both sides of the main gate. Optionally, n is an even number, and the n sub-gates are symmetrically distributed on two sides of the main gate.
Step S403: and forming contacts of the main grid, the n sub-grids, the source electrode and the drain electrode.
Specifically, a main gate contact is provided on the main gate for applying a voltage to the main gate, sub-gate contacts are respectively provided on the n sub-gates for applying a voltage to the n sub-gates, and a source contact and a drain contact are respectively provided on the source S and the drain D for applying a voltage to the source S and the drain D, respectively, by a contact hole and interconnection layer forming method commonly used in the art. The arrangement positions of the contacts of the main gate, the n sub-gates, the source and the drain are exemplarily shown in fig. 1A to 3C.
According to the manufacturing method of the semiconductor device, the main grid and the n sub-grids separated from the main grid are formed on the semiconductor substrate, so that n +1 grid connection modes are obtained, and the voltage applied to a channel can be adjusted through different grid connection modes, so that the saturation current of the device can be accurately controlled.
EXAMPLE five
Yet another embodiment of the present invention provides an electronic apparatus including a semiconductor device and an electronic component connected to the semiconductor device. The semiconductor device is an NMOS device or a PMOS device. Wherein, this semiconductor device includes: the semiconductor device comprises a semiconductor substrate, a main grid electrode, a channel, a source electrode, a drain electrode, n sub-grid electrodes and a control circuit, wherein the main grid electrode is positioned on the semiconductor substrate, the channel is positioned below the main grid electrode, the source electrode and the drain electrode are positioned on two sides of the main grid electrode and the channel, the n sub-grid electrodes are arranged between the source electrode and the drain electrode, the main grid electrode and the n sub-grid electrodes are separated from each other, different voltages can be independently applied to the main grid electrode and the n sub-grid electrodes so as to adjust the voltage applied to the channel, and n is.
Wherein the semiconductor substrate may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). In addition, an isolation structure, which is a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure as an example, may also be formed in the semiconductor substrate. In this embodiment, the constituent material of the semiconductor substrate is monocrystalline silicon.
Further, each of the sub-gates is disposed in a direction of a source and a drain.
Further, the n sub-gates are arranged in parallel.
Further, the main gate includes n openings, and one sub-gate is disposed in each of the openings.
Further, the main gate includes n +1 fingers, and one sub-gate is disposed between two adjacent fingers.
Further, the main gate and the n sub-gates are arranged in parallel.
Further, the main gate is disposed over a middle region of the channel, and the sub-gates are disposed at both sides of the main gate.
Furthermore, n is an even number, and the n sub-gates are symmetrically distributed on two sides of the main gate.
The electronic component may be any electronic component such as a discrete device and an integrated circuit.
The electronic device of this embodiment may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game machine, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice pen, an MP3, an MP4, and a PSP, and may also be any intermediate product including the semiconductor device.
Fig. 5 shows an example of a mobile phone. The exterior of the cellular phone 500 is provided with a display portion 502, operation buttons 503, an external connection port 504, a speaker 505, a microphone 506, and the like, which are included in a housing 501.
In the electronic device of the embodiment of the invention, the key size of the active region of the included semiconductor device meets the design requirement, so the performance of the device can reach the design specification. The electronic device also has similar advantages.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (6)
1. A semiconductor device, comprising: the semiconductor device comprises a semiconductor substrate, a main grid electrode, a channel, a source electrode and a drain electrode, wherein the main grid electrode is positioned on the semiconductor substrate, the channel is positioned below the main grid electrode, the source electrode and the drain electrode are positioned in the semiconductor substrate on two sides of the main grid electrode and the channel, n sub grid electrodes are further arranged on the semiconductor substrate between the source electrode and the drain electrode, the main grid electrode and the n sub grid electrodes are separated from each other, and the n sub grid electrodes are arranged in parallel,
wherein the main gate and the n sub-gates each can be independently applied with different voltages, the voltage applied to the channel is adjusted by controlling the number of the sub-gates to which the voltage is applied, thereby obtaining different saturation currents, n is an integer of 1 or more, and wherein,
the main gate comprises n openings, and one sub-gate is arranged in each opening, or the main gate comprises n +1 fingers, and one sub-gate is arranged between two adjacent fingers.
2. The semiconductor device of claim 1, wherein each of the sub-gates is disposed in a direction of a source and a drain.
3. The semiconductor device according to any one of claims 1 to 2, wherein the semiconductor device is an NMOS device or a PMOS device.
4. A method for manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor substrate, and forming a grid material layer and a source electrode and a drain electrode which are positioned at two sides of the grid material layer on the semiconductor substrate;
patterning the grid electrode material layer to form a main grid electrode and n sub grid electrodes separated from the main grid electrode, wherein the n sub grid electrodes are arranged in parallel;
forming contacts for the main gate, the n sub-gates, the source and the drain,
wherein the main gate and the n sub-gates each can be applied with different voltages individually, and the voltages applied to the channel are adjusted by controlling the number of the sub-gates to which the voltages are applied, so as to obtain different saturation currents, n being an integer of 1 or more, wherein the main gate includes n openings in each of which one of the sub-gates is disposed, or the main gate includes n +1 fingers, and one of the sub-gates is disposed between two adjacent fingers.
5. The method according to claim 4, wherein each of the sub-gates is arranged along a direction of a source and a drain.
6. An electronic device comprising the semiconductor device according to any one of claims 1 to 3 and an electronic component connected to the semiconductor device.
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| US5442209A (en) * | 1992-05-30 | 1995-08-15 | Gold Star Electron Co., Ltd. | Synapse MOS transistor |
| CN101017783B (en) * | 2006-02-06 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Method for making the separated dual-bar field effect transistor |
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| JP2611751B2 (en) * | 1995-04-07 | 1997-05-21 | 日本電気株式会社 | Field-effect transistor |
| JP4348644B2 (en) * | 2006-09-26 | 2009-10-21 | セイコーエプソン株式会社 | Thin film transistor, electro-optical device and electronic apparatus |
| US9287406B2 (en) * | 2013-06-06 | 2016-03-15 | Macronix International Co., Ltd. | Dual-mode transistor devices and methods for operating same |
| CN103531623A (en) * | 2013-10-30 | 2014-01-22 | 上海集成电路研发中心有限公司 | Semiconductor nano-structure based transistor device and preparation method thereof |
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|---|---|---|---|---|
| US5442209A (en) * | 1992-05-30 | 1995-08-15 | Gold Star Electron Co., Ltd. | Synapse MOS transistor |
| CN101017783B (en) * | 2006-02-06 | 2013-06-19 | 中芯国际集成电路制造(上海)有限公司 | Method for making the separated dual-bar field effect transistor |
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