CN107526622B

CN107526622B - Rapid exception handling method and device for Linux

Info

Publication number: CN107526622B
Application number: CN201710702378.XA
Authority: CN
Inventors: 刘蕾; 韩存武; 史运涛; 孙德辉
Original assignee: North China University of Technology
Current assignee: North China University of Technology
Priority date: 2017-08-16
Filing date: 2017-08-16
Publication date: 2020-04-07
Anticipated expiration: 2037-08-16
Also published as: CN107526622A

Abstract

The invention discloses a method and a device for quickly processing an exception of Linux, which can reduce the time spent on interrupt processing in a system based on an embedded main stream processor. The method comprises the following steps: s1, compiling the main program and the interrupt handler, and forbidding the registers belonging to the SET2 class; s2, replacing registers belonging to SET1 class in the compiled interrupt processing program with registers belonging to SET2 class by using a preset mapping relation, wherein the SET2 class and the SET1 class are obtained by dividing registers needing to be saved in a processor into two groups of registers with the same number; and S3, linking the compiled main program and the replaced interrupt processing program, and executing.

Description

Rapid exception handling method and device for Linux

Technical Field

The invention relates to the field of communication, in particular to a method and a device for quickly processing an exception of Linux.

Background

The interrupt or system call overhead is the time of the interrupt response process, and the interrupt response process is the time for processing the process, called interrupt response overhead, when an event occurs, before the event enters the interrupt, the current event must be remembered and then the event is processed. The basic definition is: the time taken from issuing the interrupt request to entering the interrupt processing.

For a pre-emptive kernel, a specific function is called first, which informs the kernel that interrupt servicing is imminent so that the kernel can track the nesting of interrupts. The interrupt response time of a preemptive core is given by: the interrupt response time is the maximum time to shut down the interrupt + the time to save the CPU internal registers + the execution time to enter the interrupt service function + the first instruction time to start executing the Interrupt Service Routine (ISR). For frequent interrupts, the "time to save CPU internal registers" tends to account for a large portion of the interrupt response time.

For an embedded linux system, a large number of system calls or external interrupts are generated during the running process of the embedded linux system. Even if the code is normally running, due to the limitation of the number of hardware tlbs (transport look aside buffer), a large number of tlb exceptions are generated, and register saving and restoring can be caused in the process of context switching from the user mode to the kernel mode. The time consumption is huge, especially for frequently-occurring and short-time processing of interrupts or exceptions, a large amount of cpu consumption is used in the backup recovery process between general registers and memory.

Disclosure of Invention

In view of the above, the present invention provides a method and an apparatus for fast exception handling in Linux, which can reduce the time of interrupt handling overhead in a system based on an embedded main stream processor (ppc, arm, etc.).

On one hand, the embodiment of the invention provides a method for quickly processing an exception of Linux, which comprises the following steps:

s1, compiling the main program and the interrupt handler, and forbidding the registers belonging to the SET2 class;

s2, replacing registers belonging to SET1 class in the compiled interrupt processing program with registers belonging to SET2 class by using a preset mapping relation, wherein the SET2 class and the SET1 class are obtained by dividing registers needing to be saved in a processor into two groups of registers with the same number;

and S3, linking the compiled main program and the replaced interrupt processing program, and executing.

On the other hand, an embodiment of the present invention provides a fast exception handling apparatus for Linux, including:

a first compiling unit for compiling the main program and the interrupt handler and disabling registers belonging to the SET2 class;

the replacing unit is used for replacing registers belonging to SET1 class in the compiled interrupt processing program with registers belonging to SET2 class by using a preset mapping relation, wherein the SET2 class and the SET1 class are obtained by dividing registers needing to be saved in the registers of the processor into two groups of registers with the same number;

and the execution unit is used for linking the compiled main program and the replaced interrupt processing program and executing the program.

The Linux rapid exception handling method and the device thereof provided by the embodiment of the invention disable the registers belonging to the SET2 class when compiling the main program and the interrupt handling program, and use the preset mapping relation to replace the registers belonging to the SET1 class in the compiled interrupt handling program into the registers belonging to the SET2 class, so that the main program and the interrupt handling program respectively only contain the registers belonging to the SET1 class and the SET2 class when executing, namely, the scheme adopts two register SETs to realize kernel state user state isolation, the two register SETs are obtained by dividing the registers needing to be saved in the registers of the processor into two register SETs with the same number, the kernel state user states can be ensured to be consistent, the two register SETs are mutually independent and do not interfere with each other when running, one register SET is fixedly used by the kernel state and the user state, thereby avoiding the situation that the kernel state falls into the kernel state or exits from the kernel state to the user state, in addition, the scheme is not limited to a specific cpu architecture and can be applied to processors with various architectures such as x86, mips, ppc and the like.

Drawings

FIG. 1 is a schematic flow chart illustrating a method for handling a quick exception in Linux according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a Linux fast exception handling device according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments, but not all embodiments, of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The switching path from the user state to the kernel state is as follows:

1: calling a system; 2: interrupting; 3: and (6) abnormal.

1. And the application program of the user space enters the kernel space through system call. At this time, the process of the user space needs to transmit a plurality of variables and parameter values to the kernel, and when the kernel runs, some register values, variables and the like of the user process need to be stored. The so-called "process context" can be regarded as the parameters passed to the kernel by the user process, and the set of variable and register values and the current environment to be saved by the kernel.

2. The hardware causes the kernel to call an interrupt processing program to enter the kernel space through a trigger signal. In the process, some variables and parameters of the hardware are also transmitted to the kernel, and the kernel processes interrupt processing through the parameters. So-called "interrupt context", which may also be regarded as the parameters and kernel passed by the hardware, and some other context that needs to be saved (mainly the process context that is currently interrupted from execution).

3. And the system operation is abnormal, such as 0 division or tlb miss, and enters a kernel state. As in 2, a complete set of variables and register values and the current context, etc. need to be saved.

For most cpu architectures, the method of context switching is software context save/restore. In this method, the main registers are saved by a save software command at the start of an interrupt routine and restored by a software command at the end of the interrupt routine. If the interrupt handler is written in a high level programming language, for example, the programmer is not allowed to specify which particular register to use, the compiler may simply save and restore all registers. This is very time consuming. For example, a MIPS processor has more than 20 registers and interrupt handlers must be properly saved and restored at the beginning and end of the interrupt handler. This approach would also be quite inefficient if the interrupt routine used only a few registers. This loss of performance can be significant if interrupt programs are frequently called during program execution.

One of the main features of this method is that the interrupt handler is written in assembly language so that the programmer can control the registers for the interrupt handler. The programmer adds save and restore commands to the registers to save and restore the registers used in the exception routine. Writing interrupt handlers in assembly language, while more efficient use of processor resources, is more time consuming and error prone when writing software than high level languages.

Yet another method of context switching is hardware context save/restore. In this method, when the hardware automatically performs context saving while an interrupt is responded, and when the interrupt routine ends, context restoration is automatically performed. Hardware context save/restore, while also time consuming, is much less overhead than software controlled context switching. But not all processors support hardware context switching.

Applicants have discovered in practicing the present invention that in most operations, compilers typically use only a small fraction of all available registers. Thus, a portion of the registers are reserved for use as interrupt handlers, while the remaining registers are used by the main program. This approach minimizes the time it takes to save and restore registers at the interrupt handler entry and exit points. Based on this, referring to fig. 1, the present embodiment discloses a fast exception handling method for Linux, including:

s1, compiling the main program and the interrupt processing program (the compiled main program and the interrupt processing program are binary codes), and forbidding registers belonging to the SET2 class;

The method for quickly processing the exception of Linux, provided by the embodiment of the invention, disables registers belonging to SET2 class when a main program and an interrupt handler are compiled, uses a preset mapping relation to replace the registers belonging to SET1 class in the compiled interrupt handler with registers belonging to SET2 class, so that the main program and the interrupt handler only contain the registers belonging to SET1 class and SET2 class respectively when the method is executed, namely the scheme adopts two register SETs to realize kernel state user state isolation, the two register SETs are obtained by dividing the registers needing to be saved in the registers of a processor into two register SETs with the same number, the kernel state user states can be ensured to be consistent, the two register SETs are mutually independent and do not interfere with each other when running, one register SET is fixedly used for the kernel state and the user state, the situation that the kernel state falls into the kernel state or exits from the kernel state to the user state is avoided, in addition, the scheme is not limited to a specific cpu architecture and can be applied to processors with various architectures such as x86, mips, ppc and the like.

The following takes the MIPS processor as an example to describe the division of register SETs of SET1 class and SET2 class in detail:

the MIPS processor has 32 general registers, and registers needing to be saved are selected from the registers and are divided into a SET1 type and a SET2 type. For example, the SET1 class may include the following registers: register at, register t0, register t1, register t2, register s0, register s1, register s2, register s3, and register v0, so that the following registers are included in the SET2 class: register t3, register t4, register t5, register t6, register t7, register s4, register s5, register s6, and register s 7. It can be understood that the SET1 class and the SET2 class are divided only by ensuring that the registers are not overlapped and the number of the registers is the same (which is the general number of registers to be saved).

For the mapping relationship, only one-to-one mapping needs to be ensured, for example, the mapping relationship may be: the mapping of the register at to the register t3, the mapping of the register t0 to the register t5, the mapping of the register t2 to the register t7, the mapping of the register v0 to the register t4, the mapping of the register t1 to the register t6, the mapping of the register s0 to the register s4, the mapping of the register s1 to the register s5, the mapping of the register s2 to the register s6, and the mapping of the register s3 to the register s 7.

Based on the foregoing method embodiment, if the main program and the interrupt handler are written in a high-level language, the S1 may include:

compiling the main program into binary codes and the interrupt processing program into assembly codes;

before the S3, the method may further include:

the interrupt handler is compiled into binary code.

In the embodiment, the high-level language is used for writing the main program and the interrupt processing program, and the register replacement processing is performed in the assembly code, so that on one hand, the problem that the assembly cannot realize complex functions is not worried about, and on the other hand, the information contained in the binary code is more complex than that of the assembly code, so that the error probability can be reduced in the replacement process compared with the embodiment.

Referring to fig. 2, the present embodiment discloses a fast exception handling apparatus for Linux, including:

a first compiling unit 1 for compiling a main program and an interrupt handler and disabling registers belonging to the SET2 class;

the replacing unit 2 is configured to replace, by using a preset mapping relationship, registers belonging to a SET1 class in the compiled interrupt handler with registers belonging to a SET2 class, where the SET2 class and the SET1 class are obtained by dividing registers to be saved in a processor into two groups of registers with the same number;

and the execution unit 3 is used for linking the compiled main program and the replaced interrupt processing program and executing the main program.

The Linux fast exception handling device provided by the embodiment of the invention disables registers belonging to the SET2 class when compiling a main program and an interrupt handling program, replaces the registers belonging to the SET1 class in the compiled interrupt handling program with registers belonging to the SET2 class by using a preset mapping relation, and only includes the SET1 class and the SET2 class registers in the main program and the interrupt handling program when executing, namely the scheme adopts two register SETs to realize kernel state user state isolation, the two register SETs are obtained by dividing registers needing to be saved in the registers of a processor into two register SETs with the same number, the kernel state user states can be ensured to be consistent, the two register SETs are mutually independent and do not interfere with each other when running, one register SET is fixedly used for the kernel state and the user state, the situation that the kernel state falls into the kernel state or exits from the kernel state to the user state is avoided, in addition, the scheme is not limited to a specific cpu architecture and can be applied to processors with various architectures such as x86, mips, ppc and the like.

On the basis of the foregoing device embodiment, if the main program and the interrupt handler are assembly codes, the first compiling unit may be specifically configured to:

the apparatus may further include:

and the second compiling unit is used for compiling the interrupt processing program into binary codes before the execution unit works.

On the basis of the foregoing device embodiment, if the processor is a MIPS processor,

the SET1 classes may include: register at, register t0, register t1, register t2, register s0, register s1, register s2, register s3, and register v0, the SET2 classes may include: register t3, register t4, register t5, register t6, register t7, register s4, register s5, register s6, and register s7,

the mapping relationship may be: the mapping of the register at to the register t3, the mapping of the register t0 to the register t5, the mapping of the register t2 to the register t7, the mapping of the register v0 to the register t4, the mapping of the register t1 to the register t6, the mapping of the register s0 to the register s4, the mapping of the register s1 to the register s5, the mapping of the register s2 to the register s6, and the mapping of the register s3 to the register s 7.

Compared with the prior art, the invention has the following advantages:

1. the method and the device really realize quick system call or quick exception handling, and are independent of specific processing contents. It allows very fast context switching.

2. The kernel state stack space is saved, and the memory utilization is more efficient.

3. The present invention allows the interrupt routine to be carried out through C or other high-level languages. Flexibility is greatly enhanced over the previous need to write interrupt handlers in assembly language to reduce the context overhead, and interrupt handling cannot be overly complicated.

Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A quick exception handling method for Linux is characterized by comprising the following steps:

2. The method according to claim 1, wherein if the main program and the interrupt handler are written in a high-level language, the step S1 includes:

before the S3, further comprising:

the interrupt handler is compiled into binary code.

3. The method of claim 2, wherein if the processor is a MIPS processor,

the SET1 classes include: register at, register t0, register t1, register t2, register s0, register s1, register s2, register s3 and register v0, the SET2 class includes: register t3, register t4, register t5, register t6, register t7, register s4, register s5, register s6, and register s7,

the mapping relation is as follows: the mapping of the register at to the register t3, the mapping of the register t0 to the register t5, the mapping of the register t2 to the register t7, the mapping of the register v0 to the register t4, the mapping of the register t1 to the register t6, the mapping of the register s0 to the register s4, the mapping of the register s1 to the register s5, the mapping of the register s2 to the register s6, and the mapping of the register s3 to the register s 7.

4. A quick exception handling apparatus for Linux, comprising:

5. The apparatus of claim 4, wherein if the main program and the interrupt handler are written in a high-level language, the first compiling unit is specifically configured to:

the device further comprises:

6. The apparatus of claim 5, wherein if the processor is a MIPS processor,