CN106406991A - Operation method of ThreadX operation system on ARM processor - Google Patents
Operation method of ThreadX operation system on ARM processor Download PDFInfo
- Publication number
- CN106406991A CN106406991A CN201610784549.3A CN201610784549A CN106406991A CN 106406991 A CN106406991 A CN 106406991A CN 201610784549 A CN201610784549 A CN 201610784549A CN 106406991 A CN106406991 A CN 106406991A
- Authority
- CN
- China
- Prior art keywords
- thread
- interrupt
- interruption
- execution
- arm processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
Abstract
The invention discloses an operation method of a ThreadX operation system on an ARM processor. The method comprises the following steps of (1) initializing an operation environment of the ARM processor and switching the operation environment into a privileged mode; (2) initializing an underlying task of the ARM processor; (3) creating an interrupt context thread stack frame, initializing the interrupt context thread stack frame and creating a thread; and (4) loading an interrupt context of an execution thread to an ARM register, beginning to process the execution thread and changing the execution thread into a current thread at the moment and responding to synchronous event processing and asynchronous event processing in the current thread operation process, wherein the synchronous event processing is an active thread switching process and the asynchronous event processing is a passive interrupt response process. A system platform built on the basis of the method is high in instantaneity and high in reliability; the interrupt response speed is very high; the operation method supports kernel deprivation and time slice-based round-robin scheduling functions of the ThreadX operation system; and an interrupt nesting function is achieved.
Description
【Technical field】
The invention belongs to field of computer technology is and in particular to a kind of fortune on arm processor for ThreadX operating system
Row method.
【Background technology】
ThreadX operating system is the hard real-time operating system that Express Logic company designs for Embedded Application, leads to
Crossing interface routine reasonable in design can make ThreadX operating system run on various processor.Operating system and processor
Between assembler language interface routine be in system operation instruction closeness highest part although a lot of processing method institute
The interface routine providing can meet the requirement of most of real-time systems, but execution efficiency is not high.Problem is concentrated mainly on finger
Order is not simplified, and storehouse can not do minimum design using the rule of compiler, does not support interrupt nesting and does not support that kernel is shelled
Take function etc. by force.
【Content of the invention】
It is an object of the invention to provide a kind of operation method on arm processor for ThreadX operating system, to solve base
In the arm processor platform stabilization of ThreadX operating system and the problem of high efficiency.
The present invention employs the following technical solutions：
A kind of operation method on arm processor for ThreadX operating system, comprises the following steps：
Step one, the running environment of initialization arm processor simultaneously switch to privileged mode；
Step 2, the underlying task of initialization arm processor；
Context thread stack frame is interrupted in step 3, establishment, and initializes interruption context thread stack frame and wound
Build thread；
Step 4, the interruption context of execution thread is loaded in ARM depositor, and to execution thread start to process,
Now execution thread is changed into current thread, carries out responding at synchronous event process and asynchronous event in current thread running
Reason, synchronous event is processed as active thread handoff procedure, and asynchronous event is processed as passive interrupt response process.
Further, in step 4, synchronous event processing procedure is as follows：
In current thread running, by calling system service function, and then CPU control is called to return function, will
The execution scene of current thread saves as request contexts storehouse thread using returning function, after the completion of preserving execution scene, then
Carry out the switching of thread by thread scheduling function.
Further, in step 4, asynchronous event processing procedure is as follows：
When there is asynchronous event in current thread running, held by calling interrupt processing function to preserve current thread
Row scene, then starts to execute Interrupt Service Routine, after the completion of service routine execution to be interrupted, according to the current thread being interrupted
Point of interruption position and the status information of execution thread and current thread, recover to execute scene or carry out kernel to deprive operation.
Further, in asynchronous event processing procedure, the method preserving current thread execution scene is：
A, in interrupt mode, call the execution interrupt mode jump instruction of interrupt processing function, jump instruction is divided into wirelessly
Idle loop instruction area during Cheng Zhihang, the thread instruction region being currently running, interruption routine instruction area, interrupt processing function
The region being fallen into according to the point of interruption is carried out preservation current thread and executes scene：
When preserve the point of interruption be located at no thread execution when idle loop instruction area when, do not preserve any depositor；
When preserving the point of interruption and being located at the thread instruction region being currently running and interruption routine instruction area, SPSR is deposited
Device is saved in the storehouse of Current interrupt pattern；Then it is incremented by the counting of system state variables, the count table of system state variables
Show the Current interrupt nesting number of plies, also illustrate that and be currently located in interrupt mode；
B, by system automatic jump to interrupt entrance function execute interrupt requests, first the pattern switching of processor is
System model, by the lr depositor press-in storehouse under system model, calls Interrupt Service Routine afterwards, carries out asynchronous event
Process；
After the completion of c, asynchronous event are processed, then the pattern switching of system is returned by lr depositor under recovery system pattern
Interrupt mode, carries out recovering execution scene or carry out kernel to deprive operation.
Further, recover execution scene or carry out kernel and deprive the method for operation be：
5.1) when the counting of system state variables is not 0, it is interrupt nesting situation, that is, the point of interruption refers to positioned at interruption routine
Make region, recover interruption routine and execute scene；
5.2) when system state variables is when being counted as 0, directly switch to privileged mode, and observe to deprive and forbid variable：
When deprive forbid that variable is not 0 when, the point of interruption is located at unalienable instruction area, recovers current thread execution existing
?；
When deprive forbid that variable is 0 when, the point of interruption be located at can deprive instruction area, if there is not the ready of higher priority
Thread, then recover current thread and execute scene；Otherwise, preserve the interruption context being interrupted thread, then call thread scheduling
Function executes the ready thread of high priority, realizes kernel and deprives operation.
Further, interrupt context different with the Warning Mark of 0 offset address storage of request contexts.
Further, the concrete grammar of step one：The running environment of initialization arm processor, including each pattern of initialization
Storehouse distribution and each pattern SP, afterwards arm processor is switched to privileged mode, and calls main letter
Number, and then call kernel entrance function.
Further, the concrete grammar of step 2：The underlying task of initialization arm processor, including setting cycle clock
Interrupt source, finds the free memory first address for thread stacks distribution.
The invention has the beneficial effects as follows：Build storehouse, call thread and thread control to return by distinctive stacking method
Also the method such as function can give full play to the characteristic of ThreadX operating system, makes full based on the system platform constructed by this method
Real-time, the high feature of reliability of foot, and Response time is very fast, if the clock frequency of CPU is 50MHz, response
The maximum duration of asynchronous event is less than 0.6us；This method supports that the kernel of ThreadX operating system deprives scheduling feature, makes height
Priority thread is faster executed, and supports the robin scheduling function based on timeslice for the ThreadX operating system it is achieved that interrupting
Nested function.
【Brief description】
Fig. 1 is the interruption context stack framework in the present invention；
Fig. 2 is the request contexts stack frame in the present invention.
【Specific embodiment】
The present invention is described in detail with reference to the accompanying drawings and detailed description.
The invention discloses a kind of operation method on arm processor for ThreadX operating system, comprise the following steps：
Step one, the running environment of initialization arm processor, the storehouse distribution including each pattern of initialization and each pattern
Arm processor is switched to privileged mode svc, and calls principal function main, and then calls kernel by SP afterwards
Entrance function _ tx_initialize_kernel_enter；Each pattern include privileged mode svc, system model sys, common in
Disconnected pattern irq and fast interrupt mode fiq, i.e. sp_svc, sp_sys, sp_irq, sp_fiq.SP includes phase
Answer r13 the or sp depositor of pattern.
Step 2, the underlying task of initialization arm processor, that is, realize function _ tx_initialize_low_level.
This function is in kernel start-up course, and ThreadX operating system initializes the interface of assembly language program(me) with arm processor,
All arm processor correlation initialization operations will be realized in this function, including setting periodic clock interrupts source, find for thread
The free memory first address of storehouse distribution；
CPU correlation initialization operation includes configuring coprocessor register realization caching CACHE, memory management unit MMU
Setting etc.；
Setting tick source, for producing periodic interruptions with driving timing device；
Distribute chart according to self-defining RAM and Link Rule calculates the internal memory lowest address for thread stacks；Will be interior
Deposit lowest address to store in threadX specifying variable _ tx_initialize_unused_memory；Finger according to compiler
Order collection option, i.e. THUMB instruction set or ARM instruction set, using corresponding jump instruction.
Step 3, set up function _ tx_thread_stack_build by thread stacks and create and interrupt context thread heap
Stack frame, this function is ThreadX operating system and the thread stacks of arm processor set up assembly language program(me) interface, by interior
The thread creation function that core provides is called, for setting up the stack frame that application thread starts；
And initialize interruption context thread stack frame and create storehouse thread, the establishment of any thread all will call line
Journey storehouse is set up function _ tx_thread_stack_build and is set up a thread stacks framework being referred to as interruption context,
And initialization thread stack frame.
This function interface has two parameters, and the parameter that depositor r0 is transmitted is thread control block TCB address, depositor r1
The parameter transmitted is the entrance function address of thread.
Obtain thread stacks bottom address so as to 8 byte-aligned from TCB；
Reserve to low address direction from thread stacks bottom and interrupt space shared by context frames；Thread is constructed according to Fig. 1
Interruption context required for initial start；Update the thread stacks pointer in TCB；According to the instruction set option of compiler, that is,
THUMB instruction set or ARM instruction set, using corresponding jump instruction.
Interrupt the stack frame of context as shown in figure 1, the growing direction of in figure storehouse is to be increased from high address to low address
Long；Tx_stack_end is the storehouse bottom of set up thread；Tx_stack_limit is the heap stack top of set up thread；tx_
Stack_ptr is the thread stacks pointer after the completion of thread stacks foundation；For interrupting context in form, often row accounts for 4 bytes,
Context Warning Mark, the Current Program Status depositor of 4 offset address corresponding A RM processors are interrupted in 0 offset address storage
CPSR, design thread operates under privileged mode SVC, and CPSR should be initialized as SVC pattern, and 8 offset address to 0x40 offset ground
Location corresponds to the depositor of arm processor, and wherein sl is r10, and fp is r11, and ip is r12, and lr is r14, and pc is r15.
When certain thread executes first, the interruption context constructed by _ tx_thread_stack_build removes 0 skew ground
Outside location, after other guide will be loaded in arm processor depositor, the principal function of this thread will bring into operation.
Step 4, by thread scheduling function _ tx_thread_schedule, the interruption context of execution thread is loaded
To in ARM depositor, execution thread is the ready thread of limit priority, and to execution thread start to process, that is, runs this line
Journey principal function, now execution thread be changed into current thread；
Calling system service function can be passed through in current thread running, and then actively call CPU control to return
Function, the execution scene of current thread is saved as request contexts storehouse thread using returning function, preserves execution scene complete
Cheng Hou, then carry out the switching of thread by thread scheduling function _ tx_thread_schedule.
Thread scheduling function _ tx_thread_schedule realizes thread switching, by by the context in thread stacks
It is loaded in ARM depositor, that is, restoring scene makes ready thread start to execute process, and is incremented by ready thread scheduling and count and set
Put the timeslice of ready thread.If no ready thread, Infinite Cyclic thread scheduling function _ tx_thread_schedule, etc.
Treat that asynchronous event removes to recover certain thread to ready state, ready thread is thread chained list medium priority highest thread, by grasping
Go out as system-computed, and be saved in variable _ tx_thread_execute_ptr.
Thread scheduling function _ tx_thread_schedule is the assembler language of ThreadX operating system and arm processor
Routine interface, calls after ThreadX operating system completes initialization, and its major function is to load up and down from thread stacks
Literary composition, to the depositor of processor, recovers the operation of thread.
It is first turned on interrupting, then realizes idle loop during no ready thread, otherwise enter the flow process recovering ready thread,
Then the operation being incremented by ready thread counts, by the timeslice assignment in ready thread TCB in length of a game's piece variable；Afterwards
Stack pointer in ready thread TCB is loaded into sp depositor；Eject the 1st context from sp depositor indication stack address
Individual and the 2nd value is loaded into r0 and r1 depositor respectively, now stores Context identifier in r0 depositor, and r1 stores cpsr；Sentence
Disconnected r0 is to interrupt context or request contexts, if interrupting context, directly recovers the instruction at thread execution scene；If
Request contexts, then first by r4 in request contexts, r5, r6, r7, r8, r9, sl, fp, pc are loaded into right in arm processor
The depositor answered, wherein lr depositor store thread return address, and the cpsr content then being stored before in r1 is loaded into
Processor cpsr depositor, then branches to the thread return address of storage in lr, starts to recover thread operation.
Synchronize event handling and asynchronous event is processed in current thread running, synchronous event is processed as actively
Thread handoff procedure, and asynchronous event is processed as passive interrupt response process.
Synchronous event processing procedure is as follows：
Calling system service function is needed, system service function is actively called CPU control in current thread running
Power returns function, function is returned using control in the execution scene of current thread and saves as request contexts storehouse thread, protect
After the completion of counter foil row scene, then the switching carrying out thread by thread scheduling function；
Control returns the assembly language program(me) interface that function is operating system and processor, by operating system service function
Call, abandon CPU control for current active thread.
First request contexts mark 0 is assigned to r0 depositor, cpsr is assigned to r1 depositor and preserves temporarily, then
By r0-r9, sl, fp, lr are pressed in current active thread storehouse, are then shut off interrupting, then preservation current thread remaining time
Piece variable, in TCB, then preserves current stack pointer to TCB, now scene protection finishes, afterwards by the time of current thread
The counting variable of piece global variable and current thread operation resets, and finally jumps to scheduling function _ tx_thread_schedule.
Control return refer to preserve current thread execute scene, that is, using compiling rule, by necessary ARM depositor guarantor
It is stored in thread stacks, necessary depositor is referred to as request contexts, request contexts and 0 offset address interrupting context
The Warning Mark of storage is different.
The rule of compiler why can be utilized here, being because that control is returned is to take by calling system all the time
Business function is realized, rather than passes through asynchronous event.For example, when thread request resource waits, corresponding system service function will
Call _ tx_thread_system_return._ tx_thread_system_return is the function of no ginseng, so not needing
Preserve temporary register r0, r1, r2, r3.In addition, function reentry point r15 is clear and definite, it is saved in r14, so not needing
Preserve r15.
Request contexts framework is as shown in Fig. 2 the growing direction of in figure storehouse is to be increased from high address to low address；tx_
Stack_end is the storehouse bottom of set up thread；Tx_stack_limit is the heap stack top of set up thread；tx_stack_ptr
Return to the stack pointer after system for current thread control, be stored in current thread control block；For request in form
Context, often goes and accounts for 4 bytes, 0 offset address storage request contexts Warning Mark, 4 offset address corresponding A RM processors
Current Program Status depositor CPSR, 8 offset address to 0x40 offset address correspond to the depositor of arm processor, wherein sl
For r10, fp is r11, and lr is r14.After the completion of saving scene, the timeslice global variable of current thread and current thread are run
Counting variable reset, then call described thread scheduling function realize thread switching.
Asynchronous event processing procedure is as follows：
When there is asynchronous event in current thread running, held by calling interrupt processing function to preserve current thread
Row scene, then starts to execute Interrupt Service Routine, after the completion of service routine execution to be interrupted, according to the current thread being interrupted
Point of interruption position and the status information of execution thread and described current thread, recover to execute scene or carry out kernel to deprive operation.
Asynchronous event is triggered by interrupt mechanism, when interrupting occurring pc pointer be likely located at any outside critical zone
The location of instruction, this position is referred to as the point of interruption, abbreviation POI.When occurring in current thread running to interrupt, in calling
The disconnected function preservation current thread that processes executes scene, then starts to execute Interrupt Service Routine, service routine to be interrupted has executed
Cheng Hou, according to the status information of the current thread point of interruption position being interrupted and execution thread and current thread, recovers execution existing
Or carry out kernel and deprive operation.
Realize interrupt processing function _ tx_irq_handler, this function is only an encapsulation function, calls each by order
Subfunction completes an asynchronous event and processes, and after interrupting occurring, processor is automatically by point of interruption pc pointer and point of interruption cpsr
It is stored in lr depositor and interrupt mode spsr of interrupt mode respectively, switch mode, to interrupt mode, then puts pc pointer simultaneously
Interrupt jump instruction call by location interrupt processing function to interrupt vector table.
When processing asynchronous event, there is kernel and deprive function and interrupt nesting function, it comprises the following steps that,
A, in current thread running, asynchronous event sends interrupt requests, and arm processor is current by present mode
Program status register and PC pointer register back up to SPSR the and lr depositor of interrupt mode respectively, and switch to interruption mould
Formula, PC pointer is jumped to interrupt vector table, calls interrupt processing function _ tx_thread_context_save execution to interrupt mould
Formula jump instruction, jump instruction is divided into idle loop instruction area Idle Loop during three parts, no thread execution
Instruction Domain (ILID), the thread instruction region Running Thread Instruction being currently running
Domain (RTID), interruption routine instruction area ISR Instruction Domain (ISRID), interrupt processing function _ tx_
Thread_context_save executes scene by carrying out preservation current thread according to the region that the preservation point of interruption falls into：
When preserve the point of interruption be located at no thread execution when idle loop instruction area when, do not preserve any depositor；
When preserving the point of interruption and being located at the thread instruction region being currently running and interruption routine instruction area by SPSR, sl,
Ip, lr, r0, r1, r2, r3 depositor is saved in the storehouse of Current interrupt pattern, that is, in the storehouse under IRQ pattern；Then pass
Increase the counting of system state variables _ tx_thread_system_state, system state variables _ tx_thread_system_
The counting of state represents the Current interrupt nesting number of plies, also illustrates that and is currently located in interrupt mode；
B, realize support interrupt nesting function _ tx_thread_irq_nesting_start function, in order that interrupt clothes
The storehouse of business routine ISR and thread stacks are separated, and first processor mode are switched to system model, interrupt handling program
ISR just runs under system model, and the lr depositor under system model is pressed in storehouse, during in order to protecting nested interrupt to occur
The return address of POI place function, function returns, and then calls Interrupt Service Routine ISR, carries out asynchronous event process, that is, enter
The event handling in row respective interrupt source；
Detailed process is as follows：
First by temporary register r0, in r1, r2, r3 press-in present mode storehouse, present mode is IRQ pattern, then
Judge whether the point of interruption is located in ISRID by interrupt nesting layer number variable _ tx_thread_system_state；
If this variable is not zero then it represents that instructing generation in ISRID, execution is incremented by _ tx_thread_system_
State, then judge whether the point of interruption occurs in RTPID by current thread pointer variable, if occurring in RTPID, by SPSR,
In sl, ip, lr depositor press-in present mode storehouse, it is then back to position IRQ Processing Return；Otherwise, abandon
In 4 depositors of press-in storehouse, return again to position IRQ Processing Return；
If this variable is equal to 0 then it represents that instruction does not occur in ISRID, execution is incremented by _ tx_thread_system_
State, then by SPSR, in sl, ip, lr depositor press-in present mode storehouse, returns again to position IRQ Processing
Return.
C. realize support interrupt nesting function _ tx_thread_irq_nesting_end function, when ISR execution complete
Afterwards, call _ tx_thread_irq_nesting_end function, the lr depositor under answering system pattern, will eject heap by lr
Stack, switches back into interrupt mode, carries out restoring scene or carries out kernel and deprive operation；_ tx_thread_irq_nesting_end letter
The function that the function of number and above-mentioned _ tx_thread_irq_nesting_start function are realized is symmetrical, first recovers SYS
Then processor mode is switched back into IRQ pattern from SYS by the lr under pattern, finally calls _ tx_thread_context_
Restore function is forbidden interrupting, and whether the interrupt nesting number of plies of successively decreasing, be currently interrupt nesting state according to the termination nest number of plies,
When the counting of system state variables _ tx_thread_system_state is not 0, be interrupt nesting situation, i.e. point of interruption position
In interruption routine instruction area ISRID, the content reverse sequence that directly will be pressed into storehouse ejects, and recovers ISR and executes scene；If no
Nested then carry out the judgement that kernel deprives operation；
D. kernel deprives the scene that executes referring to preserve the affiliated thread of the point of interruption, and the thread of scheduling higher priority executes,
It is made to obtain the control of CPU.After the completion of interrupt nesting is processed, lr depositor under recovery system pattern, then by system
Pattern switching returns interrupt mode, carries out recovering execution scene or carry out kernel to deprive operation；
Recover execution scene or carry out the method that kernel deprives operation, that is, realize function _ tx_thread_context_
The method of restore is：
In _ tx_thread_context_restore function, situations below is had according to the position of the point of interruption：
5.1) when the counting of system state variables _ tx_thread_system_state is not 0, it is interrupt nesting feelings
Condition, that is, positioned at interruption routine instruction area ISRID, the content reverse sequence that directly will be pressed into storehouse ejects, in recovery the point of interruption
Disconnected routine executes scene；
5.2) when system state variables is when being counted as 0, illustrate that the point of interruption is located at ILID, directly switch to privileged mode,
And observe to deprive and forbid variable：
When deprive forbid that variable _ tx_thread_preempt_disable is not 0 when, the point of interruption be located at unalienable finger
Make region, recover current thread and execute scene；
When deprive forbid variable _ tx_thread_preempt_disable be 0 when, the point of interruption be located at can deprive instruction area
Domain, if there is not the ready thread of higher priority, then recovers current thread and executes scene；Otherwise, preserve and be interrupted thread
Interrupt context, then call thread scheduling function to execute the ready thread of high priority, realize kernel and deprive operation.
When meeting kernel and depriving condition, when interrupting occurring before needing to preserve, current thread executes scene, first structure
Build IRQ Context and be pressed into thread stacks to protect the scene being interrupted thread, then recover previously to be pressed into IRQ heap
Spsr in stack, sl, ip, lr depositor, wherein spsr are the cpsr depositor of breakpoint order position, and lr is breakpoint order
Position；Lr is sent to r1 depositor, so that SVC pattern is able to access that；It is switched to SVC pattern, and keep interruption to forbid；By r1
The breakpoint order position press-in thread stacks that depositor preserves；It is by r4-r9, sl, the fp of point of interruption position under SVC pattern,
Ip, lr depositor stacking；Preserve cpsr using r4 temporarily；It is switched to IRQ pattern and keep interruption to forbid；Recover under IRQ pattern
Temporary register r0-r3；It is switched to SVC pattern and keep interruption to forbid；It is that temporary register r0-r3 is pressed into thread stacks；
Cpsr the and IRQ Context that r4 is preserved identifies constant 1 and is pressed into thread stacks；Stack pointer sp depositor is saved in line
In program control clamp dog TCB；The timeslice preserving current thread count down in TCB；Finally, call thread scheduling function _ tx_
Thread_schedule executes higher priority thread.
Claims (8)
1. a kind of operation method on arm processor for ThreadX operating system is it is characterised in that comprise the following steps：
Step one, the running environment of initialization arm processor simultaneously switch to privileged mode；
Step 2, the underlying task of initialization arm processor；
Context thread stack frame is interrupted in step 3, establishment, and initializes described interruption context thread stack frame and wound
Build thread；
Step 4, the interruption context of execution thread is loaded in ARM depositor, and to described execution thread start to process,
Now described execution thread is changed into current thread, carries out responding synchronous event process and asynchronous thing in current thread running
Part is processed, and synchronous event is processed as active thread handoff procedure, and asynchronous event is processed as passive interrupt response process.
2. operation method on arm processor for the described a kind of ThreadX operating system as claimed in claim 1, its feature
It is, in described step 4, synchronous event processing procedure is as follows：
In current thread running, by calling system service function, and then CPU control is called to return function, will be current
The execution scene of thread saves as request contexts storehouse thread using returning function, after the completion of preserving execution scene, then passes through
Described thread scheduling function carries out the switching of thread.
3. operation method on arm processor for the described a kind of ThreadX operating system as claimed in claim 1, its feature
It is, in described step 4, asynchronous event processing procedure is as follows：
When there is asynchronous event in described current thread running, held by calling interrupt processing function to preserve current thread
Row scene, then starts to execute Interrupt Service Routine, after the completion of service routine execution to be interrupted, described current according to be interrupted
Thread interrupt point position and the status information of execution thread and described current thread, recover to execute scene or carry out kernel to deprive behaviour
Make.
4. as claimed in claim 3 a kind of operation method on arm processor for ThreadX operating system it is characterised in that
In described asynchronous event processing procedure, the described live method of current thread execution that preserves is：
A, in interrupt mode, call the execution interrupt mode jump instruction of interrupt processing function, described jump instruction is divided into wirelessly
Idle loop instruction area during Cheng Zhihang, the thread instruction region being currently running, interruption routine instruction area, described interrupt processing
The region being fallen into according to the point of interruption is carried out preservation current thread and executes scene by function：
When the described idle loop instruction area preserving when the point of interruption is located at no thread execution, do not preserve any depositor；
When SPSR is deposited by described preservation when the point of interruption is located at the thread instruction region being currently running and interruption routine instruction area
Device is saved in the storehouse of Current interrupt pattern；Then it is incremented by the counting of system state variables, the meter of described system state variables
Number represents the Current interrupt nesting number of plies, also illustrates that and is currently located in interrupt mode；
B, by system automatic jump to interrupt entrance function execute interrupt requests, first by the pattern switching of processor be system
Pattern, by the lr depositor press-in storehouse under system model, calls Interrupt Service Routine afterwards, carries out asynchronous event process；
After the completion of c, described asynchronous event are processed, then the pattern switching of system is returned by lr depositor under recovery system pattern
Interrupt mode, carries out recovering execution scene or carry out kernel to deprive operation.
5. as claimed in claim 4 a kind of operation method on arm processor for ThreadX operating system it is characterised in that
Described recover execution scene or carry out kernel and deprive the method for operation be：
5.1) when the counting of described system state variables is not 0, it is interrupt nesting situation, that is, the point of interruption refers to positioned at interruption routine
Make region, recover described interruption routine and execute scene；
5.2) when described system state variables is when being counted as 0, directly switch to privileged mode, and observe to deprive and forbid variable：
When deprive forbid that variable is not 0 when, the point of interruption is located at unalienable instruction area, recovers the execution of described current thread existing
?；
When deprive forbid that variable is 0 when, the point of interruption be located at can deprive instruction area, if there is not the ready line of higher priority
Journey, then recover described current thread and execute scene；Otherwise, preserve the interruption context being interrupted thread, then call thread to adjust
Degree function executes the ready thread of high priority, realizes kernel and deprives operation.
6. as claimed in claim 2 a kind of operation method on arm processor for ThreadX operating system it is characterised in that
Described interruption context is different with the Warning Mark of 0 offset address storage of described request contexts.
7. as claimed in claim 1 a kind of operation method on arm processor for ThreadX operating system it is characterised in that
The concrete grammar of described step one：The running environment of initialization arm processor, including the storehouse distribution initializing each pattern and respectively
Described arm processor is switched to privileged mode, and calls principal function, and then calls by the SP of pattern afterwards
Kernel entrance function.
8. as claimed in claim 1 a kind of operation method on arm processor for ThreadX operating system it is characterised in that
The concrete grammar of described step 2：Initialize the underlying task of described arm processor, including setting periodic clock interrupts source, look for
To the free memory first address for thread stacks distribution.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610784549.3A CN106406991B (en) | 2016-08-30 | 2016-08-30 | running method of ThreadX operating system on ARM processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610784549.3A CN106406991B (en) | 2016-08-30 | 2016-08-30 | running method of ThreadX operating system on ARM processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106406991A true CN106406991A (en) | 2017-02-15 |
| CN106406991B CN106406991B (en) | 2019-12-17 |
Family
ID=58000428
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610784549.3A Active CN106406991B (en) | 2016-08-30 | 2016-08-30 | running method of ThreadX operating system on ARM processor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106406991B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107526622A (en) * | 2017-08-16 | 2017-12-29 | 北方工业大学 | Rapid exception handling method and device for Linux |
| CN109240815A (en) * | 2018-08-24 | 2019-01-18 | 珠海格力电器股份有限公司 | A kind of multitask running method, device and equipment of shared storehouse |
| CN109409083A (en) * | 2018-09-21 | 2019-03-01 | 中国科学院信息工程研究所 | The device that return address is tampered in detection storehouse |
| CN109522099A (en) * | 2017-09-20 | 2019-03-26 | 厦门雅迅网络股份有限公司 | Improve the method and its system of non real-time nature operating system real-time |
| CN110825441A (en) * | 2019-09-23 | 2020-02-21 | 万达信息股份有限公司 | Method for implementing asynchronous system, computer equipment and storage medium |
| CN111782368A (en) * | 2020-06-30 | 2020-10-16 | 珠海全志科技股份有限公司 | Interrupt nesting processing method, device, terminal and storage medium |
| CN111897632A (en) * | 2019-05-05 | 2020-11-06 | 北京兆易创新科技股份有限公司 | Interrupt processing method and device, electronic equipment and storage medium |
| CN113806025A (en) * | 2020-06-12 | 2021-12-17 | 富泰华工业（深圳）有限公司 | Data processing method, system, electronic device and storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101668283A (en) * | 2008-09-01 | 2010-03-10 | 沃勤网络科技（上海）有限公司 | Method for dynamic loading in embedded system of mobile phone |
| US20100088703A1 (en) * | 2008-10-02 | 2010-04-08 | Mindspeed Technologies, Inc. | Multi-core system with central transaction control |
| CN103294544A (en) * | 2012-02-27 | 2013-09-11 | 展讯通信（上海）有限公司 | Embedded system as well as interrupt processing method and device thereof |
-
2016
- 2016-08-30 CN CN201610784549.3A patent/CN106406991B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101668283A (en) * | 2008-09-01 | 2010-03-10 | 沃勤网络科技（上海）有限公司 | Method for dynamic loading in embedded system of mobile phone |
| US20100088703A1 (en) * | 2008-10-02 | 2010-04-08 | Mindspeed Technologies, Inc. | Multi-core system with central transaction control |
| CN103294544A (en) * | 2012-02-27 | 2013-09-11 | 展讯通信（上海）有限公司 | Embedded system as well as interrupt processing method and device thereof |
Non-Patent Citations (2)
| Title |
|---|
| 吴千彬: "基于ARM_Cortex_R4平台的ThreadX系统移植", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
| 安蓉 等: "ThreadX 操作系统在 ARM 处理器上的移植", 《计算机工程与设计》 * |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107526622B (en) * | 2017-08-16 | 2020-04-07 | 北方工业大学 | Rapid exception handling method and device for Linux |
| CN107526622A (en) * | 2017-08-16 | 2017-12-29 | 北方工业大学 | Rapid exception handling method and device for Linux |
| CN109522099B (en) * | 2017-09-20 | 2023-03-31 | 厦门雅迅网络股份有限公司 | Method and system for improving instantaneity of non-instantaneity operating system |
| CN109522099A (en) * | 2017-09-20 | 2019-03-26 | 厦门雅迅网络股份有限公司 | Improve the method and its system of non real-time nature operating system real-time |
| CN109240815A (en) * | 2018-08-24 | 2019-01-18 | 珠海格力电器股份有限公司 | A kind of multitask running method, device and equipment of shared storehouse |
| CN109240815B (en) * | 2018-08-24 | 2021-07-23 | 珠海格力电器股份有限公司 | Multi-task running method, device and equipment for shared stack |
| CN109409083A (en) * | 2018-09-21 | 2019-03-01 | 中国科学院信息工程研究所 | The device that return address is tampered in detection storehouse |
| CN111897632B (en) * | 2019-05-05 | 2023-10-20 | 兆易创新科技集团股份有限公司 | Interrupt processing method and device, electronic equipment and storage medium |
| CN111897632A (en) * | 2019-05-05 | 2020-11-06 | 北京兆易创新科技股份有限公司 | Interrupt processing method and device, electronic equipment and storage medium |
| CN110825441A (en) * | 2019-09-23 | 2020-02-21 | 万达信息股份有限公司 | Method for implementing asynchronous system, computer equipment and storage medium |
| CN113806025A (en) * | 2020-06-12 | 2021-12-17 | 富泰华工业（深圳）有限公司 | Data processing method, system, electronic device and storage medium |
| CN113806025B (en) * | 2020-06-12 | 2023-08-18 | 富泰华工业（深圳）有限公司 | Data processing method, system, electronic device and storage medium |
| CN111782368A (en) * | 2020-06-30 | 2020-10-16 | 珠海全志科技股份有限公司 | Interrupt nesting processing method, device, terminal and storage medium |
| CN111782368B (en) * | 2020-06-30 | 2024-02-09 | 珠海全志科技股份有限公司 | Interrupt nesting processing method, device, terminal and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106406991B (en) | 2019-12-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106406991A (en) | Operation method of ThreadX operation system on ARM processor | |
| TWI705375B (en) | Interrupt request processing method, apparatus, virtualization device and readable storage medium | |
| CN103999051B (en) | Strategy for tinter resource allocation in the minds of shader core | |
| US8161481B2 (en) | Operating system providing a mutual exclusion mechanism | |
| CN102789395B (en) | Apparatus and method for managing hypercalls in a hypervisor and the hypervisor thereof | |
| US7296271B1 (en) | Replaceable scheduling algorithm in multitasking kernel | |
| GB2478733A (en) | Stack management with multiple levels of exception | |
| US8595747B2 (en) | Efficient task scheduling by assigning fixed registers to scheduler | |
| US20230135951A1 (en) | Scheduling of threads for clusters of processors | |
| EP4174648A1 (en) | Thread scheduling | |
| US20180285135A1 (en) | Cooperative virtual processor scheduling | |
| CN109933451A (en) | A kind of exception and interrupt processing system and method based on RISC-V framework | |
| CN111324432A (en) | Processor scheduling method, device, server and storage medium | |
| US6728962B1 (en) | Context swapping in multitasking kernel | |
| US9841994B2 (en) | Implementation of multi-tasking on a digital signal processor with a hardware stack | |
| CN100535864C (en) | Method of invalid time over message under system process scheduling | |
| CN109783245A (en) | Data interactive method and system based on dual system shared drive | |
| CN107526622A (en) | Rapid exception handling method and device for Linux | |
| EP4174647A1 (en) | Thread state transitions | |
| EP1233340A2 (en) | Context preservation | |
| CN110955520A (en) | Multi-task scheduling method and system for electric energy meter | |
| CN110716791A (en) | Real-time virtualization system and execution method thereof | |
| CN110059040A (en) | It is a kind of based on RISC-V framework can nested abnormal and uneven bottoms system and method | |
| US20230135214A1 (en) | Interrupt handling | |
| US11972285B2 (en) | Interrupt request processing method and apparatus, and virtualized device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |