CN107517052B - Power control drive circuit for motor control and power conversion - Google Patents
Power control drive circuit for motor control and power conversion Download PDFInfo
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- CN107517052B CN107517052B CN201710783471.8A CN201710783471A CN107517052B CN 107517052 B CN107517052 B CN 107517052B CN 201710783471 A CN201710783471 A CN 201710783471A CN 107517052 B CN107517052 B CN 107517052B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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Abstract
The present invention relates to a power control drive circuit for motor control and power conversion. It includes: the drive circuit front stage is used for controlling the output voltage of the voltage output end of the drive circuit according to a PWM signal or a logic signal sent from the outside; the grid electrode of the N-MOSFET is connected with the voltage output end of the front stage of the driving circuit; a first resistor is arranged between the grid electrode and the source electrode of the N-MOSFET, and the drain electrode of the N-MOSFET is connected with a driving power supply; the grid electrode of the P-MOSFET is connected with the voltage output end of the drive integrated circuit; a second resistor is arranged between the source electrode of the N-MOSFET and the source electrode of the P-MOSFET; and the grid electrode of the controlled power control device is connected with the third resistor in series and then is connected with the source electrode of the P-MOSFET, and the source electrode of the controlled power control device is connected with the drain electrode of the P-MOSFET.
Description
Technical Field
The present invention relates to a power control drive circuit, and more particularly to a power control device (such as a MOSFET and an IGBT) drive circuit for a power control device. The driving circuit can output peak current with large amplitude and short rising edge and falling edge. The drive circuit can be applied to the power control fields of motor control, power conversion, power management and the like by using the MOSFET and the IGBT.
Background
In the prior art, when a controlled power control device such as an MOSFET or an IGBT is started, a driving circuit needs to inject large current into a grid electrode of the controlled power control device MOSFET or the IGBT in a short time, and when the controlled power control device MOSFET or the IGBT is closed, the driving circuit needs to extract the large current from the grid electrode of the controlled power control device MOSFET or the IGBT in a short time. Alternatively, the magnitude of the drive current pulse applied to the gate of the controlled power control device MOSFET or IGBT is sufficiently large and the rising and falling edge times are sufficiently short. For this reason, the drive current output portion of the controlled power control device is generally constructed with MOSFETs, and commonly used circuits (a drive circuit front stage including a dedicated MOSFET or IGBT) are as shown in fig. 1(a) to (D).
In fig. 1, Q1 and Q2 are MOSFETs driving controlled power control devices MOSFETs or IGBTs (i.e., Q3). And R is a driving resistor used for adjusting the driving current and damping the ringing of the driving loop. The pin 3 is connected with a driving power supply. The potential of the pin 3 is V3; pins 1 and 2 are control signals that drive Q1, Q2, respectively. The potential of the pin 1 is V1, and the potential of the pin 2 is V2; in the bridge circuit, when Q3 is used in the upper bridge, 4 is connected to the positive supply of the power stage and 5 is the output. When Q3 is used in the lower bridge, 5 is connected to the power supply negative of the power stage and 4 is the output. Note that the potential of pin 4 is V4, and the potential of pin 5 is V5. The voltage of the gate of Q3 is denoted as VG3 (i.e., the potential difference between the gate and the source), in order to deeply saturate Q3 (the MOSFET enters the resistive region and the on-resistance is sufficiently small), VG3=5V-15V is necessary, and similarly, the voltage of the gate of Q1 is denoted as VG1, in order to deeply saturate Q1 (the MOSFET enters the resistive region and the on-resistance is sufficiently small), VG1=5V-15V is necessary, so that the amplitude of the control signal for turning on Q1 must reach VG1+ VG =20V-30V in the N-PMOSFET combination of fig. 1(a) and fig. 1 (D). Obviously, the circuit processing is relatively complex, so the two circuits are rarely used.
For the P-PMOSFET combination of fig. 1(B), Q1 is on when V1= V5, turning on Q3, and Q2 is on when V2= V5, turning off Q3. In order to prevent Q1 and Q2 from being turned on simultaneously, V2= V3 is required when V1= V5, V1= V3 is required when V2= V5, and in the switching process of Q1 and Q2, a suitable time interval is ensured to be inserted between the switch and the switch after the switch, and the time interval is also called dead zone protection.
For the P-NMOSFET combination of fig. 1(C), Q1 is on when V1= V5, turning on Q3, and Q2 is on when V2= V3, turning off Q3. In order to prevent Q1 and Q2 from being turned on simultaneously, V2= V5 is required when V1= V5, V1= V3 is required when V2= V3, and in the switching process of Q1 and Q2, a suitable time interval is ensured to be inserted between the switch and the switch after the switch, and the time interval is also called dead zone protection.
It can thus be seen that the control signal processing circuitry of the P-PMOSFET combination of fig. 1(B) and the P-NMOSFET combination of fig. 1(C) is relatively complex and that the operating state of the controlled power control device Q3 is not ideal, particularly during dead-time protection times.
Disclosure of Invention
The invention provides a power control driving circuit which can output peak current with large amplitude and short rising edge and falling edge (namely the on-off time of a controlled power control device is short).
In order to solve the above-described technical problem, the present invention provides a power control drive circuit including: the drive circuit front stage is used for controlling the output voltage of the voltage output end of the drive circuit according to a PWM signal or a logic signal sent from the outside; an N-MOSFET (Q1), the grid (G) of which is connected with the voltage output end of the front stage of the driving circuit; a first resistor (R1) is arranged between the grid (G) and the source (S) of the N-MOSFET (Q1), and the drain (D) of the N-MOSFET (Q1) is connected with a driving power supply; a P-MOSFET (Q2), the grid (G) of which is connected with the voltage output end of the front stage of the driving circuit; a second resistor (R2) is arranged between the source (S) of the N-MOSFET (Q1) and the source (S) of the P-MOSFET (Q2); and the grid (G) of the controlled power control device (Q3) is connected with a third resistor (R3) in series and then connected with the source (S) of the P-MOSFET (Q2), and the source (S) of the controlled power control device (Q3) is connected with the drain (D) of the P-MOSFET (Q2).
The front stage of the driving circuit is formed by a driving integrated circuit or a split device.
Preferably, the first resistor (R1) has a resistance value of less than 1K Ω, and the second resistor (R2) and the third resistor (R3) have a resistance value of less than 100 Ω.
Preferably, the voltage output end of the previous stage of the driving circuit can output a voltage of 10-15V, and the peak values of the output current and the absorption current are not less than 200 mA.
Preferably, the controlled power control device (Q3) is a MOSFET or an IGBT.
The method for operating the power control drive circuit includes:
when the PWM signal or the logic signal is effective, the output voltage VOUT of the voltage output end of the front stage of the driving circuit is =10-15V, the voltage is added to the grid electrode of the controlled power control device (Q3) through the first resistor, the second resistor and the third resistor (R1, R2, R3), and a current output current (I1) is formed; the voltage is also directly applied to the grid electrode of the N-MOSFET (Q1), so that the N-MOSFET (Q1) is conducted and is quickly and deeply saturated, and the grid electrode voltage of the controlled power control device (Q3) is quickly increased; as the gate voltage of the controlled power control device (Q3) rises, the output current (I1) is gradually reduced until the voltage at two ends of the first resistor (R1) is smaller than the threshold voltage of the N-MOSFET (Q1), the N-MOSFET (Q1) is out of conduction, the gate voltage of the controlled power control device (Q3) is held by the front stage of the driving circuit, and the controlled power control device (Q3) is maintained in a deep saturation region; when the PWM signal or the logic signal is changed from active to inactive, the voltage output end is decreased, the grid of the controlled power control device (Q3) is enabled to output a sink current (I2) to the voltage output end of the previous stage of the driving circuit through the first resistor (R1), the second resistor (R2 and the R3), and when the product of the sum of the resistances of the first resistor (R1 and the second resistor (R2) and the output sink current (I2) is larger than the threshold voltage of the P-MOSFET (Q2), the P-MOSFET (Q2) is enabled to be in saturation conduction quickly, the grid voltage of the controlled power control device (Q3) is enabled to be decreased quickly, and finally the Q2 is enabled to be disconnected; the grid voltage of the controlled power control device (Q3) is kept by the front stage of the driving circuit, and the front stage of the driving circuit can absorb the current with the peak value not less than 200mA, so that the controlled power control device (Q3) can be reliably maintained in a cut-off region.
As a variant, the voltage output end of the front stage of the driving circuit is connected in series with a fourth resistor (R4), a fifth resistor (R5) and a first gate resistor (RG 1) in sequence and then connected with the gate (G) of an N-MOSFET (Q1); the junction of the fifth resistor (R5) and the first gate resistor (RG 1) is connected in series with the first resistor (R1) and then connected with the source (S) of the N-MOSFET (Q1); the joint of the fourth resistor (R4) and the fifth resistor (R5) is connected in series with the second gate resistor (RG 2) and then connected with the gate (G) of the P-MOSFET (Q2).
As another variant, the voltage output end of the front stage of the driving circuit is connected in series with a fourth resistor (R4), a fifth resistor (R5) and a second gate resistor (RG 2) in sequence and then connected with the gate (G) of the P-MOSFET (Q2); the junction of the fourth resistor (R4) and the fifth resistor (R5) is connected in series with the first gate resistor (RG 1) and then connected with the gate (G) of the N-MOSFET (Q1); the junction of the fifth resistor (R5) and the second gate resistor (RG 2) is connected in series with the first resistor (R1) and then connected with the source (S) of the N-MOSFET (Q1).
A bridge power control circuit, comprising: the driving circuit front stage is used for respectively controlling the output voltages of a pair of voltage output ends of the driving circuit according to a pair of PWM signals or logic signals sent from the outside; the pair of voltage output ends are respectively connected with an upper bridge driving circuit and a lower bridge driving circuit which have the same structure; the upper and lower bridge driving circuits include: an N-MOSFET (Q1) with its gate connected to a voltage output terminal of the previous stage of the driving circuit; a first resistor (R1) is arranged between the grid (G) and the source (S) of the N-MOSFET (Q1), and the drain (D) of the N-MOSFET (Q1) is connected with a driving power supply; a P-MOSFET (Q2), the grid (G) of which is connected with the voltage output end of the front stage of the driving circuit; a second resistor (R2) is arranged between the source (S) of the N-MOSFET (Q1) and the source (S) of the P-MOSFET (Q2); a controlled power control device (Q3), wherein the grid (G) of the controlled power control device is connected with a third resistor (R3) in series and then connected with the source (S) of the P-MOSFET (Q2), and the source (S) of the controlled power control device (Q3) is connected with the drain (D) of the P-MOSFET (Q2); the source (S) of the controlled power control device in the upper bridge driving circuit is connected with the drain (D) of the controlled power control device in the lower bridge driving circuit, and the source (S) of the controlled power control device in the lower bridge driving circuit is connected with the common end (COM) of the front stage of the driving circuit.
Compared with the prior art, the invention has the technical effects that: (1) the power control driving circuit of the invention drives the N-MOSFET (Q1) and the P-MOSFET (Q2) to be closed in a steady state (meaning that a controlled power control device Q3 of an output stage is reliably saturated and turned on or off). In the conventional circuit, when the PWM or logic signal is changed into active or inactive, the controlled power control device Q3 is turned off and still in saturation, and obviously, the turn-off time and the turn-off delay are both greater than those of the present invention. (2) The control signals driving the N-MOSFET (Q1) and the P-MOSFET (Q2) of the present invention do not require the insertion of dead time protection. (3) The driving N-MOSFET (Q1) and the driving P-MOSFET (Q2) used by the invention only work during state transition (the controlled power control device Q3 of an on or off output stage), and can output peak current with larger amplitude and shorter rising edge and falling edge. (4) The resistance values of the second resistor R2 and the third resistor R3 can be changed to adjust the on and off time of the controlled power control device Q3 of the output stage. (5) The driver circuit pre-stage of the controlled power control device Q3 may be formed using a general purpose driver circuit (e.g., IRS2003, IRS2103, IRS2117, IRS2118, IRS2175, etc.), or may be formed using a split device.
Drawings
In order to clearly illustrate the innovative principles of the present invention and its technical advantages compared with the prior art products, a possible embodiment is illustrated below by way of non-limiting example applying said principles, with the aid of the annexed drawings. In the figure:
FIG. 1(A) is a prior art N-NMOSFET combination;
FIG. 1(B) is a prior art P-PMOSFET combination;
FIG. 1(C) is a prior art P-NMOSFET combination;
FIG. 1(D) is a prior art N-PMOSFET combination;
FIG. 2 is a schematic circuit diagram of a power control driver circuit according to the present invention;
FIG. 3 is a schematic circuit diagram of a second power control driver circuit according to the present invention;
FIG. 4 is a schematic circuit diagram of a third power control driver circuit according to the present invention;
FIG. 5 is a circuit diagram of an exemplary application using a driver IC IRF2003(S) PbF to form a front stage of the driver circuit; q13 and Q23 are respectively a first controlled power control device and a second controlled power control device;
FIG. 6 is a circuit diagram of a prior art exemplary front stage of a driving circuit comprising column devices; q16 and Q26 are respectively a third controlled power control device and a fourth controlled power control device; the circuit is used as a preceding stage of a driving circuit, the on-off time of the circuit is longer, and the driving current is not large enough; obviously cannot be used in high power control devices;
fig. 7 is a circuit diagram of a typical application circuit using a driver integrated circuit IRF2003(S) PbF, and applied to a power control driver circuit of the present invention. Q13 and Q23 are respectively a first controlled power control device and a second controlled power control device;
fig. 8 is a circuit diagram of a drive circuit preceding stage formed by a split device structure (a non-integrated circuit device, or a conventional device) and applied to the drive circuit for power control of the present invention; wherein, Q16 and Q26 are the third and fourth controlled power control devices respectively.
Detailed Description
Example 1
As shown in fig. 2, the power control drive circuit of the present embodiment includes: a drive circuit front stage formed by a drive integrated circuit U1, for controlling the output voltage of its voltage output terminal OUT according to an externally fed PWM signal (or logic signal); an N-MOSFET (Q1) with a gate G connected to the voltage output terminal OUT of the driver IC; a first resistor R1 is arranged between the grid G and the source S of the N-MOSFET (Q1), and the drain D of the N-MOSFET (Q1) is connected with a driving power supply; a P-MOSFET (Q2) with a gate G connected to the voltage output terminal OUT of the driver IC; a second resistor R2 is arranged between the source S of the N-MOSFET (Q1) and the source S of the P-MOSFET (Q2); and a grid electrode G of the controlled power control device Q3 is connected in series with a third resistor R3 and then connected with the source electrode S of the P-MOSFET (Q2), and the source electrode S of the controlled power control device Q3 is connected with the drain electrode D of the P-MOSFET (Q2).
The controlled power control device Q3 is a MOSFET or an IGBT. The driver integrated circuit U1 is a MOSFET driver integrated circuit IRS2003(S) PbF from International Rectifier. The voltage output by the voltage output end OUT is 10-15V, and the peak value of the output current and the peak value of the absorption current are not less than 200 mA.
The resistance value of the first resistor R1 is 500-1K omega, the resistance value of the second resistor R2 is 10-50 omega, and the resistance value of the third resistor R3 is less than 10 omega. In specific implementation, the on and off time of the controlled power control device Q3 of the output stage can be adjusted by changing the resistance values of the second resistor R2 and the third resistor R3.
When the PWM signal (or logic signal) is asserted, the output voltage VOUT =10-15V at the voltage output terminal OUT of the driver ic is applied to the gate of the controlled power control device Q3 via the first resistor R1, the second resistor R2, and the third resistor R3, and forms a current output current I1; the voltage is also directly applied to the grid electrode of the N-MOSFET (Q1), so that the N-MOSFET (Q1) is turned on and is quickly and deeply saturated, and the grid electrode voltage of the controlled power control device Q3 is quickly increased; as the gate voltage of the controlled power control device Q3 rises, the output current I1 gradually decreases until the N-MOSFET (Q1) is turned off when the voltage across the first resistor R1 is smaller than the threshold voltage of the N-MOSFET (Q1), the gate voltage of the controlled power control device Q3 is maintained by the driving integrated circuit, and the controlled power control device Q3 is maintained in a deep saturation region;
when the PWM signal (or logic signal) is changed from active to inactive, the voltage output end OUT is decreased, the grid electrode of the controlled power control device Q3 outputs a sink current I2 to the voltage output end OUT of the driving integrated circuit through the first resistor R1, the second resistor R2 and the third resistor R3, and when the product of the sum of the resistance values of the first resistor R1 and the second resistor R2 and the output sink current I2 is larger than the threshold voltage of the P-MOSFET (Q2), the P-MOSFET (Q2) is quickly saturated and conducted, the grid electrode voltage of the controlled power control device Q3 is quickly decreased, and finally the P-MOSFET (Q2) is disconnected;
the gate voltage of the controlled power control device Q3 is maintained by the driving integrated circuit, and the controlled power control device Q3 can be reliably maintained in the cut-off region because the driving integrated circuit can absorb the current with the peak value not less than 200 mA.
Example 2
On the basis of embodiment 1, the power control drive circuit of the present embodiment has the following modifications:
as shown in fig. 3, the voltage output terminal OUT of the driving integrated circuit is connected in series with the fourth resistor R4, the fifth resistor R5 and the first gate resistor RG1 in sequence and then connected to the gate G of the N-MOSFET (Q1); the junction of the fifth resistor R5 and the first gate resistor RG1 is connected in series with the first resistor R1 and then connected with the source S of the N-MOSFET (Q1); the junction of the fourth resistor R4 and the fifth resistor R5 is connected in series with the second gate resistor RG2 and then connected with the gate G of the P-MOSFET (Q2).
The pin 3 is connected to a driving power supply. When the controlled power control device Q3 is used in the upper bridge, pin 4 is connected to the positive supply of the power stage and pin 5 is the output. When the controlled power control device Q3 is used in the lower bridge, pin 5 is connected to the power supply negative of the power stage and pin 4 is the output.
Further, the power control drive circuit of fig. 4 is a modification of embodiment 2.
Application example 1
The power control driving circuit described in embodiment 1 is applied to form a bridge power control circuit. As shown in fig. 7, the bridge power control circuit includes: a driver integrated circuit U1 for controlling output voltages of a pair of voltage output terminals HO and LO thereof, respectively, according to a pair of PWM signals (or logic signals) HIN and LIN externally input; the pair of voltage output terminals HO and LO are connected to upper and lower bridge driving circuits having the same structure, respectively.
The upper bridge driving circuit includes: an N-MOSFET (Q11) having a gate connected to a first voltage output terminal HO of said driver IC; a first resistor R11 is arranged between the grid G and the source S of the N-MOSFET (Q11), and a power supply VCC of a driving integrated circuit U1 is connected with the drain D of the N-MOSFET (Q11) through a diode D11; the grid G of the P-MOSFET (Q12) is connected with the first voltage output end HO of the driving integrated circuit; a resistor R12 is arranged between the source S of the N-MOSFET (Q11) and the drain D of the P-MOSFET (Q12); a controlled power control device Q13, wherein the grid G of the controlled power control device Q13 is connected with the drain D of the P-MOSFET (Q12) after being connected with a resistor R13 in series, and the source S of the controlled power control device Q13 is connected with the source S of the P-MOSFET (Q12); the source S of the controlled power control device in the upper bridge driving circuit is connected with the drain D of the controlled power control device in the lower bridge driving circuit, and the source S of the controlled power control device in the lower bridge driving circuit is connected with the common end COM of the driving integrated circuit U1.
U1 is an International Rectifier (International Rectifier) MOSFET driver integrated circuit IRS2003(S) PbF. Controlled power control devices Q13 and Q23 in the upper bridge driving circuit and the lower bridge driving circuit form an output stage of the bridge power control circuit.
The on-resistance of the N-MOSFET (Q11) is designated as RDS (ON) Q11, and the on-resistance of the N-MOSFET (Q21) is designated as RDS (ON) Q21. The on-resistance of the P-MOSFET (Q12) is designated as RDS (ON) Q12, and the on-resistance of the P-MOSFET (Q22) is designated as RDS (ON) Q22.
(R12+R13+RDS(ON)Q11)=6Ω，(R22+R23+RDS(ON)Q21)=6Ω，
(R13+RDS(ON)Q12)=1Ω，(R23+RDS(ON)Q22)=1Ω。
When VCC =12V, the maximum current injected by the improved circuit to the gate of the controlled power control device Q3 reaches 2A when the controlled power control device Q3 is turned on (taking MOSFET as an example), and the maximum current absorbed by the gate of the controlled power control device Q3 reaches 12A when the controlled power control device Q3 is turned off.
The improved circuit applied to the invention is already applied to a motor controller with the maximum output power of 10 KW.
Fig. 5 shows a typical application circuit of the MOSFET driver integrated circuit IRS2003(S) PbF, wherein the maximum current injected by IRS2003(S) PbF to the gate of the MOSFET (corresponding to the controlled power control device Q3 of the present embodiment) when the MOSFET is turned on is 130mA, and the maximum current absorbed by IRS2003(S) PbF from the gate of the MOSFET when the MOSFET is turned off is 270 mA. And obviously cannot be used in high power control devices.
Example 3
In addition to embodiment 1, the driving circuit front stage of the present embodiment is configured by using the column device shown in fig. 8, specifically, the driving circuit front stage configured by using the column device on the left side of the dotted line in fig. 8.
In FIG. 8, pins 1 and 5 are connected to a driving power source, which is generally 12V to 15V.
Pin 7 is the lower bridge control signal PWM (or logic signal) input.
Pin 6 is connected to the positive pole of the logic power supply, which is typically 3.3V or 5V.
The pin 8 is connected to the positive pole of the power supply.
D11 and C11 form a bootstrap boost circuit to provide the upper bridge driving power supply.
The drive circuit front stage of MOSFET or IGBT formed by devices in rows or the drive circuit front stage of MOSFET and IGBT special integrated circuit is adopted. The power control device using the MOSFET and the IGBT has positive effects of improving performance and reliability.
It should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And such obvious variations or modifications which fall within the spirit of the invention are intended to be covered by the scope of the present invention.
Claims (1)
1. A power control driver circuit, comprising:
the drive circuit front stage is used for controlling the output voltage of the voltage output end of the drive circuit according to a PWM signal or a logic signal sent from the outside;
an N-MOSFET (Q1), the grid (G) of which is connected with the voltage output end of the front stage of the driving circuit; a first resistor (R1) is arranged between the grid (G) and the source (S) of the N-MOSFET (Q1), and the drain (D) of the N-MOSFET (Q1) is connected with a driving power supply;
a P-MOSFET (Q2), the grid (G) of which is connected with the voltage output end of the front stage of the driving circuit; a second resistor (R2) is arranged between the source (S) of the N-MOSFET (Q1) and the source (S) of the P-MOSFET (Q2);
a controlled power control device (Q3), wherein the grid (G) of the controlled power control device is connected with a third resistor (R3) in series and then connected with the source (S) of the P-MOSFET (Q2), and the source (S) of the controlled power control device (Q3) is connected with the drain (D) of the P-MOSFET (Q2);
the voltage which can be output by the voltage output end of the front stage of the driving circuit is 5V-15V, and the peak values of the output current and the absorbed current are not less than 50 mA;
the voltage output end of the front stage of the driving circuit is sequentially connected in series with a fourth resistor (R4), a fifth resistor (R5) and a second gate resistor (RG 2) and then connected with the gate (G) of a P-MOSFET (Q2);
the junction of the fourth resistor (R4) and the fifth resistor (R5) is connected in series with the first gate resistor (RG 1) and then connected with the gate (G) of the N-MOSFET (Q1);
the junction of the fifth resistor (R5) and the second gate resistor (RG 2) is connected in series with the first resistor (R1) and then connected with the source (S) of the N-MOSFET (Q1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710783471.8A CN107517052B (en) | 2014-07-11 | 2014-07-11 | Power control drive circuit for motor control and power conversion |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710783471.8A CN107517052B (en) | 2014-07-11 | 2014-07-11 | Power control drive circuit for motor control and power conversion |
| CN201410331421.2A CN105099420B (en) | 2014-07-11 | 2014-07-11 | Power Control drive circuit |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201410331421.2A Division CN105099420B (en) | 2014-07-11 | 2014-07-11 | Power Control drive circuit |
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| CN107517052A CN107517052A (en) | 2017-12-26 |
| CN107517052B true CN107517052B (en) | 2020-06-23 |
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| CN201710783471.8A Active CN107517052B (en) | 2014-07-11 | 2014-07-11 | Power control drive circuit for motor control and power conversion |
| CN201710783448.9A Active CN107579731B (en) | 2014-07-11 | 2014-07-11 | Power control driving circuit and its working method for motor control |
| CN201710783459.7A Active CN107517051B (en) | 2014-07-11 | 2014-07-11 | Bridge type power control circuit for motor control and working method thereof |
| CN201410331421.2A Expired - Fee Related CN105099420B (en) | 2014-07-11 | 2014-07-11 | Power Control drive circuit |
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| CN201710783448.9A Active CN107579731B (en) | 2014-07-11 | 2014-07-11 | Power control driving circuit and its working method for motor control |
| CN201710783459.7A Active CN107517051B (en) | 2014-07-11 | 2014-07-11 | Bridge type power control circuit for motor control and working method thereof |
| CN201410331421.2A Expired - Fee Related CN105099420B (en) | 2014-07-11 | 2014-07-11 | Power Control drive circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US10090792B2 (en) * | 2016-12-08 | 2018-10-02 | Ford Global Technologies, Llc | Self-balancing parallel power devices with a temperature compensated gate driver |
| CN108831880A (en) * | 2018-08-07 | 2018-11-16 | 成都赛力康电气有限公司 | A kind of DBC substrate for power electronic devices MOS module |
| CN110661404A (en) * | 2019-09-30 | 2020-01-07 | 北京机械设备研究所 | IGBT single power supply driving circuit based on bootstrap mode |
| CN111404526B (en) * | 2020-03-19 | 2021-12-03 | 华中科技大学 | Programmable high-precision dynamic GaN driving circuit and application thereof |
| CN113659972B (en) * | 2021-09-13 | 2024-01-05 | 复旦大学 | Driving circuit and electronic device |
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| CN2255696Y (en) * | 1995-02-15 | 1997-06-04 | 陈亚宁 | Driving circuit for simple high-efficiency isolation-type insulated gate high-power device |
| JP3773863B2 (en) * | 2001-07-19 | 2006-05-10 | 三菱電機株式会社 | Semiconductor device |
| CN102541232B (en) * | 2010-12-29 | 2014-12-10 | 鸿富锦精密工业（深圳）有限公司 | Buck conversion circuit |
| CN203071864U (en) * | 2013-01-21 | 2013-07-17 | 珠海格力电器股份有限公司 | Single-phase AC motor and its speed control circuit |
| CN103414333B (en) * | 2013-07-05 | 2015-10-21 | 电子科技大学 | A kind of active power factor correction controller |
| CN103795385A (en) * | 2014-02-24 | 2014-05-14 | 南京航空航天大学 | Power tube drive method and circuit, and direct-current solid power controller |
| CN204068909U (en) * | 2014-07-11 | 2014-12-31 | 唐险峰 | Power control drive circuit |
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- 2014-07-11 CN CN201711073590.0A patent/CN107733210B/en active Active
- 2014-07-11 CN CN201710783471.8A patent/CN107517052B/en active Active
- 2014-07-11 CN CN201710783448.9A patent/CN107579731B/en active Active
- 2014-07-11 CN CN201710783459.7A patent/CN107517051B/en active Active
- 2014-07-11 CN CN201410331421.2A patent/CN105099420B/en not_active Expired - Fee Related
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| JPH0292017A (en) * | 1988-09-28 | 1990-03-30 | Nec Corp | Output circuit |
| US5949273A (en) * | 1996-07-12 | 1999-09-07 | Semikron Elektronik Gmbh | Short circuit protection for parallel connected devices |
| CN1588799A (en) * | 2004-07-09 | 2005-03-02 | 清华大学 | Driving protective circuit for inverse resistance type insulated gate bipolar transistor |
| CN101355352A (en) * | 2007-07-26 | 2009-01-28 | 上海空间电源研究所 | Driver circuit for P type power MOS switch tube |
| CN102412711A (en) * | 2011-11-22 | 2012-04-11 | 常熟市董浜镇华进电器厂 | High-speed driving circuit for power MOS (Metal-Oxide Semiconductor) tube |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107517051A (en) | 2017-12-26 |
| CN107517051B (en) | 2020-07-10 |
| CN105099420B (en) | 2017-12-15 |
| CN107579731B (en) | 2019-11-22 |
| CN107733210A (en) | 2018-02-23 |
| CN107733210B (en) | 2019-09-06 |
| CN107517052A (en) | 2017-12-26 |
| CN105099420A (en) | 2015-11-25 |
| CN107579731A (en) | 2018-01-12 |
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