CN107508460A - A kind of boost capacitor charging circuit with under-voltage protection - Google Patents

A kind of boost capacitor charging circuit with under-voltage protection Download PDF

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Publication number
CN107508460A
CN107508460A CN201710783955.2A CN201710783955A CN107508460A CN 107508460 A CN107508460 A CN 107508460A CN 201710783955 A CN201710783955 A CN 201710783955A CN 107508460 A CN107508460 A CN 107508460A
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China
Prior art keywords
pmos
nmos tube
boost capacitor
boot
connects
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CN201710783955.2A
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CN107508460B (en
Inventor
明鑫
魏秀凌
张宣
辛杨立
高笛
王卓
张波
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/34—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering
    • H02J7/345—Parallel operation in networks using both storage and other dc sources, e.g. providing buffering using capacitors as storage or buffering devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection

Abstract

A kind of boost capacitor charging circuit with under-voltage protection, belongs to electronic circuit technology field.Detection charge loop is used to detect boost capacitor CbootBoth ends pressure difference simultaneously gives boost capacitor CbootCharging, eliminate the problem of traditional mode needs to design loop compensation using low pressure difference linear voltage regulator LDO to boost capacitor charging, it is not necessary to plug-in bulky capacitor, save chip cost and area, it it also avoid after being in light-load mode for a long time, boost capacitor C when exitingbootThe problem of upper voltage is inadequate；Current comparator is used to realize under-voltage protection function, and boost capacitor C is given using low pressure difference linear voltage regulator LDO compared to traditionbootThe mode of charging, charging modes of the invention are simpler, enormously simplify the design difficulty of circuit.

Description

A kind of boost capacitor charging circuit with under-voltage protection
Technical field
The invention belongs to electronic circuit technology field, and in particular to a kind of band under-voltage protection for not needing plug-in bulky capacitor The boost capacitor charging circuit of function, suitable for the Buck converters that power tube is NMOS tube.
Background technology
Buck converters just seem outstanding as a type most-often used in DC-DC converter, the driving of its power tube To be important.As shown in figure 1, NMOS Buck converters are used for power tube, including power tube MN, drive module, boosting electricity Hold Cboot, diode D, inductance, electric capacity Co and resistance RL, power tube MN driving when require safe opening, it is necessary to by power tube MN grid driving voltage one gate source voltage V of lifting on the basis of the voltage at switching node SWGS, the realization of this lifting voltage Usually provided by boosting (boot) electric capacity.When power tube MN is turned off, switching node SW ground connection, low pressure difference linearity voltage stabilizing Device LDO gives boost capacitor CbootCharging, ensure boost capacitor CbootOn the enough power tube MN of pressure difference can fully open next time； When power tube MN is opened, switching node SW connects output, (i.e. booster voltage C at node BSTbootTop crown) voltage is elevated Arrive：VBST=VSW+Vboot, Schottky diode now turns off, and low pressure difference linear voltage regulator LDO no longer gives boost capacitor CbootFill Electricity.
But give boost capacitor C for traditional this use low pressure difference linear voltage regulator LDObootThe mode of charging, is deposited In following drawback：
1st, low pressure difference linear voltage regulator LDO complex designing, due to boost capacitor CbootThe conduct when power tube MN is turned off Low pressure difference linear voltage regulator LDO output capacitance and output when opening with low pressure difference linear voltage regulator LDO disconnects, make low voltage difference Linear voltage regulator LDO output limit change very greatly, it is necessary to plug-in bulky capacitor Ce guarantee loop stability, add chip into This.
2nd, when Buck circuits enter light-load mode, power tube MN is turned off and the turn-off time is very long, now at switching node SW Voltage be Vout, boost capacitor CbootUpper voltage may drop to VLDO-VD-Vout(VDFor diode D pressure drop), if Vout voltage is too high, can be due to boost capacitor C when system, which exits underloading, needs to be again turned on power tube MNbootUpper pressure difference is not Enough cause power tube MN not fully open, lose the efficiency of system (when i.e. output voltage is very high, because exiting underloading When boost capacitor on pressure drop it is inadequate, power tube MN can be caused can not now to fully open).In order to prevent boost capacitor CbootOn Because electric leakage causes pressure difference is too small can not fully open power tube MN, it is necessary to design under-voltage protecting circuit and logic, and it is traditional The logical design using low pressure difference linear voltage regulator LDO charge modes can be more complicated.
3rd, under frequency applications, as shown in figure 1, Schottky diode D1 both ends pressure drops VD1By low pressure difference linear voltage regulator LDO Output voltage (generally 5V) limitation, its both ends electric currentIt can be restricted so that boost capacitor CbootBoth ends pressure drop Ideal value can not be charged to, efficiency is reduced so as to cause upper tube can not be fully on.
The content of the invention
For above-mentioned weak point, the present invention proposes a kind of boost capacitor charging circuit with under-voltage protection, suitable for work( Rate pipe is the decompression Buck comparators of NMOS tube.
The technical scheme is that：
A kind of boost capacitor charging circuit with under-voltage protection, including current comparator and detection charge loop,
The detection charge loop includes operational amplifier, power diode D2, first resistor R1, second resistance R2, the Three resistance R3, the first NMOS tube MN1, the first PMOS MP1 and the 4th PMOS MP4,
The inverting input of operational amplifier connects the first reference voltage V ref, and its output end connects the 4th PMOS MP4 Grid, the 4th PMOS MP4 source electrode connects input voltage vin；
Power diode D2 negative electrode connects the 4th PMOS MP4 drain electrode, and its anode connects the boost capacitor Cboot Top crown and source electrode by connecting the first PMOS MP1 after first resistor R1；
First PMOS MP1 grid connects the boost capacitor CbootBottom crown, its connection 3rd resistor R3 that drains One end and the first NMOS tube MN1 drain electrode；
The second resistance R2 one end connection 3rd resistor R3 other end, the first NMOS tube MN1 source electrode and operation amplifier The in-phase input end of device, its other end ground connection；
The current comparator includes the second NMOS tube MN2, the 3rd NMOS tube MN3, the second PMOS MP2, the 3rd PMOS Pipe MP3, the first phase inverter INV1, the second phase inverter INV2, the 4th resistance Rf and the first electric capacity Cf,
First NMOS tube MN1 drain electrode, other end connection in 4th resistance Rf one end connection detection charge loop 3rd NMOS tube MN3 grid and by being grounded after the first electric capacity Cf；
Second PMOS MP2 grid leak short circuit and the leakage for connecting the 3rd PMOS MP3 grid and the second NMOS tube MN2 Pole, its source electrode connect the 3rd PMOS MP3 source electrode；
Second NMOS tube MN2 grid connects the second reference voltage V ref1, its source ground；
3rd NMOS tube MN3 the 3rd PMOS MP3 of drain electrode connection drain electrode simultaneously passes through the first phase inverter INV1 and second The grid of the first NMOS tube MN1 in the detection charge loop, its source ground are connected after phase inverter INV2 cascaded structure.
Beneficial effects of the present invention are：By detecting boost capacitor CbootPressure difference to give boost capacitor CbootCharging, removes from The problem of traditional mode needs to design loop compensation using low pressure difference linear voltage regulator LDO to boost capacitor charging, it is not necessary to Plug-in bulky capacitor, chip cost and area are saved, it also avoid after being in light-load mode for a long time, boost capacitor when exiting CbootThe problem of upper voltage is inadequate；There is under-voltage monitoring function simultaneously, compared to tradition using low pressure difference linear voltage regulator LDO to liter Voltage capacitance CbootThe mode of charging, charging modes of the invention are simpler, enormously simplify the design difficulty of circuit.
Brief description of the drawings
Fig. 1 gives boost capacitor C to be traditional using low pressure difference linear voltage regulator LDObootThe topological diagram of charging.
Fig. 2 is the physical circuit figure of the boost capacitor charging circuit provided by the invention with under-voltage protection.
Embodiment
The present invention is described in detail below in conjunction with the accompanying drawings.
The circuit of the present invention is as shown in Fig. 2 charging circuit provided by the invention, for the decompression that power tube is NMOS tube Boost capacitor C in Buck convertersbootCharging, detection charge loop are used to detect boost capacitor CbootBoth ends pressure difference simultaneously gives liter Voltage capacitance CbootCharging, including operational amplifier, power diode D2, first resistor R1, second resistance R2,3rd resistor R3, First NMOS tube MN1, the first PMOS MP1 and the 4th PMOS MP4, the inverting input of operational amplifier connect the first benchmark Voltage Vref, its output end connect the 4th PMOS MP4 grid, and the 4th PMOS MP4 source electrode connects the defeated of Buck converters Enter voltage Vin；Power diode D2 negative electrode connects the 4th PMOS MP4 drain electrode, its anode connection boost capacitor Cboot's Top crown and the source electrode by connecting the first PMOS MP1 after first resistor R1；First PMOS MP1 grid connection boosting electricity Hold CbootBottom crown, its connection 3rd resistor R3 that drains one end and the first NMOS tube MN1 drain electrode；The one of second resistance R2 The end connection 3rd resistor R3 other end, the first NMOS tube MN1 source electrode and the in-phase input end of operational amplifier, its other end Ground connection.
Current comparator is used to realize under-voltage protection function, including the second NMOS tube MN2, the 3rd NMOS tube MN3, second PMOS MP2, the 3rd PMOS MP3, the first phase inverter INV1, the second phase inverter INV2, the 4th resistance Rf and the first electric capacity Cf, First NMOS tube MN1 drain electrode in 4th resistance Rf one end connecting detection charge loop, the other end connect the 3rd NMOS tube MN3 Grid and by being grounded after the first electric capacity Cf；Second PMOS MP2 grid leak short circuit and the grid for connecting the 3rd PMOS MP3 With the second NMOS tube MN2 drain electrode, its source electrode connects the 3rd PMOS MP3 source electrode；Second NMOS tube MN2 grid connection the Two reference voltage Vref1, its source ground；3rd NMOS tube MN3 the 3rd PMOS MP3 of drain electrode connection drain electrode simultaneously passes through the After one phase inverter INV1 and the second phase inverter INV2 cascaded structure in connecting detection charge loop the first NMOS tube MN1 grid Pole, its source ground.
As shown in Fig. 2 work as boost capacitor CbootWhen upper pressure difference is enough, the voltage VFB of the in-phase input end of operational amplifier The drain terminal voltage VA that first reference voltage V ref, A point is the first NMOS tube MN1 is clamped to by negative-feedback and is higher than the second reference voltage Vref1, B point are that the first NMOS tube MN1 grid voltage VB is pulled low, VB output low levels, the first NMOS tube MN1 shut-offs.This When, flow through the first PMOS MP1 electric current I1For：
Wherein upFor the mobility in hole, Cox is PMOS unit area gate capacitance, and Vthp is the threshold value electricity of PMOS Pressure,For the first PMOS MP1 breadth length ratio.Derived more than, boost capacitor CbootBoth ends pressure difference Vboot can lead to Cross and set the first reference voltage V ref, first resistor R1 and second resistance R2 to set, but be in the first reference voltage V ref Non-linear relation.If necessary to approximate existing relation, Vboot voltages that can be as needed, increase first resistor R1, second Resistance R2 and the first PMOS MP1 breadth length ratiosThe first PMOS MP1 is operated in subthreshold region, now there is following relation：
Now, boost capacitor CbootBoth ends pressure difference Vboot and the first reference voltage V ref is approximately linear relationship.
As shown in Fig. 2 when system is in light-load mode for a long time, now power tube MN is closed for a long time, if now gone out Existing boost capacitor CbootThe too small situation of upper pressure difference, at this moment in order to ensure that the efficiency of system is not lost, it is necessary to start under-voltage protection Function, allow system in this case without opening power tube MN action.A point voltages VA is by the electricity of the 4th resistance Rf and first Hold the grid end that the filter network that Cf is formed is coupled to the 3rd NMOS tube MN3, as boost capacitor CbootUpper voltage is reduced to under-voltage guarantor During shield value, A point voltages VA is less than the second reference voltage V ref1, flow through the 3rd NMOS tube MN3 electric current be less than flow through the 3rd PMOS Pipe MP3 electric current, B point voltages VB turns over height, and after two-stage phase inverter, B point voltages VB also makes the first NMOS tube for high level MN1 is opened, and A point voltages VA continues to reduce, and accelerates the upset of B points, plays a hysteresis effect.
When triggering under-voltage protection function：
Vref1=VA=I1(R2+R3) (5)
So now boost capacitor CbootUpper pressure difference is：
As boost capacitor CbootAfter upper voltage is begun to ramp up, now need to exit under-voltage protection：
Amount of hysteresis is：
As known from the above, required minimum Vboot voltages can be fully opened according to power tube MN to select the ginseng of correlation Number and setting amount of hysteresis.
The present invention devises a detection boost capacitor CbootPressure difference gives boost capacitor CbootCharging, while have under-voltage The circuit of monitoring function.Power diode D2 both ends pressure drops in the present invention do not have Schottky diode D1 both ends in traditional form Limited by low pressure difference linear voltage regulator LDO output voltages, can also in frequency applications so as to which its electric current can reach very big By boost capacitor CbootOn voltage be charged to ideal value.
Advantages of the present invention, which first consists in, to be eliminated traditional mode and is filled using low pressure difference linear voltage regulator LDO to boost capacitor The problem of electricity needs to design loop compensation, while plug-in bulky capacitor is also avoided the need for, chip cost and area are saved, next is avoided After being in light-load mode for a long time, the problem of when exiting voltage is inadequate in boost capacitor.Under-voltage protecting circuit is set simultaneously Meter and logic are also simpler to boost capacitor charging modes using low pressure difference linear voltage regulator LDO than tradition, enormously simplify circuit Design difficulty.
One of ordinary skill in the art will be appreciated that embodiment described here is to aid in reader and understands this hair Bright principle, it should be understood that protection scope of the present invention is not limited to such especially statement and embodiment.This area Those of ordinary skill can make according to these technical inspirations disclosed by the invention various does not depart from the other each of essence of the invention The specific deformation of kind and combination, these deform and combined still within the scope of the present invention.

Claims (1)

1. a kind of boost capacitor charging circuit with under-voltage protection, it is characterised in that including current comparator and detection charging ring Road,
It is described detection charge loop include operational amplifier, power diode (D2), first resistor (R1), second resistance (R2), 3rd resistor (R3), the first NMOS tube (MN1), the first PMOS (MP1) and the 4th PMOS (MP4),
The inverting input of operational amplifier connects the first reference voltage (Vref), and its output end connects the 4th PMOS (MP4) Grid, the source electrode of the 4th PMOS (MP4) connects input voltage (Vin)；
The negative electrode of power diode (D2) connects the drain electrode of the 4th PMOS (MP4), and its anode connects the boost capacitor (Cboot) Top crown and connect the first PMOS (MP1) source electrode afterwards by first resistor (R1)；
The grid of first PMOS (MP1) connects the boost capacitor (Cboot) bottom crown, its drain connection 3rd resistor (R3) One end and the first NMOS tube (MN1) drain electrode；
The other end of one end connection 3rd resistor (R3), the source electrode of the first NMOS tube (MN1) and the computing of second resistance (R2) are put The in-phase input end of big device, its other end ground connection；
The current comparator includes the second NMOS tube (MN2), the 3rd NMOS tube (MN3), the second PMOS (MP2), the 3rd PMOS (MP3), the first phase inverter (INV1), the second phase inverter (INV2), the 4th resistance (Rf) and the first electric capacity (Cf),
The drain electrode of first NMOS tube (MN1), other end connection in one end connection detection charge loop of 4th resistance (Rf) The grid of 3rd NMOS tube (MN3) is simultaneously grounded afterwards by the first electric capacity (Cf)；
The grid leak short circuit of second PMOS (MP2) simultaneously connects the grid of the 3rd PMOS (MP3) and the leakage of the second NMOS tube (MN2) Pole, its source electrode connect the source electrode of the 3rd PMOS (MP3)；
The grid of second NMOS tube (MN2) connects the second reference voltage (Vref1), its source ground；
The drain electrode of 3rd NMOS tube (MN3) connects the drain electrode of the 3rd PMOS (MP3) and by the first phase inverter (INV1) and the The grid of the first NMOS tube (MN1) in the detection charge loop, its source electrode are connected after the cascaded structure of two phase inverters (INV2) Ground connection.
CN201710783955.2A 2017-09-04 2017-09-04 A kind of boost capacitor charging circuit with under-voltage protection Active CN107508460B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113849029A (en) * 2021-09-26 2021-12-28 电子科技大学 Under-voltage detection circuit of self-biased reference source

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160065072A1 (en) * 2014-08-27 2016-03-03 Chengdu Monolithic Power Systems Co., Ltd. Power converter with bootstrap circuit
CN105450019A (en) * 2016-01-20 2016-03-30 电子科技大学 A drive circuit used for a DC-DC converter
CN105915042A (en) * 2016-05-27 2016-08-31 电子科技大学 Soft start and soft shutoff circuit for Buck converters

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160065072A1 (en) * 2014-08-27 2016-03-03 Chengdu Monolithic Power Systems Co., Ltd. Power converter with bootstrap circuit
CN105450019A (en) * 2016-01-20 2016-03-30 电子科技大学 A drive circuit used for a DC-DC converter
CN105915042A (en) * 2016-05-27 2016-08-31 电子科技大学 Soft start and soft shutoff circuit for Buck converters

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113849029A (en) * 2021-09-26 2021-12-28 电子科技大学 Under-voltage detection circuit of self-biased reference source
CN113849029B (en) * 2021-09-26 2022-08-26 电子科技大学 Under-voltage detection circuit of self-biased reference source

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