CN107507822B - Array substrate, preparation method thereof and display device - Google Patents
Array substrate, preparation method thereof and display device Download PDFInfo
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- CN107507822B CN107507822B CN201710735340.2A CN201710735340A CN107507822B CN 107507822 B CN107507822 B CN 107507822B CN 201710735340 A CN201710735340 A CN 201710735340A CN 107507822 B CN107507822 B CN 107507822B
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Abstract
The embodiment of the invention provides an array substrate, a preparation method thereof and a display device, relates to the technical field of display, and aims to solve the problem that the height of the upper surface of the array substrate at a marked pattern position is uneven due to the thickness of the marked pattern; and then solve in the process of carrying out the rubbing orientation to the array substrate, when locating through the mark pattern, lead to the problem that the rubbing cloth warp even damaged to improve display effect. The array substrate comprises a mark pattern of a first subarea in a mark area of the array substrate and an insulating layer; in the mark region, the insulating layer is arranged in a second subregion except the first subregion, and the difference between the thickness of the mark pattern and the thickness of the insulating layer is smaller than the thickness of the mark pattern; or, in the mark region, the insulating layer covers the mark pattern, and the difference between the sum of the thickness of the part of the insulating layer located in the first sub-region and the mark pattern and the thickness of the part of the insulating layer located in the second sub-region is smaller than the thickness of the mark pattern.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a preparation method of the array substrate and a display device.
Background
In the case of a liquid crystal display panel, in order to facilitate alignment of an array substrate and a cell substrate when the array substrate is manufactured, as shown in fig. 1, a Mark pattern (Mark)11 is formed in a non-display region at the same time as a gate electrode is formed, and then a gate insulating film 12 and a passivation film 13 covering the Mark pattern 11 are formed on a base substrate.
However, since the mark pattern 11 has a certain thickness, a step is formed at a position where the mark pattern 11 is located in the non-display region, and when the rubbing roller is used to rub and orient the array substrate, the rubbing cloth on the rubbing roller is easily deformed or damaged when passing through the step, and the deformed or damaged rubbing cloth passes through the display region of the array substrate, which affects formation of the alignment layer groove of the array substrate and subsequent dropping of the liquid crystal.
Disclosure of Invention
The embodiment of the invention provides an array substrate, a preparation method thereof and a display device, aiming at solving the problem that the upper surface of the array substrate is uneven at the position of a mark pattern due to the thickness of the mark pattern; and then solve in the process of carrying out the rubbing orientation to the array substrate, when locating through the mark pattern, lead to the problem that the rubbing cloth warp even damaged to improve display effect.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
in a first aspect, an array substrate is provided, which includes a mark pattern located in a first sub-area of a mark area of the array substrate, and further includes an insulating layer; in the mark region, the insulating layer is arranged in a second subregion except the first subregion, and the difference between the thickness of the mark pattern and the thickness of the insulating layer is smaller than the thickness of the mark pattern; or, in the mark region, the insulating layer covers the mark pattern, and the difference between the sum of the thicknesses of the part of the insulating layer located in the first sub-region and the mark pattern and the thickness of the part of the insulating layer located in the second sub-region is smaller than the thickness of the mark pattern.
Preferably, the insulating layer is a layer; or the insulating layer comprises a first insulating layer and a second insulating layer, the first insulating layer covers the mark pattern and is arranged in the second subarea, and the second insulating layer is arranged in the second subarea and is positioned on one side of the second insulating layer, which is deviated from the substrate.
Further preferably, the insulating layer is a gate insulating layer; or, the first insulating layer is a gate insulating layer, and the second insulating layer is a passivation layer.
Further preferably, the thickness of the gate insulating layer is equal to the thickness of the mark pattern; alternatively, the passivation layer has a thickness equal to that of the mark pattern.
In a second aspect, a display device is provided, which includes the array substrate of the first aspect.
In a third aspect, a method for preparing an array substrate is provided, the method including:
forming a metal layer on a substrate, the metal layer comprising: and the mark pattern is positioned in the first subarea of the array substrate mark area.
Forming an insulating layer on the substrate provided with the metal layer, the insulating layer including: the insulating layer is positioned on the part of the second subregion, and is not arranged on the first subregion; wherein a difference between a thickness of the mark pattern and a thickness of the insulating layer is smaller than a thickness of the mark pattern; the second sub-area is an area other than the first sub-area in the mark area.
Preferably, the forming an insulating layer on the substrate base plate provided with the metal layer specifically includes:
forming a first insulating layer film on the substrate base plate provided with the metal layer, and forming a first photoresist pattern above the first insulating layer film, wherein the first photoresist pattern is positioned outside the first subregion and at least arranged in the second subregion.
And forming a second insulating layer film on the substrate base plate on which the first photoresist pattern is formed, and forming a second photoresist pattern above the second insulating layer film, wherein the second photoresist pattern is positioned outside the first subregion and at least arranged in the second subregion.
And etching the second insulating layer film and the first insulating layer film of the first subarea.
And stripping the first photoresist pattern.
In a fourth aspect, a method for manufacturing an array substrate is provided, the method including:
forming a metal layer on a substrate, the metal layer comprising: and the mark pattern is positioned in the first subarea of the array substrate mark area.
Forming an insulating layer on the substrate provided with the metal layer, the insulating layer including: a portion located at the marking region; the difference between the sum of the thicknesses of the part of the insulating layer positioned in the first sub-area and the mark pattern and the thickness of the part of the insulating layer positioned in the second sub-area is smaller than the thickness of the mark pattern; the second sub-area is an area other than the first sub-area in the mark area.
Preferably, the forming an insulating layer on the substrate provided with the metal layer specifically includes:
and sequentially forming a first insulating layer film and a second insulating layer film on the substrate base plate provided with the metal layer, and forming photoresist above the second insulating layer film.
Exposing the photoresist by using a half-tone mask plate, and developing to form a photoresist semi-reserved part, a photoresist completely removed part and a photoresist completely reserved part; the photoresist semi-reserved part corresponds to the first sub-area, the photoresist completely removed part corresponds to a via hole to be formed on the array substrate, and the photoresist completely reserved part corresponds to other areas of the array substrate.
And etching the first insulating layer film and the second insulating layer film corresponding to the completely removed parts of the photoresist to form the via hole.
And removing the photoresist semi-reserved part by adopting an ashing process to form a third photoresist pattern.
And etching the second insulating film of the first sub-area.
And stripping the third photoresist pattern.
Preferably, the forming an insulating layer on the substrate provided with the metal layer specifically includes:
and sequentially forming a first insulating layer film and a second insulating layer film on the substrate base plate provided with the metal layer, and forming a fourth photoresist pattern above the second insulating layer film, wherein the fourth photoresist pattern is positioned outside the first subarea and at least arranged in the second subarea.
And etching the second insulating layer film of the first sub-area.
And stripping the fourth photoresist pattern.
In the marking area 100, the difference between the thickness of the marking pattern 11 located in the first sub-area 101 and the thickness of the insulating layer 20 located in the second sub-area 102 is smaller than the thickness of the marking pattern 11; alternatively, the difference between the sum of the thicknesses of the mark pattern 11 and the portion of the insulating layer 20 located in the first sub-region 101 and the insulating layer 20 located in the second sub-region 102 is smaller than the thickness of the mark pattern 11 by making the insulating layer 20 cover the mark pattern 11. Therefore, the problem that the height of the upper surface of the array substrate at the position of the mark pattern 11 is uneven due to the thickness of the mark pattern 11 can be solved, the problem that the formation of the alignment layer groove of the array substrate and the subsequent dripping of liquid crystal are influenced due to the fact that the rubbing cloth is deformed or even damaged when passing through the position of the mark pattern 11 in the process of rubbing and aligning the array substrate is solved, the Mura display phenomenon is improved, and the display effect is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic side view of a marking pattern according to the prior art;
fig. 2(a) is a schematic side view of an array substrate according to an embodiment of the present invention;
fig. 2(b) is a schematic side view of an array substrate according to an embodiment of the invention;
fig. 2(c) is a schematic side view of an array substrate according to an embodiment of the present invention;
fig. 3 is a schematic top view of an array substrate according to an embodiment of the invention;
FIG. 4 is a schematic top view of a relationship between a mark region and a mark pattern according to an embodiment of the present invention;
fig. 5(a) is a schematic side view of an array substrate according to an embodiment of the present invention;
fig. 5(b) is a schematic side view of an array substrate according to an embodiment of the present invention;
fig. 5(c) is a schematic side view illustrating a sixth exemplary embodiment of an array substrate;
fig. 6(a) is a schematic side view illustrating an array substrate according to an embodiment of the present invention;
fig. 6(b) is a schematic side view of an array substrate according to an embodiment of the present invention;
fig. 6(c) is a schematic side view illustrating an array substrate according to an embodiment of the present invention;
fig. 7 is a first schematic flow chart illustrating a process of manufacturing an array substrate according to an embodiment of the present invention;
fig. 8 is a first schematic view illustrating a first process of manufacturing an array substrate according to an embodiment of the present invention;
fig. 9 is a second schematic flow chart illustrating a process of manufacturing an array substrate according to an embodiment of the present invention;
fig. 10(a) is a schematic view of a second process for manufacturing an array substrate according to an embodiment of the present invention;
fig. 10(b) is a schematic view of a third process for manufacturing an array substrate according to an embodiment of the present invention;
fig. 10(c) is a fourth schematic view illustrating a process of manufacturing an array substrate according to an embodiment of the present invention;
fig. 10(d) is a schematic view of a fifth process for manufacturing an array substrate according to an embodiment of the present invention;
fig. 11 is a third schematic flow chart illustrating a process of manufacturing an array substrate according to an embodiment of the present invention;
fig. 12 is a fourth schematic flowchart illustrating a process of manufacturing an array substrate according to an embodiment of the present invention;
fig. 13(a) is a sixth schematic view illustrating a process of manufacturing an array substrate according to an embodiment of the present invention;
fig. 13(b) is a seventh schematic view illustrating a process of manufacturing an array substrate according to an embodiment of the present invention;
fig. 13(c) is a schematic view of an eighth exemplary process for manufacturing an array substrate according to an embodiment of the present invention;
fig. 13(d) is a schematic diagram illustrating a process of manufacturing an array substrate according to an embodiment of the present invention;
fig. 13(e) is a schematic view showing a process of manufacturing an array substrate according to an embodiment of the present invention;
fig. 14 is a fifth flowchart illustrating a process of manufacturing an array substrate according to an embodiment of the present invention.
Reference numerals:
11-a pattern of marks; 12-a gate insulating layer film; 13-a passivation layer film; 20-an insulating layer; 21-a first insulating layer; 211-a first insulating layer film; 22-a second insulating layer; 221-a second insulating layer film; 31 — a first photoresist pattern; 32-a second photoresist pattern; 33-a third photoresist pattern; 34-a fourth photoresist pattern; 100-a mark area; 101-a first sub-region; 102-second sub-region.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides an array substrate, as shown in fig. 2(a), 2(b), and 2(c), including a mark pattern 11 located in a first sub-area 101 in a mark area 100 of the array substrate, and further including an insulating layer 20; in the mark region 100, the insulating layer 20 is disposed in the second sub-region 102 except the first sub-region 101, and a difference between a thickness of the mark pattern 11 and a thickness of the insulating layer 20 is smaller than a thickness of the mark pattern 11.
Wherein, when the array substrate is applied to a display panel, the array substrate includes a metal layer, the metal layer includes: the mark pattern 11, a gate electrode, a gate line, and further, a common electrode line may be included. The mark pattern 11, the grid electrode and the grid line can be formed by the same composition process; alternatively, the mark pattern 11, the gate electrode, the gate line, and the common electrode line may be formed through the same patterning process.
First, the specific pattern of the mark pattern 11 is different depending on the production line, and the specific pattern of the mark pattern 11 is not limited herein, for example, the specific pattern of the mark pattern 11 may be H-shaped as shown in fig. 3.
Secondly, the position and number of the mark patterns 11 are not limited as long as the mark patterns 11 are located in the non-display area of the array substrate and normal arrangement of other patterns in the non-display area is not affected. Of course, as shown in fig. 3, the array substrate at least includes 4 mark patterns 11, and the mark patterns are respectively distributed at 4 top corners of the array substrate.
Here, when the array substrate includes a plurality of mark patterns 11, specific patterns of the plurality of mark patterns 11 may be the same or different.
Third, as shown in fig. 4, the mark area 100 refers to: an area surrounding the outer edge of the marker pattern 11 and excluding the other light shielding pattern in the non-display area. Wherein the other light-shielding pattern may be a gate line lead, a data line lead, or the like. Of course, in the embodiment of the invention, the mark area 100 should be larger than the area of the mark pattern 11 on the basis of surrounding the outer edge of the mark pattern 11, so that the difference between the thickness of the mark pattern 11 and the thickness of the insulating layer 20 is smaller than the thickness of the mark pattern 11 by adjusting the thickness relationship between the insulating layer 20 located in the second sub-region 102 and the mark pattern 11 located in the first sub-region 101, thereby improving the problem that the upper surface of the array substrate is uneven at the position of the mark pattern 11 due to the thickness of the mark pattern 11.
Here, the upper surface of the array substrate means: the surface on the side where the marker pattern 11 is provided.
Fourth, the thickness of the mark pattern 11 and the thickness of the insulating layer 20 are not limited as long as the difference between the thickness of the mark pattern 11 and the thickness of the insulating layer 20 in the mark region 100 is smaller than the thickness of the mark pattern 11.
For example, as shown in fig. 2(a), the thickness of the mark pattern 11 is equal to the thickness of the insulating layer 20; as shown in fig. 2(b), the thickness of the mark pattern 11 may be larger than that of the insulating layer 20; as shown in fig. 2(c), the thickness of the mark pattern 11 may be smaller than that of the insulating layer 20.
Of course, if the array substrate is applied to a display panel, the actual thickness of the display panel, that is, the thicknesses of the mark pattern 11 and the insulating layer 20, should not exceed the distance between the array substrate and the opposite box substrate in the display panel. Illustratively, the thickness of the mark pattern 11 and the insulating layer 20 are both
In the mark area 100, the difference between the thickness of the mark pattern 11 located in the first sub-area 101 and the thickness of the insulating layer 20 located in the second sub-area 102 is smaller than the thickness of the mark pattern 11, so that the problem that the upper surface of the array substrate is uneven at the position of the mark pattern 11 due to the thickness of the mark pattern 11 can be solved, the problem that the formation of the alignment layer groove of the array substrate and the subsequent liquid crystal dripping are affected due to the deformation and even breakage of a rubbing cloth when the rubbing cloth passes through the position of the mark pattern 11 in the process of rubbing and aligning the array substrate is solved, the display Mura phenomenon is improved, and the display effect is improved.
Preferably, as shown in fig. 2(a), 2(b), and 2(c), the insulating layer 20 is a single layer; when the array substrate is applied to a display panel, the insulating layer 20 is a gate insulating layer (GI).
The material of the gate insulating layer may be silicon nitride (SiN)x)。
In the embodiment of the invention, the insulating layer 20 is arranged as one layer, so that the process is simple and easy to operate; when the array substrate is applied to a display panel, the mark pattern 11 may be formed by the same patterning process as a gate electrode, a gate line, and the like, and the insulating layer 20 may be a gate insulating layer on the gate electrode, the gate line, and the like, so that when the insulating layer 20 is formed, there is no need to provide another insulating film, and the difference between the thickness of the mark pattern 11 and the thickness of the insulating layer 20 is smaller than the thickness of the mark pattern 11.
In order to maximally improve the problem that the upper surface of the array substrate is uneven at the position of the mark pattern 11 due to the thickness of the mark pattern 11, it is further preferable that the thickness of the gate insulating layer is equal to the thickness of the mark pattern 11.
An embodiment of the present invention provides an array substrate, as shown in fig. 5(a), 5(b), and 5(c), including a mark pattern 11 located in a first sub-area 101 in a mark area 100 of the array substrate, and further including an insulating layer 20; in the mark region 100, the insulating layer 20 covers the mark pattern 11, and the difference between the sum of the thickness of the part of the insulating layer 20 located in the first sub-region 101 and the mark pattern 11 and the thickness of the part of the insulating layer 20 located in the second sub-region 102 is smaller than the thickness of the mark pattern 11; the second sub-area 102 is an area other than the first sub-area 101 in the mark area 100.
Wherein, when the array substrate is applied to a display panel, the array substrate includes a metal layer, the metal layer includes: the mark pattern 11, a gate electrode, a gate line, and further, a common electrode line may be included. The mark pattern 11, the grid electrode and the grid line can be formed by the same composition process; alternatively, the mark pattern 11, the gate electrode, the gate line, and the common electrode line may be formed through the same patterning process.
First, the specific pattern of the mark pattern 11 is different depending on the production line, and the specific pattern of the mark pattern 11 is not limited herein, for example, the specific pattern of the mark pattern 11 may be H-shaped as shown in fig. 3.
Secondly, the position and number of the mark patterns 11 are not limited as long as the mark patterns 11 are located in the non-display area of the array substrate and normal arrangement of other patterns in the non-display area is not affected. Of course, as shown in fig. 3, the array substrate at least includes 4 mark patterns 11, and the mark patterns are respectively distributed at 4 top corners of the array substrate.
Here, when the array substrate includes a plurality of mark patterns 11, specific patterns of the plurality of mark patterns 11 may be the same or different.
Third, as shown in fig. 4, the mark area 100 refers to: an area surrounding the outer edge of the marker pattern 11 and excluding the other light shielding pattern in the non-display area. Wherein the other light-shielding pattern may be a gate line lead, a data line lead, or the like. Of course, in the embodiment of the present invention, the mark area 100 should be larger than the area of the mark pattern 11 on the basis of surrounding the outer edge of the mark pattern 11, so that the difference between the sum of the thicknesses of the portion of the insulating layer 20 located in the first sub-area 101 and the mark pattern 11 and the thickness of the portion of the insulating layer 20 located in the second sub-area 102 is smaller than the thickness of the mark pattern 11 by adjusting the sum of the thicknesses of the portion of the insulating layer 20 located in the first sub-area 101 and the mark pattern 11 and the thickness of the portion of the insulating layer 20 located in the second sub-area 102, thereby improving the problem that the upper surface of the array substrate is uneven at the position of the mark pattern 11 due to the thickness of the mark pattern 11.
Fourth, the thickness of the mark pattern 11 and the thickness of the insulating layer 20 are not limited as long as the difference between the sum of the thicknesses of the mark pattern 11 and the portion of the insulating layer 20 located in the first sub-region 101 and the thickness of the insulating layer 20 located in the second sub-region 102 in the mark region 100 is smaller than the thickness of the mark pattern 11.
For example, as shown in fig. 5(a), the sum of the thicknesses of the portion of the insulating layer 20 located in the first sub-region 101 and the mark pattern 11 is equal to the thickness of the portion of the insulating layer 20 located in the second sub-region 102; as shown in fig. 5(b), the sum of the thicknesses of the portion of the insulating layer 20 located in the first sub-region 101 and the mark pattern 11 is greater than the thickness of the portion of the insulating layer 20 located in the second sub-region 102; as shown in fig. 5(c), the sum of the thicknesses of the portion of the insulating layer 20 located in the first sub-region 101 and the mark pattern 11 may be smaller than the thickness of the portion of the insulating layer 20 located in the second sub-region 102.
Of course, if the array substrate is applied to a display panel, the actual thickness of the display panel, that is, the thickness of the mark pattern 11 and the portion of the insulating layer 20 located in the first sub-region 101 and the thickness of the portion of the insulating layer 20 located in the second sub-region 102, should not exceed the distance between the array substrate and the cassette substrate in the display panel. Illustratively, the thickness sum of the portion of the insulating layer 20 located in the first sub-region 101 and the mark pattern 11 is
The thickness of the portion of the insulating layer 20 located in the second subregion 102 is
In the mark area 100, the insulating layer 20 covers the mark pattern 11, and the difference between the thickness of the part of the insulating layer 20 located in the first sub-area 101 and the thickness of the mark pattern 11 and the thickness of the part of the insulating layer 20 located in the second sub-area 102 is smaller than the thickness of the mark pattern 11, so that the problem that the upper surface of the array substrate is uneven at the position of the mark pattern 11 due to the thickness of the mark pattern 11 can be solved, the problem that the formation of the alignment layer groove of the array substrate and the subsequent liquid crystal dripping are affected due to the fact that the rubbing cloth is deformed or even damaged when passing through the position of the mark pattern 11 in the process of rubbing and aligning the array substrate is solved, the display Mura phenomenon is improved, and the display effect is improved.
Preferably, as shown in fig. 6(a), 6(b), and 6(c), the insulating layer 20 includes a first insulating layer 21 and a second insulating layer 22, the first insulating layer 21 covers the mark pattern 11 and is disposed on the second sub-region 102, and the second insulating layer 22 is disposed on the second sub-region 102 and is located on a side of the second insulating layer 22 away from the substrate; when the array substrate is applied to a display panel, the first insulating layer 21 is a gate insulating layer, and the second insulating layer 22 is a passivation layer (PVX).
Wherein, the material of the gate insulating layer and the passivation layer can be silicon nitride.
Here, the first insulating layer 21 covers the mark pattern 11, meaning that the first insulating layer 21 is disposed in the first sub-region 101, and the first insulating layer 21 covers the mark pattern 11 and is disposed in the second sub-region 102, that is, the first insulating layer 21 is disposed in the entire mark region 100.
In the embodiment of the present invention, the insulating layer 20 is provided as two layers, and when the array substrate is applied to a display panel, the mark pattern 11 may be formed by the same patterning process as a gate electrode, a gate line, and the like, and the first insulating layer 21 may utilize a gate insulating layer located on the gate electrode, the gate line, and the like, and the second insulating layer 22 may utilize a passivation layer located on the gate insulating layer, so that, when the insulating layer 20 is formed, there is no need to provide another insulating film, and a difference between a thickness of a portion of the insulating layer 20 located in the first sub-region 101 and a thickness of the mark pattern 11 and a thickness of a portion of the insulating layer 20 located in the second sub-region 102 is smaller than.
In order to maximally improve the problem that the upper surface of the array substrate is uneven at the position of the mark pattern 11 due to the thickness of the mark pattern 11, it is further preferable that the thickness of the passivation layer is equal to the thickness of the mark pattern 11.
An embodiment of the present invention further provides a display device, including the array substrate according to any one of the foregoing embodiments.
Wherein the display device may be a liquid crystal display.
Embodiments of the present invention provide a display device having the same technical effects as the array substrate, and are not described herein again.
The embodiment of the invention also provides a preparation method of the array substrate, which can be specifically realized through the following steps as shown in fig. 7:
s11, as shown in fig. 8, forming a metal layer on the substrate, the metal layer including: the mark pattern 11 is located in the first sub-area 101 in the array substrate mark area 100.
Here, the metal layer may further include a gate electrode and a gate line, and further, the metal layer may further include a common electrode line. The mark pattern 11, the grid electrode and the grid line can be formed by the same composition process; alternatively, the mark pattern 11, the gate electrode, the gate line, and the common electrode line may be formed through the same patterning process.
S12, as shown in fig. 2(a), 2(b), and 2(c), the insulating layer 20 is formed on the base substrate provided with the metal layer, and the insulating layer 20 includes: the insulating layer 20 is not disposed in the first sub-region 101 and is located in the second sub-region 102; wherein, the difference between the thickness of the mark pattern 11 and the thickness of the insulating layer 20 is smaller than the thickness of the mark pattern 11.
The second sub-area 102 is an area of the mark area 100 other than the first sub-area 101.
Here, the insulating layer 20 may be located in other regions than the mark region 100, and is not limited herein.
In the marking area 100, the difference between the thickness of the marking pattern 11 located in the first sub-area 101 and the thickness of the insulating layer 20 located in the second sub-area 102 is smaller than the thickness of the marking pattern 11, so that the problem that the upper surface of the array substrate is uneven at the position of the marking pattern 11 due to the thickness of the marking pattern 11 can be solved, the problem that the formation of the alignment layer groove of the array substrate and the subsequent dripping of liquid crystal are influenced due to the deformation and even breakage of a rubbing cloth when the rubbing cloth passes through the position of the marking pattern 11 in the process of rubbing and aligning the array substrate is solved, the display Mura phenomenon is improved, and the display effect is improved.
Preferably, as shown in fig. 9, the insulating layer 20 is formed on the substrate provided with the metal layer, and specifically, the following steps are performed:
s101, as shown in fig. 10(a), a first insulating layer film 211 is formed on the substrate provided with the metal layer, and a first photoresist pattern 31 is formed above the first insulating layer film 211, where the first photoresist pattern 31 is located outside the first sub-region 101 and at least in the second sub-region 102.
Among them, the first insulating layer film 211 may be the gate insulating layer film 12.
Here, the first photoresist pattern 31 functions to: when the first photoresist pattern 31 is subsequently stripped, the structures on the first photoresist pattern 31 are also separated from the array substrate along with the first photoresist pattern 31.
Based on this, specifically, the first photoresist pattern 31 is disposed on the second sub-region 102, and on this basis, the first photoresist pattern 31 may also be disposed in a first region outside the first sub-region 101, where the first region refers to: this region includes a structure that is separated from the array substrate as the first photoresist pattern 31 is stripped.
S102, as shown in fig. 10(b), a second insulating film 221 is formed on the substrate with the first photoresist pattern 31, and a second photoresist pattern 32 is formed above the second insulating film 221, wherein the second photoresist pattern 32 is located outside the first sub-region 101 and at least disposed in the second sub-region 102.
The second insulating film 221 may be a passivation film 13.
Here, the second photoresist pattern 32 functions to: when the second insulating layer film 221 and the first insulating layer film 211 of the first sub-region 101 are etched subsequently, the second insulating layer film 221 and the first insulating layer film 211 in the region which is not required to be etched can be prevented from being etched. For example, the second sub-area 102, the display area of the array substrate, and other areas except the via holes.
Based on this, specifically, the second photoresist pattern 32 is disposed in the second sub-region 102, on this basis, the second photoresist pattern 32 may also be disposed in a second region outside the first sub-region 101, and the second insulating layer thin film 221 and the first insulating layer thin film 211 located in the second region do not need to be etched. For example, the second region may also be other regions in the display region of the array substrate except for the via hole.
Here, the via may be a via for routing in a display area of the array substrate.
S103, as shown in fig. 10(c), the second insulating film 221 and the first insulating film 211 of the first sub-region 101 are etched.
Here, the second insulating layer film 221 and the first insulating layer film 211 of the first sub-region 101 may be etched by dry etching.
S104, as shown in fig. 10(d), the first photoresist pattern 31 is stripped.
It should be noted that, in order to improve the problem that the upper surface of the array substrate is uneven at the position of the mark pattern 11 due to the thickness of the mark pattern 11 to the maximum, the thickness of the insulating layer 20 may be equal to the thickness of the mark pattern 11. And making the thickness of the insulating layer 20 equal to that of the mark pattern 11 can be achieved by making the thickness of the first insulating layer film 211 equal to that of the mark pattern 11.
In the embodiment of the present invention, the first photoresist pattern 31 is formed above the first insulating layer film 211, and after the second insulating layer film 221 of the first sub-region 101 and the first insulating layer film 211 are etched, the first photoresist pattern 31 is directly stripped, so that the portion of the second insulating layer film 221 located in the second sub-region 102 and the second photoresist 32 are separated from the array substrate, the process is simple, and in the etching process, the first photoresist pattern 31 can protect the portion of the first insulating layer film 211 located in the first sub-region 101 from being etched; in addition, via holes can be formed in the display area at the same time.
The embodiment of the invention provides a preparation method of an array substrate, which can be specifically realized through the following steps as shown in fig. 11:
s21, as shown in fig. 8, forming a metal layer on the substrate, the metal layer including: the mark pattern 11 is located in the first sub-area 101 in the array substrate mark area 100.
Here, the metal layer may further include a gate electrode and a gate line, and further, the metal layer may further include a common electrode line. The mark pattern 11, the grid electrode and the grid line can be formed by the same composition process; alternatively, the mark pattern 11, the gate electrode, the gate line, and the common electrode line may be formed through the same patterning process.
S22, as shown in fig. 5(a), 5(b), and 5(c), the insulating layer 20 is formed on the base substrate provided with the metal layer, and the insulating layer 20 includes: a portion located in the mark area 100; the difference between the sum of the thicknesses of the part of the insulating layer 20 located in the first sub-region 101 and the mark pattern 11 and the thickness of the part of the insulating layer 20 located in the second sub-region 102 is smaller than the thickness of the mark pattern 11.
The second sub-area 102 is an area of the mark area 100 other than the first sub-area 101.
Here, the insulating layer 20 may be located in other regions than the mark region 100, and is not limited herein.
In the mark area 100, the insulating layer 20 covers the mark pattern 11, and the difference between the thickness of the part of the insulating layer 20 located in the first sub-area 101 and the thickness of the mark pattern 11 and the thickness of the part of the insulating layer 20 located in the second sub-area 102 is smaller than the thickness of the mark pattern 11, so that the problem that the upper surface of the array substrate is uneven at the position of the mark pattern 11 due to the thickness of the mark pattern 11 can be solved, the problem that the formation of the alignment layer groove of the array substrate and the subsequent dripping of liquid crystal are influenced due to the deformation and even breakage of friction cloth when the upper surface passes through the position of the mark pattern 11 in the process of performing friction alignment on the array substrate is solved, the display Mura phenomenon is improved, and the display effect is improved.
Preferably, as shown in fig. 12, the insulating layer 20 is formed on the substrate provided with the metal layer, and specifically, the following steps are performed:
s211, as shown in fig. 13(a), a first insulating layer film 211 and a second insulating layer film 221 are sequentially formed on the substrate provided with the metal layer, and a photoresist is formed over the second insulating layer film 221.
Wherein the first insulating layer film 211 may be the gate insulating layer film 12; the second insulating layer film 221 may be a passivation layer film 13.
S212, as shown in fig. 13(b), exposing the photoresist by using a halftone mask, and forming a photoresist semi-reserved portion, a photoresist completely removed portion, and a photoresist completely reserved portion after developing; the photoresist half-remaining portion corresponds to the first sub-region 101, the photoresist completely-removed portion corresponds to a via to be formed on the array substrate, and the photoresist completely-remaining portion corresponds to another region of the array substrate (the photoresist completely-removed portion is not shown in fig. 13 (b)).
Here, the via may be a via for routing in a display area of the array substrate.
And S213, etching the first insulating layer thin film 211 and the second insulating layer thin film 221 corresponding to the completely removed parts of the photoresist to form the via holes.
Here, the first insulating layer film 211 and the second insulating layer film 221, from which the photoresist is completely removed, may be etched by dry etching.
S214, as shown in fig. 13(c), the photoresist half-remaining portion is removed by an ashing process to form a third photoresist pattern 33.
Here, the third photoresist pattern 33 functions to: when the second insulating layer thin film 221 of the first sub-region 101 is subsequently etched, the second insulating layer thin film 221 in the region that does not need to be etched may be made not to be etched.
Based on this, specifically, the third photoresist pattern 33 is disposed in the second sub-region 102, on this basis, the third photoresist pattern 33 may also be disposed in a third region outside the first sub-region 101, and the second insulating layer film 221 located in the third region does not need to be etched. For example, the third region may also be other regions than the via hole in the display region of the array substrate.
S215, as shown in fig. 13(d), the second insulating film 221 of the first sub-region 101 is etched.
Here, the second insulating layer thin film 221 of the first sub-region 101 may be etched using dry etching.
S216, as shown in fig. 13(e), the third photoresist pattern 33 is stripped.
It should be noted that, in order to improve the problem that the upper surface of the array substrate is uneven at the position of the mark pattern 11 due to the thickness of the mark pattern 11 to the maximum extent, the sum of the thicknesses of the part of the insulating layer 20 located in the first sub-region 101 and the mark pattern 11 may be equal to the thickness of the part of the insulating layer 20 located in the second sub-region 102. However, the above condition can be satisfied by making the thickness of the second insulating film 221 equal to the thickness of the mark pattern 11.
Of course, the etching time of the second insulating film 221 of the first sub-region 101 may be controlled so that the sum of the thickness of the portion of the insulating layer 20 located in the first sub-region 101 and the thickness of the mark pattern 11 is equal to the thickness of the portion of the insulating layer 20 located in the second sub-region 102. On the basis, if the sum of the thickness of the portion of the insulating layer 20 located in the first sub-region 101 and the thickness of the mark pattern 11 is still not equal to the thickness of the portion of the insulating layer 20 located in the second sub-region 102, the first insulating layer film 211 may be partially etched.
In the embodiment of the present invention, in the process of forming the insulating layer 20, via holes are formed in the display region at the same time through a half-tone mask process, and compared with the method of forming the insulating layer 20 in the foregoing embodiment, a mask (i.e., a mask for forming the first photoresist pattern) can be saved in the embodiment of the present invention.
Preferably, as shown in fig. 14, the insulating layer 20 is formed on the substrate provided with the metal layer, and specifically, the following steps are performed:
s221, as shown in fig. 13(c), sequentially forming a first insulating layer film 211 and a second insulating layer film 221 on the substrate provided with the metal layer, and forming a fourth photoresist pattern 34 above the second insulating layer film 221, wherein the fourth photoresist pattern 34 is located outside the first sub-region 101 and at least disposed in the second sub-region 102.
Wherein the first insulating layer film 211 may be the gate insulating layer film 12; the second insulating layer film 221 may be a passivation layer film 13.
Here, the fourth photoresist pattern 34 functions to: when the second insulating layer thin film 221 of the first sub-region 101 is subsequently etched, the second insulating layer thin film 221 in the region that does not need to be etched may be made not to be etched.
Based on this, specifically, the fourth photoresist pattern 34 is disposed in the second sub-region 102, on this basis, the fourth photoresist pattern 34 may also be disposed in a fourth region outside the first sub-region 101, and the second insulating layer thin film 221 located in the fourth region does not need to be etched.
S222, as shown in fig. 13(d), the second insulating film 221 of the first sub-region 101 is etched.
Here, the second insulating layer thin film 221 of the first sub-region 101 may be etched using dry etching.
In step S223, the fourth photoresist pattern 34 is stripped as shown in fig. 13 (e).
It should be noted that, in order to improve the problem that the upper surface of the array substrate is uneven at the position of the mark pattern 11 due to the thickness of the mark pattern 11 to the maximum extent, the sum of the thicknesses of the part of the insulating layer 20 located in the first sub-region 101 and the mark pattern 11 may be equal to the thickness of the part of the insulating layer 20 located in the second sub-region 102. However, the above condition can be satisfied by making the thickness of the second insulating film 221 equal to the thickness of the mark pattern 11.
Of course, the etching time of the second insulating film 221 of the first sub-region 101 may be controlled so that the sum of the thickness of the portion of the insulating layer 20 located in the first sub-region 101 and the thickness of the mark pattern 11 is equal to the thickness of the portion of the insulating layer 20 located in the second sub-region 102. On the basis, if the sum of the thickness of the portion of the insulating layer 20 located in the first sub-region 101 and the thickness of the mark pattern 11 is still not equal to the thickness of the portion of the insulating layer 20 located in the second sub-region 102, the first insulating layer film 211 may be partially etched.
In the embodiment of the present invention, in the process of forming the insulating layer 20, compared with the method for forming the first photoresist pattern 31, a mask plate can be saved; compared with the method which needs the half-tone mask process, the method has the advantage of simple process.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (9)
1. An array substrate comprises a mark pattern located in a first sub-area of a mark area of the array substrate, and is characterized by further comprising an insulating layer;
in the mark region, the insulating layer is arranged in a second subregion except the first subregion, and the difference between the thickness of the mark pattern and the thickness of the insulating layer is smaller than the thickness of the mark pattern;
or, in the mark region, the insulating layer covers the mark pattern, and the difference between the sum of the thickness of the part of the insulating layer located in the first sub-region and the mark pattern and the thickness of the part of the insulating layer located in the second sub-region is smaller than the thickness of the mark pattern;
the insulating layer comprises a first insulating layer and a second insulating layer, the first insulating layer covers the mark pattern and is arranged in the second subarea, and the second insulating layer is arranged in the second subarea and is positioned on one side of the second insulating layer, which is deviated from the substrate base plate.
2. The array substrate of claim 1,
the first insulating layer is a gate insulating layer, and the second insulating layer is a passivation layer.
3. The array substrate of claim 2,
the thickness of the passivation layer is equal to the thickness of the mark pattern.
4. A display device comprising the array substrate according to any one of claims 1 to 3.
5. A preparation method of an array substrate is characterized by comprising the following steps:
forming a metal layer on a substrate, the metal layer comprising: the mark pattern is positioned in a first sub-area in the array substrate mark area;
forming an insulating layer on the substrate provided with the metal layer, the insulating layer including: the insulating layer is positioned on the part of the second sub-area and is not arranged on the first sub-area;
wherein a difference between a thickness of the mark pattern and a thickness of the insulating layer is smaller than a thickness of the mark pattern; the second sub-area is an area except the first sub-area in the mark area; the insulating layer comprises a first insulating layer and a second insulating layer, the first insulating layer covers the mark pattern and is arranged in the second subarea, and the second insulating layer is arranged in the second subarea and is positioned on one side of the second insulating layer, which is deviated from the substrate base plate.
6. The method according to claim 5, wherein the forming an insulating layer on the substrate provided with the metal layer specifically includes:
forming a first insulating layer film on the substrate base plate provided with the metal layer, and forming a first photoresist pattern above the first insulating layer film, wherein the first photoresist pattern is positioned outside the first subregion and at least arranged in the second subregion;
forming a second insulating layer film on the substrate on which the first photoresist pattern is formed, and forming a second photoresist pattern over the second insulating layer film, the second photoresist pattern being located outside the first sub-region and at least disposed in the second sub-region;
etching the second insulating layer film and the first insulating layer film of the first subarea;
and stripping the first photoresist pattern.
7. A preparation method of an array substrate is characterized by comprising the following steps:
forming a metal layer on a substrate, the metal layer comprising: the mark pattern is positioned in a first sub-area in the array substrate mark area;
forming an insulating layer on the substrate provided with the metal layer, the insulating layer including: a portion located at the marking region;
the difference between the sum of the thicknesses of the part of the insulating layer positioned in the first sub-area and the mark pattern and the thickness of the part of the insulating layer positioned in the second sub-area is smaller than the thickness of the mark pattern; the second sub-area is an area except the first sub-area in the mark area; the insulating layer comprises a first insulating layer and a second insulating layer, the first insulating layer covers the mark pattern and is arranged in the second subarea, and the second insulating layer is arranged in the second subarea and is positioned on one side of the second insulating layer, which is deviated from the substrate base plate.
8. The method according to claim 7, wherein the forming an insulating layer on the substrate provided with the metal layer specifically includes:
sequentially forming a first insulating layer film and a second insulating layer film on the substrate base plate provided with the metal layer, and forming photoresist above the second insulating layer film;
exposing the photoresist by using a half-tone mask plate, and developing to form a photoresist semi-reserved part, a photoresist completely removed part and a photoresist completely reserved part; the photoresist semi-reserved part corresponds to the first sub-area, the photoresist completely removed part corresponds to a via hole to be formed on the array substrate, and the photoresist completely reserved part corresponds to other areas of the array substrate;
etching the first insulating layer film and the second insulating layer film corresponding to the completely removed parts of the photoresist to form the via holes;
removing the photoresist semi-reserved part by adopting an ashing process to form a third photoresist pattern;
etching the second insulating layer film of the first subregion;
and stripping the third photoresist pattern.
9. The method according to claim 7, wherein the forming an insulating layer on the substrate provided with the metal layer specifically includes:
sequentially forming a first insulating layer film and a second insulating layer film on the substrate base plate provided with the metal layer, and forming a fourth photoresist pattern above the second insulating layer film, wherein the fourth photoresist pattern is positioned outside the first subarea and at least arranged in the second subarea;
etching the second insulating layer film of the first subregion;
and stripping the fourth photoresist pattern.
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| KR100954332B1 (en) * | 2003-06-30 | 2010-04-21 | 엘지디스플레이 주식회사 | Liquid crystal display device and method of fabricating the same |
| CN103474438A (en) * | 2013-09-26 | 2013-12-25 | 深圳市华星光电技术有限公司 | Thin film transistor array substrate and liquid crystal display panel |
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