CN107507639A - Eliminate circuit and method that SONOS word lines coupling influence reads surplus - Google Patents
Eliminate circuit and method that SONOS word lines coupling influence reads surplus Download PDFInfo
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- CN107507639A CN107507639A CN201710579019.XA CN201710579019A CN107507639A CN 107507639 A CN107507639 A CN 107507639A CN 201710579019 A CN201710579019 A CN 201710579019A CN 107507639 A CN107507639 A CN 107507639A
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- wordline
- bias voltage
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
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Abstract
The invention discloses the circuit that a kind of elimination SONOS word lines coupling influence reads surplus, cellular construction is 2T structures, and the drain electrode of storage tube connects bit line, and the grid of selecting pipe connects the first wordline；The grid of storage tube connects the second wordline；And formation wordline coupled capacitor parallel with two wordline with the first of a line cellular construction；Second wordline is connected to ground by discharge tube；During read operation, the second wordline ground connection, the first wordline, which connects the first bias voltage, turns on selecting pipe, and institute's bit line connects reading of the second bias voltage realization to storage tube；The grid of amplifier tube is connected to the 3rd bias voltage, and the value of the 3rd bias voltage ensures to make the second wordline be pulled down to ground before the precharge of read operation terminates, and eliminates influence of the coupled voltages of coupled capacitor formation to reading surplus.The invention also discloses a kind of method that elimination SONOS word lines coupling influence reads surplus.The present invention eliminates influence of the SONOS word lines coupling to reading surplus, improves and reads surplus.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing field, and the coupling of SONOS word lines is eliminated more particularly to one kind
Influence the circuit of reading surplus.The invention further relates to a kind of method of elimination SONOS word lines coupling influence read operations.
Background technology
As shown in figure 1, be the structure chart of a line of the storage array of existing SONOS devices, the storage of existing SONOS devices
The cellular construction (Cell) of array (Array) is 2T structures, and the 2T structures include the storage tube being made up of SONOS transistors
101 and the selecting pipe 102 that is made up of NMOS tube.
The drain electrode connection bit line BL of the storage tube 101, the source electrode of the storage tube 101 connect the selecting pipe 102
Drain electrode, the source electrode of the selecting pipe 102 meet source line SL.In the storage array of the SONOS devices, the cellular construction is arranged in
Row-column configuration, the bit line BL of the cellular construction of same row are shared, and the multiple row of storage array is shown in Fig. 1, each row
The drain electrode of the storage tube 101 all connects identical bit line BL, in order to distinguish the bit line of different lines, increases in Fig. 1 after BL
[0] to digital numbers such as [N] represents bit line corresponding to different lines, and 2 row, other each column skips are only show in Fig. 1.
The grid of the selecting pipe 102 connects the first wordline WL；The grid of the storage tube 101 connects the second wordline WLS.
Storage array includes multirow, and the first wordline WL with the cellular construction of a line is shared, with the unit knot of a line
The second wordline WLS of structure is shared, and a line is only show in Fig. 1, and other each rows eliminate.The selecting pipe per a line
102 grid all connects the first wordline WL, and the grid of the storage tube 101 connects the second wordline WLS, is not gone together pair to distinguish
The first wordline and the second wordline answered, corresponding numbering is added after WL and WLS respectively, is the 0th row in Fig. 1, therefore in WL
Added [0] afterwards with WLS.
And meeting shape parallel and neighbouring with the second wordline WLS with the first wordline WL of the cellular construction of a line
Into wordline coupled capacitor.Shown in Fig. 1 between the first wordline WL [0] of the 0th row and the second wordline WLS [0]
Coupled capacitor, as shown in Fig. 1, coupled capacitor is formed in parallel by electric capacity C0 and C1.
In Fig. 1, the storage tube 101 of each cellular construction and the substrate of the selecting pipe 102 all link together
And meet same backing substrate electrode VBPW.
Each second wordline WLS's is connected to ground by discharge tube, and in Fig. 1, the discharge tube is by two NMOS
Pipe is that NMOS tube 103 and NMOS tube 104 are in series, and NMOS tube 103 and NMOS tube 104 all use high-voltage tube, and nhv is used in Fig. 1
Represent that NMOS tube 103 and NMOS tube 104 are all high-voltage tube.The grid of NMOS tube 103 and NMOS tube 104 all connects supply voltage
VDDA15。
Table one
| WL[0] | WLS[0] | BL[0]/BL[N] | VBPW | SL | |
| Read operation | First bias voltage | Ground | Second bias voltage | Ground | Ground |
Table one illustrates the voltage that the available circuit shown in Fig. 1 adds in read operation, is specially：
During read operation, the second wordline WLS is WLS [0] ground connection in Fig. 1, and the first wordline WL is the WL in Fig. 1
[0] connecing the first bias voltage turns on the selecting pipe 102, the BL [0] in the bit line BL such as Fig. 1/BL [N] be BL [0] extremely
Arbitrarily selected BL [N] bit line BL connects reading of the second bias voltage realization to the storage tube 101.Backing substrate electrode
VBPW is grounded, source line SL ground connection.Generally, first bias voltage is supply voltage, and second bias voltage is power supply electricity
Pressure, that is, it is added in the supply voltage VDDA15 of the grid of NMOS tube 103 and NMOS tube 104.
In available circuit shown in Fig. 1, the problem of coupling causes be present：
After cellular construction Cell sizes diminish, the spacing (Space) of the interconnection traces between WL and WLS diminishes,
Capacity is big-and-middle, and Array sizes are big, and the coupled capacitor between WL and WLS is increasing.In read operation, WL [0] is set to height,
WLS [0] can be coupled and raise i.e. WLS [0] voltage to be lifted to one from ground connection larger because of the coupling between WL/WLS
Value.WLS [0] is coupled raise after, cause the CELL of SONOS devices electric current to become big, be unfavorable for Cell reading, reading can be made
Surplus is that the surplus (Margin) of read operation reduces, namely normal process fluctuation during cellular construction and read operation be present
When, situation of the available circuit very by being likely to occur read error.
Existing in the case that in coupled capacitor, this is not kind, in order to ensure the Margin read, the improved method of use includes：Increase
The long time read, the WLS of coupling is allowed to have the charge and discharge time to be discharged into ground, but this method can bring read access time is increased to lack
Point.
Another kind is：Strengthen the size of WLS discharge tube, to shorten the time of electric discharge, but this can sacrifice area.
The content of the invention
The technical problems to be solved by the invention are to provide the electricity that a kind of elimination SONOS word lines coupling influence reads surplus
Road, influence of the SONOS word lines coupling to reading surplus can be eliminated, improves and reads surplus.Therefore, the present invention also provides a kind of eliminate
The method that SONOS word lines coupling influence reads surplus.
In order to solve the above technical problems, elimination SONOS word lines coupling influence provided by the invention reads the circuit of surplus
The cellular constructions of storage array of SONOS devices be 2T structures, the 2T structures include the storage being made up of SONOS transistors
Pipe and the selecting pipe i.e. selecting pipe being made up of NMOS tube are N-type selecting pipe (fnpass).
The drain electrode connection bit line of the storage tube, the source electrode of the storage tube connect the drain electrode of the selecting pipe, the choosing
The source electrode for selecting pipe connects source line.
The grid of the selecting pipe connects the first wordline；The grid of the storage tube connects the second wordline.
In the storage array of the SONOS devices, the cellular construction is arranged in rows array structure, the unit of same row
The bit line of structure shares, first wordline with the cellular construction of a line shares, with the cellular construction of a line
Second wordline shares, it is parallel and neighbouring with second wordline with first wordline of the cellular construction of a line and
Wordline coupled capacitor can be formed.
Second wordline is connected to ground by discharge tube, and the discharge tube is made up of NMOS tube.
During read operation, the second wordline ground connection, first wordline, which connects the first bias voltage, turns on the selecting pipe,
The bit line connects reading of the second bias voltage realization to the storage tube.
First bias voltage can be coupled in second wordline simultaneously in power-up by the wordline coupled capacitor
The coupled voltages formed in second wordline；The grid of the amplifier tube is connected to the 3rd bias voltage, the 3rd biasing
Voltage turns on the amplifier tube and second wordline is pulled down into ground, and the 3rd bias voltage is higher by second word
The speed that line drags down from the coupled voltages is faster, and the value of the 3rd bias voltage ensures to terminate in the precharge of read operation
Before make second wordline be pulled down to ground, eliminate the coupled voltages to read surplus influence.
Further improve is that first bias voltage is supply voltage, and second bias voltage is supply voltage.
Further improve is that the discharge tube is in series by two or more NMOS tube, and the NMOS of the discharge tube
The grid of pipe all connects the 3rd bias voltage.
Further improve is that the 3rd bias voltage is more than the supply voltage and provided by positive pressure pump.
Further improve is that the 3rd bias voltage is 4V.
Further improve is, under conditions of the reading surplus is ensured by the 3rd bias voltage, described in diminution
The time of read operation, improve reading rate；Or increase the time of the read operation, with reference to the 3rd bias voltage and described
The setting of the time of read operation eliminates influence of the coupled voltages to reading surplus together.
Further improve is, under conditions of the reading surplus is ensured by the 3rd bias voltage, described in diminution
The size of discharge tube；Or increase the size of the discharge tube, with reference to the 3rd bias voltage and increase the discharge tube
The setting of size eliminates influence of the coupled voltages to reading surplus together.
In order to solve the above technical problems, the method that elimination SONOS word lines coupling influence provided by the invention reads surplus
In the cellular constructions of storage array of SONOS devices be 2T structures, the 2T structures include being deposited by what SONOS transistors formed
Storage pipe and the selecting pipe being made up of NMOS tube.
The drain electrode connection bit line of the storage tube, the source electrode of the storage tube connect the drain electrode of the selecting pipe, the choosing
The source electrode for selecting pipe connects source line.
The grid of the selecting pipe connects the first wordline；The grid of the storage tube connects the second wordline.
In the storage array of the SONOS devices, the cellular construction is arranged in rows array structure, the unit of same row
The bit line of structure shares, first wordline with the cellular construction of a line shares, with the cellular construction of a line
Second wordline shares, it is parallel and neighbouring with second wordline with first wordline of the cellular construction of a line and
Wordline coupled capacitor can be formed.
Second wordline is connected to ground by discharge tube, and the discharge tube is made up of NMOS tube.
During read operation, second wordline is grounded, first wordline, which connects the first bias voltage, leads the selecting pipe
Logical, the bit line connects reading of the second bias voltage realization to the storage tube.
First bias voltage can be coupled in second wordline simultaneously in power-up by the wordline coupled capacitor
The coupled voltages formed in second wordline；The grid of the amplifier tube is connected to the 3rd bias voltage, the described 3rd is inclined
Putting voltage turns on the amplifier tube and second wordline is pulled down into ground, and the value of the 3rd bias voltage ensures reading
The precharge of operation makes second wordline be pulled down to ground before terminating, eliminate influence of the coupled voltages to reading surplus.
Further improve is that first bias voltage is supply voltage, and second bias voltage is supply voltage.
Further improve is that the discharge tube is in series by two or more NMOS tube, and the NMOS of the discharge tube
The grid of pipe all connects the 3rd bias voltage.
Further improve is that the 3rd bias voltage is more than the supply voltage and provided by positive pressure pump.
Further improve is that the 3rd bias voltage is 4V.
Further improve is, under conditions of the reading surplus is ensured by the 3rd bias voltage, described in diminution
The time of read operation, improve reading rate；Or increase the time of the read operation, with reference to the 3rd bias voltage and described
The setting of the time of read operation eliminates influence of the coupled voltages to reading surplus together.
Further improve is, under conditions of the reading surplus is ensured by the 3rd bias voltage, described in diminution
The size of discharge tube；Or increase the size of the discharge tube, with reference to the 3rd bias voltage and increase the discharge tube
The setting of size eliminates influence of the coupled voltages to reading surplus together.
The present invention only needs the 3rd bias voltage of the grid to being connected to amplifier tube to be configured, and utilizes the 3rd bias voltage
Can make amplifier tube turn on and by the second wordline be pulled down to ground and the 3rd bias voltage it is higher by the second wordline from coupled voltages draw
The characteristics of low speed is faster, the present invention, which brings up to the value of the 3rd bias voltage, to be ensured to make before the precharge of read operation terminates
Second wordline is pulled down to ground, so as to eliminate influence of the coupled voltages to reading surplus, so as to improve reading surplus.
Due to present invention only requires carrying out simple voltage and set to can be achieved, thus can not change the structure of circuit and
Realized under conditions of reading speed, therefore the present invention can not increase extra circuit area overhead and not interfere with reading speed
And it can further increase reading speed.
In addition, the present invention can also reduce discharge tube under conditions of the reading surplus is ensured by the 3rd bias voltage
Size, and then the area overhead of circuit is reduced, so as to reduce cost.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is the structure chart of a line of the storage array of existing SONOS devices；
Fig. 2 is the structure chart of a line of the storage array of SONOS devices of the embodiment of the present invention.
Embodiment
As shown in Fig. 2 being the structure chart of a line of the storage array of SONOS devices of the embodiment of the present invention, the present invention is implemented
The cellular construction that example eliminates the storage array of the SONOS devices of the circuit of SONOS word lines coupling influence reading surplus is that 2T is tied
Structure, the 2T structures include the storage tube 101 being made up of SONOS transistors and the selecting pipe 102 being made up of NMOS tube.
The drain electrode connection bit line BL of the storage tube 101, the source electrode of the storage tube 101 connect the selecting pipe 102
Drain electrode, the source electrode of the selecting pipe 102 meet source line SL.In the storage array of the SONOS devices, the cellular construction is arranged in
Row-column configuration, the bit line BL of the cellular construction of same row are shared, and the multiple row of storage array is shown in Fig. 2, each row
The drain electrode of the storage tube 101 all connects identical bit line BL, in order to distinguish the bit line of different lines, increases in Fig. 2 after BL
[0] to digital numbers such as [N] represents bit line corresponding to different lines, and 2 row, other each column skips are only show in Fig. 2.
The grid of the selecting pipe 102 connects the first wordline WL；The grid of the storage tube 101 connects the second wordline WLS.
Storage array includes multirow, and the first wordline WL with the cellular construction of a line is shared, with the unit knot of a line
The second wordline WLS of structure is shared, and a line is only show in Fig. 2, and other each rows eliminate.The selecting pipe per a line
102 grid all connects the first wordline WL, and the grid of the storage tube 101 connects the second wordline WLS, is not gone together pair to distinguish
The first wordline and the second wordline answered, corresponding numbering is added after WL and WLS respectively, is the 0th row in Fig. 2, therefore in WL
Added [0] afterwards with WLS.
And meeting shape parallel and neighbouring with the second wordline WLS with the first wordline WL of the cellular construction of a line
Into wordline coupled capacitor.Shown in Fig. 2 between the first wordline WL [0] of the 0th row and the second wordline WLS [0]
Coupled capacitor, as shown in Fig. 2, coupled capacitor is formed in parallel by electric capacity C0 and C1.
In Fig. 2, the storage tube 101 of each cellular construction and the substrate of the selecting pipe 102 all link together
And meet same backing substrate electrode VBPW.
Each second wordline WLS's is connected to ground by discharge tube, and the discharge tube is made up of NMOS tube；This hair
In bright embodiment, the discharge tube is that NMOS tube 103 and NMOS tube 104 are in series by two NMOS tubes, and the NMOS tube
103 and the grid of the NMOS tube 104 all connect the 3rd bias voltage VPOS_MARG.
During read operation, the second wordline WLS ground connection, the first wordline WL, which connects the first bias voltage, makes the selecting pipe
102 conductings, the bit line BL connect reading of the second bias voltage realization to the storage tube 101.
First bias voltage can be coupled on the second wordline WLS in power-up by the wordline coupled capacitor
And the coupled voltages formed on the second wordline WLS；The discharge tube is that the grid voltage of NMOS tube 103 and 104 all connects
To the 3rd bias voltage VPOS_MARG, the 3rd bias voltage VPOS_MARG makes the discharge tube turn on and by described second
Wordline WLS is pulled down to ground, the 3rd bias voltage VPOS_MARG it is higher by the second wordline WLS from the coupled voltages
The speed dragged down is faster, and the value of the 3rd bias voltage VPOS_MARG ensures to make institute before the precharge of read operation terminates
State the second wordline WLS and be pulled down to ground, eliminate influence of the coupled voltages to reading surplus.
Generally, first bias voltage is supply voltage, and second bias voltage is supply voltage.Described 3rd is inclined
Voltage VPOS_MARG is put more than the supply voltage and is provided by positive pressure pump, such as：The 3rd bias voltage VPOS_MARG is
4V, 4V are only a representative value, can take other values as needed.
Due to being by setting the 3rd bias voltage VPOS_MARG to ensure the reading surplus in the embodiment of the present invention
It is impregnable, therefore the embodiment of the present invention can be realized and ensure the reading surplus by the 3rd bias voltage VPOS_MARG
Under conditions of, the time of the read operation is reduced, improves reading rate.And the 3rd bias voltage VPOS_ can passed through
Under conditions of MARG ensures the reading surplus, the size of the discharge tube is reduced.
In other embodiments, if to when read operation rate request is not very high, can also increase the read operation when
Between, the coupled voltages are eliminated together to reading surplus with reference to the setting of the time of the 3rd bias voltage and the read operation
Influence.
In other embodiments, if to when chip size requirement is not very high, can also increase the size of the discharge tube,
The coupled voltages are eliminated together to reading surplus with reference to the setting of the 3rd bias voltage and the size for increasing the discharge tube
Influence.
The embodiment of the present invention is eliminated in the method that SONOS word lines coupling influence reads surplus, the storage battle array of SONOS devices
The cellular construction of row is 2T structures, and the 2T structures include the storage tube 101 being made up of SONOS transistors and by NMOS tube group
Into selecting pipe 102.
The drain electrode connection bit line BL of the storage tube 101, the source electrode of the storage tube 101 connect the selecting pipe 102
Drain electrode, the source electrode of the selecting pipe 102 meet source line SL.In the storage array of the SONOS devices, the cellular construction is arranged in
Row-column configuration, the bit line BL of the cellular construction of same row are shared, and the multiple row of storage array is shown in Fig. 2, each row
The drain electrode of the storage tube 101 all connects identical bit line BL, in order to distinguish the bit line of different lines, increases in Fig. 2 after BL
[0] to digital numbers such as [N] represents bit line corresponding to different lines, and 2 row, other each column skips are only show in Fig. 2.
The grid of the selecting pipe 102 connects the first wordline WL；The grid of the storage tube 101 connects the second wordline WLS.
Storage array includes multirow, and the first wordline WL with the cellular construction of a line is shared, with the unit knot of a line
The second wordline WLS of structure is shared, and a line is only show in Fig. 2, and other each rows eliminate.The selecting pipe per a line
102 grid all connects the first wordline WL, and the grid of the storage tube 101 connects the second wordline WLS, is not gone together pair to distinguish
The first wordline and the second wordline answered, corresponding numbering is added after WL and WLS respectively, is the 0th row in Fig. 2, therefore in WL
Added [0] afterwards with WLS.
And meeting shape parallel and neighbouring with the second wordline WLS with the first wordline WL of the cellular construction of a line
Into wordline coupled capacitor.Shown in Fig. 2 between the first wordline WL [0] of the 0th row and the second wordline WLS [0]
Coupled capacitor, as shown in Fig. 2, coupled capacitor is formed in parallel by electric capacity C0 and C1.
In Fig. 2, the storage tube 101 of each cellular construction and the substrate of the selecting pipe 102 all link together
And meet same backing substrate electrode VBPW.
Each second wordline WLS's is connected to ground by discharge tube, and the discharge tube is made up of NMOS tube；This hair
In bright embodiment, the discharge tube is that NMOS tube 103 and NMOS tube 104 are in series by two NMOS tubes, and the NMOS tube
103 and the grid of the NMOS tube 104 all connect the 3rd bias voltage VPOS_MARG.
During read operation, the second wordline WLS is grounded, the first wordline WL, which connects the first bias voltage, makes the selection
Pipe 102 turns on, and the bit line BL connects reading of the second bias voltage realization to the storage tube 101.
First bias voltage can be coupled on the second wordline WLS in power-up by the wordline coupled capacitor
And the coupled voltages formed on the second wordline WLS；The grid voltage that the discharge tube is NMOS tube 103 and 104 is all connected
It is connected to the 3rd bias voltage VPOS_MARG, the 3rd bias voltage VPOS_MARG makes the discharge tube turn on and by described the
Two wordline WLS are pulled down to ground, and the 3rd bias voltage VPOS_MARG is higher electric from the coupling by the second wordline WLS
Press the speed dragged down faster, and the value of the 3rd bias voltage VPOS_MARG ensures to make before the precharge of read operation terminates
The second wordline WLS is pulled down to ground, eliminates influence of the coupled voltages to reading surplus.
Generally, first bias voltage is supply voltage, and second bias voltage is supply voltage.Described 3rd is inclined
Voltage VPOS_MARG is put more than the supply voltage and is provided by positive pressure pump, such as：The 3rd bias voltage VPOS_MARG is
4V。
Due to being by setting the 3rd bias voltage VPOS_MARG to ensure the reading in present invention method
Surplus is impregnable, therefore the embodiment of the present invention can be realized and ensure the reading by the 3rd bias voltage VPOS_MARG
Under conditions of surplus, reduce the time of the read operation, improve reading rate.And the 3rd bias voltage can passed through
Under conditions of VPOS_MARG ensures the reading surplus, the size of the discharge tube is reduced.
In other embodiments, if to when read operation rate request is not very high, can also increase the read operation when
Between, the coupled voltages are eliminated together to reading surplus with reference to the setting of the time of the 3rd bias voltage and the read operation
Influence.
In other embodiments, if to when chip size requirement is not very high, can also increase the size of the discharge tube,
The coupled voltages are eliminated together to reading surplus with reference to the setting of the 3rd bias voltage and the size for increasing the discharge tube
Influence.
Emulation is carried out under the conditions of same reference current to be verified：
The WLS of existing structure shown in Fig. 1 coupled voltages current potential at the end of (precharge) is pre-charged is 60mV,
So that reading 1 wrong (Fail) occurs, it is normal to read 0.
The WLS of structure of the embodiment of the present invention shown in Fig. 2 coupled voltages precharge (precharge) terminate before
Ground is discharged into, reading 1 and reading 0 are all normal.
The present invention is described in detail above by specific embodiment, but these not form the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (14)
1. a kind of elimination SONOS word lines coupling influence reads the circuit of surplus, it is characterised in that：The storage battle array of SONOS devices
The cellular construction of row is 2T structures, and the 2T structures include the storage tube being made up of SONOS transistors and are made up of NMOS tube
Selecting pipe；
The drain electrode connection bit line of the storage tube, the source electrode of the storage tube connect the drain electrode of the selecting pipe, the selecting pipe
Source electrode connect source line；
The grid of the selecting pipe connects the first wordline；The grid of the storage tube connects the second wordline；
In the storage array of the SONOS devices, the cellular construction is arranged in rows array structure, the cellular construction of same row
Bit line share, first wordline with the cellular construction of a line shares, described in the cellular construction of a line
Second wordline shares, and meeting shape parallel and neighbouring with second wordline with first wordline of the cellular construction of a line
Into wordline coupled capacitor；
Second wordline is connected to ground by discharge tube, and the discharge tube is made up of NMOS tube；
During read operation, the second wordline ground connection, first wordline, which connects the first bias voltage, turns on the selecting pipe, described
Bit line connects reading of the second bias voltage realization to the storage tube；
First bias voltage can be coupled in second wordline and formed by the wordline coupled capacitor in power-up
Coupled voltages in second wordline；The grid of the amplifier tube is connected to the 3rd bias voltage, the 3rd bias voltage
Turn on the amplifier tube and second wordline be pulled down to ground, the 3rd bias voltage it is higher by second wordline from
The speed that the coupled voltages drag down is faster, and the value of the 3rd bias voltage ensures to make before the precharge of read operation terminates
Second wordline is pulled down to ground, eliminates influence of the coupled voltages to reading surplus.
2. the circuit that SONOS word lines coupling influence reads surplus is eliminated as claimed in claim 1, it is characterised in that：It is described
First bias voltage is supply voltage, and second bias voltage is supply voltage.
3. the circuit that SONOS word lines coupling influence reads surplus is eliminated as claimed in claim 1, it is characterised in that：It is described
Discharge tube is in series by two or more NMOS tube, and the grid of the NMOS tube of the discharge tube all connects the 3rd biased electrical
Pressure.
4. the elimination SONOS word lines coupling influence as described in claim 1 or 3 reads the circuit of surplus, it is characterised in that：Institute
The 3rd bias voltage is stated more than the supply voltage and is provided by positive pressure pump.
5. the circuit that SONOS word lines coupling influence reads surplus is eliminated as claimed in claim 4, it is characterised in that：It is described
3rd bias voltage is 4V.
6. the circuit that SONOS word lines coupling influence reads surplus is eliminated as claimed in claim 1, it is characterised in that：Logical
Cross under conditions of the 3rd bias voltage guarantee reading surplus, reduce the time of the read operation, improve reading rate；
Or increase the time of the read operation, with reference to the setting one of the 3rd bias voltage and the time of the read operation
Act the influence for eliminating the coupled voltages to reading surplus.
7. the circuit that SONOS word lines coupling influence reads surplus is eliminated as claimed in claim 1, it is characterised in that：Logical
Cross under conditions of the 3rd bias voltage guarantee reading surplus, reduce the size of the discharge tube；
Or increase the size of the discharge tube, with reference to setting for the size of the 3rd bias voltage and the increase discharge tube
Put the influence for eliminating the coupled voltages together to reading surplus.
8. a kind of method that elimination SONOS word lines coupling influence reads surplus, it is characterised in that：The storage battle array of SONOS devices
The cellular construction of row is 2T structures, and the 2T structures include the storage tube being made up of SONOS transistors and are made up of NMOS tube
Selecting pipe；
The drain electrode connection bit line of the storage tube, the source electrode of the storage tube connect the drain electrode of the selecting pipe, the selecting pipe
Source electrode connect source line；
The grid of the selecting pipe connects the first wordline；The grid of the storage tube connects the second wordline；
In the storage array of the SONOS devices, the cellular construction is arranged in rows array structure, the cellular construction of same row
Bit line share, first wordline with the cellular construction of a line shares, described in the cellular construction of a line
Second wordline shares, and meeting shape parallel and neighbouring with second wordline with first wordline of the cellular construction of a line
Into wordline coupled capacitor；
Second wordline is connected to ground by discharge tube, and the discharge tube is made up of NMOS tube；
During read operation, second wordline is grounded, first wordline, which connects the first bias voltage, turns on the selecting pipe, institute
Rheme line connects reading of the second bias voltage realization to the storage tube；
First bias voltage can be coupled in second wordline and formed by the wordline coupled capacitor in power-up
Coupled voltages in second wordline；The grid of the amplifier tube is connected to the 3rd bias voltage, the 3rd biased electrical
Pressure turns on the amplifier tube and second wordline is pulled down into ground, and the value of the 3rd bias voltage ensures in read operation
Precharge terminate before make second wordline be pulled down to ground, eliminate the coupled voltages to read surplus influence.
9. the method that SONOS word lines coupling influence reads surplus is eliminated as claimed in claim 8, it is characterised in that：It is described
First bias voltage is supply voltage, and second bias voltage is supply voltage.
10. the method that SONOS word lines coupling influence reads surplus is eliminated as claimed in claim 8, it is characterised in that：It is described
Discharge tube is in series by two or more NMOS tube, and the grid of the NMOS tube of the discharge tube all connects the 3rd biased electrical
Pressure.
11. the method that the elimination SONOS word lines coupling influence as described in claim 8 or 10 reads surplus, it is characterised in that：
3rd bias voltage is more than the supply voltage and provided by positive pressure pump.
12. the method that SONOS word lines coupling influence reads surplus is eliminated as claimed in claim 11, it is characterised in that：Institute
It is 4V to state the 3rd bias voltage.
13. the method that SONOS word lines coupling influence reads surplus is eliminated as claimed in claim 8, it is characterised in that：Logical
Cross under conditions of the 3rd bias voltage guarantee reading surplus, reduce the time of the read operation, improve reading rate；
Or increase the time of the read operation, with reference to the setting one of the 3rd bias voltage and the time of the read operation
Act the influence for eliminating the coupled voltages to reading surplus.
14. the method that SONOS word lines coupling influence reads surplus is eliminated as claimed in claim 8, it is characterised in that：Logical
Cross under conditions of the 3rd bias voltage guarantee reading surplus, reduce the size of the discharge tube；
Or increase the size of the discharge tube, with reference to setting for the size of the 3rd bias voltage and the increase discharge tube
Put the influence for eliminating the coupled voltages together to reading surplus.
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