CN107507639B - Circuit and method for eliminating influence of word line coupling on read margin of SONOS (silicon oxide nitride oxide semiconductor) device - Google Patents

Circuit and method for eliminating influence of word line coupling on read margin of SONOS (silicon oxide nitride oxide semiconductor) device Download PDF

Info

Publication number
CN107507639B
CN107507639B CN201710579019.XA CN201710579019A CN107507639B CN 107507639 B CN107507639 B CN 107507639B CN 201710579019 A CN201710579019 A CN 201710579019A CN 107507639 B CN107507639 B CN 107507639B
Authority
CN
China
Prior art keywords
word line
bias voltage
sonos
tube
coupling
Prior art date
Application number
CN201710579019.XA
Other languages
Chinese (zh)
Other versions
CN107507639A (en
Inventor
李祖渠
刘芳芳
姚翔
Original Assignee
上海华虹宏力半导体制造有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 上海华虹宏力半导体制造有限公司 filed Critical 上海华虹宏力半导体制造有限公司
Priority to CN201710579019.XA priority Critical patent/CN107507639B/en
Publication of CN107507639A publication Critical patent/CN107507639A/en
Application granted granted Critical
Publication of CN107507639B publication Critical patent/CN107507639B/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/08Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/16Multiple access memory array, e.g. addressing one storage element via at least independent addressing line groups

Abstract

The invention discloses a circuit for eliminating word line coupling influence on read margin of an SONOS device, wherein a unit structure is a 2T structure, a drain electrode of a storage tube is connected with a bit line, and a grid electrode of a selection tube is connected with a first word line; the grid of the storage tube is connected with a second word line; the first word line and the second word line of the same row of unit structures are parallel and form a word line coupling capacitor; the second word line is connected to the ground through a discharge tube; during reading operation, the second word line is grounded, the first word line is connected with a first bias voltage to enable the selection tube to be conducted, and the bit line is connected with a second bias voltage to read the storage tube; the gate of the amplifying tube is connected to a third bias voltage, and the value of the third bias voltage ensures that the second word line is pulled down to the ground before the precharge of the reading operation is finished, so that the influence of the coupling voltage formed by the coupling capacitor on the reading allowance is eliminated. The invention also discloses a method for eliminating the influence of word line coupling of the SONOS device on the read margin. The method eliminates the influence of word line coupling of the SONOS device on the read margin, and improves the read margin.

Description

Circuit and method for eliminating influence of word line coupling on read margin of SONOS (silicon oxide nitride oxide semiconductor) device

Technical Field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a circuit for eliminating influence of word line coupling of a SONOS device on read margin. The invention also relates to a method for eliminating word line coupling influence on the reading operation of the SONOS device.

Background

As shown in fig. 1, the Cell structure (Cell) of a memory Array of a conventional SONOS device is a 2T structure, and the 2T structure includes a memory transistor 101 composed of a SONOS transistor and a selection transistor 102 composed of an NMOS transistor.

The drain of the storage tube 101 is connected with a bit line BL, the source of the storage tube 101 is connected with the drain of the selection tube 102, and the source of the selection tube 102 is connected with a source line SL. In the memory array of the SONOS device, the cell structures are arranged in a row-column structure, bit lines BL of the cell structures in the same column are shared, multiple columns of the memory array are shown in fig. 1, drains of the memory tubes 101 in each column are all connected with the same bit line BL, in order to distinguish bit lines in different columns, numerical numbers such as [0] to [ N ] are added behind the BL in fig. 1 to indicate bit lines corresponding to different columns, only 2 columns are shown in fig. 1, and other columns are omitted.

The grid electrode of the selection tube 102 is connected with a first word line WL; the gate of the storage tube 101 is connected to a second word line WLS. The memory array comprises a plurality of rows, the first word lines WL of the unit structures in the same row are shared, the second word lines WLS of the unit structures in the same row are shared, only one row is shown in FIG. 1, and other rows are omitted. The grid electrode of the selection tube 102 of each row is connected with a first word line WL, the grid electrode of the storage tube 101 is connected with a second word line WLS, and in order to distinguish the first word line and the second word line corresponding to different rows, corresponding numbers are added after the WL and the WLS respectively, the number is 0 in the figure 1, so that [0] is added after the WL and the WLS.

The first word line WL and the second word line WLs of the cell structures of the same row are parallel and adjacent and form a word line coupling capacitance. The coupling capacitance between the first word line WL [0] and the second word line WLS [0] of row 0 is shown in FIG. 1, and is shown in FIG. 1 as being formed by capacitors C0 and C1 connected in parallel.

In fig. 1, the substrates of the storage tube 101 and the selection tube 102 of each of the unit structures are connected together and to the same back substrate electrode VBPW.

Each second word line WLS is connected to the ground through a discharge tube, in fig. 1, the discharge tube is formed by connecting two NMOS tubes, i.e., an NMOS tube 103 and an NMOS tube 104 in series, the NMOS tube 103 and the NMOS tube 104 both use high voltage tubes, and nhv in fig. 1 indicates that the NMOS tube 103 and the NMOS tube 104 both use high voltage tubes. The gates of the NMOS transistor 103 and the NMOS transistor 104 are both connected to the supply voltage VDDA 15.

Watch 1

WL[0] WLS[0] BL[0]/BL[N] VBPW SL Read operation First bias voltage Ground Second bias voltage Ground Ground

Table one shows voltages applied during a read operation in the conventional circuit shown in fig. 1, specifically:

in a read operation, the second word line WLS, i.e. WLS [0] in fig. 1, is grounded, the first word line WL, i.e. WL [0] in fig. 1, is connected to a first bias voltage to turn on the select transistor 102, and the bit line BL, e.g. any selected one of bit lines BL [0]/BL [ N ], i.e. BL [0] to BL [ N ] in fig. 1, is connected to a second bias voltage to implement reading of the storage transistor 101. The back substrate electrode VBPW is grounded, and the source line SL is grounded. Typically, the first bias voltage is a power supply voltage, and the second bias voltage is a power supply voltage, i.e., a power supply voltage VDDA15 applied to the gates of the NMOS transistor 103 and the NMOS transistor 104.

In the prior art circuit shown in fig. 1, there are problems caused by coupling:

after the Cell size of the Cell structure becomes smaller, the pitch (Space) of the interconnect traces between the WL and the WLs becomes smaller, and the larger the capacity, the larger the Array size, and the larger the coupling capacitance between the WL and the WLs. In a read operation, WL [0] is set high, WLS [0] will be coupled up due to the coupling effect between WL/WLS, i.e. the voltage of WLS [0] will be raised from ground to a larger value. After WLS [0] is coupled and raised, the current of a CELL of the SONOS device is increased, the reading of the CELL is not facilitated, the reading Margin (Margin) which is the Margin of reading operation is reduced, namely when normal process fluctuation exists in a CELL structure and the reading operation process, the conventional circuit is likely to have the situation of reading errors.

In the prior art, under the condition that the coupling capacitance is not good, in order to ensure read Margin, the adopted improvement method comprises the following steps: the read time is increased, and the coupled WLS has the charge and discharge time to release to the ground, but this method has the disadvantage of increasing the read time.

The other is as follows: the discharge tube of a WLS is enhanced in size to shorten the discharge time, but this sacrifices area.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a circuit for eliminating the influence of word line coupling of an SONOS device on the read margin, which can eliminate the influence of word line coupling of the SONOS device on the read margin and improve the read margin. Therefore, the invention also provides a method for eliminating the influence of word line coupling of the SONOS device on the read margin.

In order to solve the technical problem, the cell structure of the memory array of the SONOS device of the circuit for eliminating the influence of the word line coupling of the SONOS device on the read margin is a 2T structure, wherein the 2T structure comprises a memory tube composed of SONOS transistors and a selection tube composed of NMOS tubes, namely the selection tube is an N-type selection tube (fnpass).

The drain electrode of the storage tube is connected with a bit line, the source electrode of the storage tube is connected with the drain electrode of the selection tube, and the source electrode of the selection tube is connected with the source line.

The grid electrode of the selection tube is connected with a first word line; and the grid electrode of the storage tube is connected with a second word line.

In the memory array of the SONOS device, the cell structures are arranged in a row-column structure, bit lines of the cell structures in the same column are shared, the first word lines of the cell structures in the same row are shared, the second word lines of the cell structures in the same row are shared, and the first word lines and the second word lines of the cell structures in the same row are parallel and adjacent to each other and form word line coupling capacitors.

The second word line is connected to the ground through a discharge tube, and the discharge tube is composed of NMOS tubes.

During reading operation, the second word line is grounded, the first word line is connected with a first bias voltage to enable the selection tube to be conducted, and the bit line is connected with a second bias voltage to achieve reading of the storage tube.

The first bias voltage is coupled to the second word line through the word line coupling capacitor and forms a coupling voltage on the second word line when the first bias voltage is powered up; the gate of the amplifying tube is connected to a third bias voltage, the third bias voltage enables the amplifying tube to be conducted and pulls the second word line to the ground, the higher the third bias voltage is, the faster the second word line is pulled from the coupling voltage is, and the third bias voltage has a value which ensures that the second word line is pulled to the ground before the precharge of the read operation is finished, so that the influence of the coupling voltage on the read margin is eliminated.

In a further improvement, the first bias voltage is a power supply voltage, and the second bias voltage is a power supply voltage.

In a further improvement, the discharge tube is formed by connecting more than two NMOS tubes in series, and the grid electrodes of the NMOS tubes of the discharge tube are connected with the third bias voltage.

In a further refinement, the third bias voltage is greater than the supply voltage and is provided by a positive pressure pump.

In a further improvement, the third bias voltage is 4V.

The further improvement is that under the condition that the read margin is ensured by the third bias voltage, the time of the read operation is shortened, and the read speed is improved; or the time of the reading operation is increased, and the influence of the coupling voltage on the reading margin is eliminated together with the third bias voltage and the time of the reading operation.

In a further improvement, the discharge tube is downsized under the condition that the read margin is secured by the third bias voltage; or, the size of the discharge tube is increased, and the influence of the coupling voltage on the reading margin is eliminated together with the third bias voltage and the arrangement for increasing the size of the discharge tube.

In order to solve the technical problem, the cell structure of the memory array of the SONOS device in the method for eliminating the influence of the word line coupling of the SONOS device on the read margin is a 2T structure, and the 2T structure comprises a memory tube composed of SONOS transistors and a selection tube composed of NMOS tubes.

The drain electrode of the storage tube is connected with a bit line, the source electrode of the storage tube is connected with the drain electrode of the selection tube, and the source electrode of the selection tube is connected with the source line.

The grid electrode of the selection tube is connected with a first word line; and the grid electrode of the storage tube is connected with a second word line.

In the memory array of the SONOS device, the cell structures are arranged in a row-column structure, bit lines of the cell structures in the same column are shared, the first word lines of the cell structures in the same row are shared, the second word lines of the cell structures in the same row are shared, and the first word lines and the second word lines of the cell structures in the same row are parallel and adjacent to each other and form word line coupling capacitors.

The second word line is connected to the ground through a discharge tube, and the discharge tube is composed of NMOS tubes.

And during reading operation, grounding the second word line, connecting the first word line with a first bias voltage to enable the selection tube to be conducted, and connecting the bit line with a second bias voltage to realize reading of the storage tube.

The first bias voltage is coupled to the second word line through the word line coupling capacitor and forms a coupling voltage on the second word line when the first bias voltage is powered up; and connecting the grid electrode of the amplifying tube to a third bias voltage, wherein the third bias voltage enables the amplifying tube to be conducted and pulls the second word line down to the ground, and the value of the third bias voltage ensures that the second word line is pulled down to the ground before the pre-charging of the reading operation is finished, so that the influence of the coupling voltage on the reading allowance is eliminated.

In a further improvement, the first bias voltage is a power supply voltage, and the second bias voltage is a power supply voltage.

In a further improvement, the discharge tube is formed by connecting more than two NMOS tubes in series, and the grid electrodes of the NMOS tubes of the discharge tube are connected with the third bias voltage.

In a further refinement, the third bias voltage is greater than the supply voltage and is provided by a positive pressure pump.

In a further improvement, the third bias voltage is 4V.

The further improvement is that under the condition that the read margin is ensured by the third bias voltage, the time of the read operation is shortened, and the read speed is improved; or the time of the reading operation is increased, and the influence of the coupling voltage on the reading margin is eliminated together with the third bias voltage and the time of the reading operation.

In a further improvement, the discharge tube is downsized under the condition that the read margin is secured by the third bias voltage; or, the size of the discharge tube is increased, and the influence of the coupling voltage on the reading margin is eliminated together with the third bias voltage and the arrangement for increasing the size of the discharge tube.

According to the invention, only the third bias voltage connected to the grid electrode of the amplifier tube needs to be set, and by utilizing the characteristics that the third bias voltage can enable the amplifier tube to be conducted and pull the second word line down to the ground and the higher the third bias voltage is, the faster the speed of pulling the second word line down from the coupling voltage is, the value of the third bias voltage is increased to ensure that the second word line is pulled down to the ground before the pre-charging of the reading operation is finished, so that the influence of the coupling voltage on the reading margin can be eliminated, and the reading margin is improved.

The invention can be realized only by simple voltage setting, so the invention can be realized under the condition of not changing the structure of the circuit and the reading speed, and the invention can further increase the reading speed without increasing additional circuit area overhead and influencing the reading speed.

In addition, the invention can also reduce the size of the discharge tube under the condition of ensuring the reading allowance through the third bias voltage, thereby reducing the area overhead of the circuit and further reducing the cost.

Drawings

The invention is described in further detail below with reference to the following figures and detailed description:

FIG. 1 is a block diagram of one row of a memory array of a prior art SONOS device;

fig. 2 is a block diagram of one row of a memory array of a SONOS device according to an embodiment of the present invention.

Detailed Description

As shown in fig. 2, which is a structure diagram of one row of a memory array of a SONOS device according to an embodiment of the present invention, a cell structure of the memory array of the SONOS device of a circuit for eliminating influence of word line coupling of the SONOS device on a read margin according to the embodiment of the present invention is a 2T structure, where the 2T structure includes a memory transistor 101 composed of a SONOS transistor and a select transistor 102 composed of an NMOS transistor.

The drain of the storage tube 101 is connected with a bit line BL, the source of the storage tube 101 is connected with the drain of the selection tube 102, and the source of the selection tube 102 is connected with a source line SL. In the memory array of the SONOS device, the cell structures are arranged in a row-column structure, bit lines BL of the cell structures in the same column are shared, multiple columns of the memory array are shown in fig. 2, drains of the memory tubes 101 in each column are all connected with the same bit line BL, in order to distinguish bit lines in different columns, numerical numbers such as [0] to [ N ] are added behind the BL in fig. 2 to represent bit lines corresponding to different columns, only 2 columns are shown in fig. 2, and other columns are omitted.

The grid electrode of the selection tube 102 is connected with a first word line WL; the gate of the storage tube 101 is connected to a second word line WLS. The memory array comprises a plurality of rows, wherein the first word lines WL of the unit structures in the same row are shared, the second word lines WLS of the unit structures in the same row are shared, only one row is shown in FIG. 2, and other rows are omitted. The gates of the selection tubes 102 of each row are connected with a first word line WL, the gates of the storage tubes 101 are connected with a second word line WLs, and corresponding numbers are added after the WL and the WLs respectively in order to distinguish the first word line and the second word line corresponding to different rows, namely, the 0 th row in fig. 2, so that [0] is added after the WL and the WLs.

The first word line WL and the second word line WLs of the cell structures of the same row are parallel and adjacent and form a word line coupling capacitance. The coupling capacitance between the first word line WL [0] and the second word line WLS [0] of row 0 is shown in FIG. 2, as is the coupling capacitance shown in FIG. 2 by the parallel connection of capacitances C0 and C1.

In fig. 2, the substrates of the storage tube 101 and the selection tube 102 of each of the cell structures are connected together and to the same back substrate electrode VBPW.

Each second word line WLS is connected to the ground through a discharge tube, and the discharge tube is composed of NMOS tubes; in the embodiment of the invention, the discharge tube is formed by connecting two NMOS tubes, namely an NMOS tube 103 and an NMOS tube 104 in series, and the gates of the NMOS tube 103 and the NMOS tube 104 are both connected with a third bias voltage VPOS _ MARG.

During reading operation, the second word line WLS is grounded, the first word line WL is connected to a first bias voltage to turn on the select transistor 102, and the bit line BL is connected to a second bias voltage to read the storage transistor 101.

The first bias voltage, when powered up, couples to and forms a coupling voltage on the second word line WLS through the word line coupling capacitance; the gate voltages of the discharge tubes, i.e., the NMOS tubes 103 and 104, are both connected to a third bias voltage VPOS _ MARG, which turns on the discharge tubes and pulls the second word line WLS down to ground, the higher the third bias voltage VPOS _ MARG, the faster the rate at which the second word line WLS is pulled down from the coupling voltage, and the value of the third bias voltage VPOS _ MARG ensures that the second word line WLS is pulled down to ground before the precharge of the read operation is finished, eliminating the influence of the coupling voltage on the read margin.

Typically, the first bias voltage is a supply voltage and the second bias voltage is a supply voltage. The third bias voltage VPOS _ MARG is greater than the supply voltage and is provided by a positive pressure pump, such as: the third bias voltage VPOS _ MARG is 4V, 4V being only one typical value, and other values may be taken as needed.

In the embodiment of the present invention, the third bias voltage VPOS _ MARG is set to ensure that the read margin is not affected, so that the embodiment of the present invention can reduce the time of the read operation and improve the read speed under the condition that the read margin is ensured by the third bias voltage VPOS _ MARG. And, the discharge tube can be downsized under the condition that the read margin is secured by the third bias voltage VPOS _ MARG.

In other embodiments, the read operation time can also be increased if the read operation speed requirement is not very high, in combination with the third bias voltage and the read operation time setting to eliminate the effect of the coupling voltage on the read margin.

In other embodiments, the discharge tube can be increased in size if chip size requirements are not high, in combination with the third bias voltage and the provision of increasing the size of the discharge tube to eliminate the effect of the coupling voltage on the read margin.

In the method for eliminating influence of word line coupling on the read margin of the SONOS device, the cell structure of the memory array of the SONOS device is a 2T structure, and the 2T structure comprises a memory tube 101 composed of SONOS transistors and a selection tube 102 composed of NMOS tubes.

The drain of the storage tube 101 is connected with a bit line BL, the source of the storage tube 101 is connected with the drain of the selection tube 102, and the source of the selection tube 102 is connected with a source line SL. In the memory array of the SONOS device, the cell structures are arranged in a row-column structure, bit lines BL of the cell structures in the same column are shared, multiple columns of the memory array are shown in fig. 2, drains of the memory tubes 101 in each column are all connected with the same bit line BL, in order to distinguish bit lines in different columns, numerical numbers such as [0] to [ N ] are added behind the BL in fig. 2 to represent bit lines corresponding to different columns, only 2 columns are shown in fig. 2, and other columns are omitted.

The grid electrode of the selection tube 102 is connected with a first word line WL; the gate of the storage tube 101 is connected to a second word line WLS. The memory array comprises a plurality of rows, wherein the first word lines WL of the unit structures in the same row are shared, the second word lines WLS of the unit structures in the same row are shared, only one row is shown in FIG. 2, and other rows are omitted. The gates of the selection tubes 102 of each row are connected with a first word line WL, the gates of the storage tubes 101 are connected with a second word line WLs, and corresponding numbers are added after the WL and the WLs respectively in order to distinguish the first word line and the second word line corresponding to different rows, namely, the 0 th row in fig. 2, so that [0] is added after the WL and the WLs.

The first word line WL and the second word line WLs of the cell structures of the same row are parallel and adjacent and form a word line coupling capacitance. The coupling capacitance between the first word line WL [0] and the second word line WLS [0] of row 0 is shown in FIG. 2, as is the coupling capacitance shown in FIG. 2 by the parallel connection of capacitances C0 and C1.

In fig. 2, the substrates of the storage tube 101 and the selection tube 102 of each of the cell structures are connected together and to the same back substrate electrode VBPW.

Each second word line WLS is connected to the ground through a discharge tube, and the discharge tube is composed of NMOS tubes; in the embodiment of the invention, the discharge tube is formed by connecting two NMOS tubes, namely an NMOS tube 103 and an NMOS tube 104 in series, and the gates of the NMOS tube 103 and the NMOS tube 104 are both connected with a third bias voltage VPOS _ MARG.

During reading operation, the second word line WLS is grounded, the first word line WL is connected to a first bias voltage to turn on the select transistor 102, and the bit line BL is connected to a second bias voltage to read the storage transistor 101.

The first bias voltage, when powered up, couples to and forms a coupling voltage on the second word line WLS through the word line coupling capacitance; the gate voltages of the discharge tubes, i.e., the NMOS tubes 103 and 104, are both connected to a third bias voltage VPOS _ MARG, which turns on the discharge tubes and pulls down the second word line WLS to ground, the higher the third bias voltage VPOS _ MARG, the faster the rate at which the second word line WLS is pulled down from the coupling voltage, and the value of the third bias voltage VPOS _ MARG ensures that the second word line WLS is pulled down to ground before the precharge of the read operation is finished, eliminating the influence of the coupling voltage on the read margin.

Typically, the first bias voltage is a supply voltage and the second bias voltage is a supply voltage. The third bias voltage VPOS _ MARG is greater than the supply voltage and is provided by a positive pressure pump, such as: the third bias voltage VPOS _ MARG is 4V.

In the method of the embodiment of the present invention, the third bias voltage VPOS _ MARG is set to ensure that the read margin is not affected, so that the embodiment of the present invention can reduce the time of the read operation and improve the read speed under the condition that the read margin is ensured by the third bias voltage VPOS _ MARG. And, the discharge tube can be downsized under the condition that the read margin is secured by the third bias voltage VPOS _ MARG.

In other embodiments, the read operation time can also be increased if the read operation speed requirement is not very high, in combination with the third bias voltage and the read operation time setting to eliminate the effect of the coupling voltage on the read margin.

In other embodiments, the discharge tube can be increased in size if chip size requirements are not high, in combination with the third bias voltage and the provision of increasing the size of the discharge tube to eliminate the effect of the coupling voltage on the read margin.

Simulations performed under the same reference current conditions can verify that:

the coupling voltage of the WLS of the conventional structure shown in fig. 1 is 60mV at the end of precharge, so that error (Fail) occurs for read 1 and read 0 is normal.

The coupling voltage of WLS constructed in accordance with the embodiment of the present invention shown in fig. 2 has been discharged to ground before the precharge (precharge) is completed, and both read 1 and read 0 are normal.

The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (14)

1. A circuit for eliminating influence of word line coupling of SONOS devices on read margin is characterized in that: the cell structure of a storage array of the SONOS device is a 2T structure, and the 2T structure comprises a storage tube consisting of SONOS transistors and a selection tube consisting of NMOS tubes;
the drain electrode of the storage tube is connected with a bit line, the source electrode of the storage tube is connected with the drain electrode of the selection tube, and the source electrode of the selection tube is connected with a source line;
the grid electrode of the selection tube is connected with a first word line; the grid electrode of the storage tube is connected with a second word line;
in the memory array of the SONOS device, the cell structures are arranged in a row-column structure, bit lines of the cell structures in the same column are shared, the first word lines of the cell structures in the same row are shared, the second word lines of the cell structures in the same row are shared, and the first word lines and the second word lines of the cell structures in the same row are parallel and adjacent to each other and form word line coupling capacitors;
the second word line is connected to the ground through a discharge tube, and the discharge tube is composed of NMOS tubes;
during reading operation, the second word line is grounded, the first word line is connected with a first bias voltage to enable the selection tube to be conducted, and the bit line is connected with a second bias voltage to read the storage tube;
the first bias voltage is coupled to the second word line through the word line coupling capacitor and forms a coupling voltage on the second word line when the first bias voltage is powered up; the grid electrode of the discharge tube is connected to a third bias voltage, the third bias voltage enables the discharge tube to be conducted and pulls the second word line to the ground, the higher the third bias voltage, the faster the second word line is pulled from the coupling voltage, and the third bias voltage has the value that the second word line is pulled to the ground before the precharge of the reading operation is finished, so that the influence of the coupling voltage on the reading allowance is eliminated.
2. The circuit of claim 1, wherein the circuit for eliminating word line coupling effect on the read margin of the SONOS device is characterized in that: the first bias voltage is a power supply voltage, and the second bias voltage is a power supply voltage.
3. The circuit of claim 1, wherein the circuit for eliminating word line coupling effect on the read margin of the SONOS device is characterized in that: the discharge tube is formed by connecting more than two NMOS tubes in series, and the grid electrodes of the NMOS tubes of the discharge tube are connected with the third bias voltage.
4. The circuit of claim 1 or 3, wherein the SONOS device word line coupling is eliminated, and wherein the circuit further comprises: the third bias voltage is greater than the supply voltage and is provided by a positive pressure pump.
5. The circuit of claim 4, wherein the SONOS device word line coupling is eliminated, and wherein the circuit further comprises: the third bias voltage is 4V.
6. The circuit of claim 1, wherein the circuit for eliminating word line coupling effect on the read margin of the SONOS device is characterized in that: reducing the time of the read operation and improving the read speed under the condition that the read margin is ensured by the third bias voltage;
or the time of the reading operation is increased, and the influence of the coupling voltage on the reading margin is eliminated together with the third bias voltage and the time of the reading operation.
7. The circuit of claim 1, wherein the circuit for eliminating word line coupling effect on the read margin of the SONOS device is characterized in that: reducing the size of the discharge tube under the condition that the read margin is ensured by the third bias voltage;
or, the size of the discharge tube is increased, and the influence of the coupling voltage on the reading margin is eliminated together with the third bias voltage and the arrangement for increasing the size of the discharge tube.
8. A method for eliminating influence of word line coupling on reading margin of SONOS device is characterized by comprising the following steps: the cell structure of a storage array of the SONOS device is a 2T structure, and the 2T structure comprises a storage tube consisting of SONOS transistors and a selection tube consisting of NMOS tubes;
the drain electrode of the storage tube is connected with a bit line, the source electrode of the storage tube is connected with the drain electrode of the selection tube, and the source electrode of the selection tube is connected with a source line;
the grid electrode of the selection tube is connected with a first word line; the grid electrode of the storage tube is connected with a second word line;
in the memory array of the SONOS device, the cell structures are arranged in a row-column structure, bit lines of the cell structures in the same column are shared, the first word lines of the cell structures in the same row are shared, the second word lines of the cell structures in the same row are shared, and the first word lines and the second word lines of the cell structures in the same row are parallel and adjacent to each other and form word line coupling capacitors;
the second word line is connected to the ground through a discharge tube, and the discharge tube is composed of NMOS tubes;
during reading operation, grounding the second word line, connecting the first word line with a first bias voltage to enable the selection tube to be conducted, and connecting the bit line with a second bias voltage to realize reading of the storage tube;
the first bias voltage is coupled to the second word line through the word line coupling capacitor and forms a coupling voltage on the second word line when the first bias voltage is powered up; connecting a gate of the discharge tube to a third bias voltage, the third bias voltage turning on the discharge tube and pulling the second word line low to ground, and the third bias voltage having a value that ensures that the second word line is pulled low to ground before the precharge of the read operation is completed, eliminating the effect of the coupling voltage on the read margin.
9. The method of claim 8, wherein the method for eliminating word line coupling influence on the read margin of the SONOS device comprises: the first bias voltage is a power supply voltage, and the second bias voltage is a power supply voltage.
10. The method of claim 8, wherein the method for eliminating word line coupling influence on the read margin of the SONOS device comprises: the discharge tube is formed by connecting more than two NMOS tubes in series, and the grid electrodes of the NMOS tubes of the discharge tube are connected with the third bias voltage.
11. The method of claim 8 or 10, wherein the SONOS device word line coupling is eliminated, and wherein the read margin is affected by: the third bias voltage is greater than the supply voltage and is provided by a positive pressure pump.
12. The method of claim 11, wherein the method of eliminating SONOS device word line coupling from affecting read margin comprises: the third bias voltage is 4V.
13. The method of claim 8, wherein the method for eliminating word line coupling influence on the read margin of the SONOS device comprises: reducing the time of the read operation and improving the read speed under the condition that the read margin is ensured by the third bias voltage;
or the time of the reading operation is increased, and the influence of the coupling voltage on the reading margin is eliminated together with the third bias voltage and the time of the reading operation.
14. The method of claim 8, wherein the method for eliminating word line coupling influence on the read margin of the SONOS device comprises: reducing the size of the discharge tube under the condition that the read margin is ensured by the third bias voltage;
or, the size of the discharge tube is increased, and the influence of the coupling voltage on the reading margin is eliminated together with the third bias voltage and the arrangement for increasing the size of the discharge tube.
CN201710579019.XA 2017-07-17 2017-07-17 Circuit and method for eliminating influence of word line coupling on read margin of SONOS (silicon oxide nitride oxide semiconductor) device CN107507639B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710579019.XA CN107507639B (en) 2017-07-17 2017-07-17 Circuit and method for eliminating influence of word line coupling on read margin of SONOS (silicon oxide nitride oxide semiconductor) device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710579019.XA CN107507639B (en) 2017-07-17 2017-07-17 Circuit and method for eliminating influence of word line coupling on read margin of SONOS (silicon oxide nitride oxide semiconductor) device

Publications (2)

Publication Number Publication Date
CN107507639A CN107507639A (en) 2017-12-22
CN107507639B true CN107507639B (en) 2020-06-09

Family

ID=60679847

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710579019.XA CN107507639B (en) 2017-07-17 2017-07-17 Circuit and method for eliminating influence of word line coupling on read margin of SONOS (silicon oxide nitride oxide semiconductor) device

Country Status (1)

Country Link
CN (1) CN107507639B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001014858A (en) * 1999-06-29 2001-01-19 Toshiba Corp Memory device and coupling noise eliminating device
CN1287362A (en) * 1999-09-08 2001-03-14 株式会社东芝 Non-volatile semiconductor memory
CN1677569A (en) * 2004-04-01 2005-10-05 海力士半导体有限公司 NAND flash memory device and method of reading the same
CN102498475A (en) * 2009-07-10 2012-06-13 柰米闪芯积体电路有限公司 Novel high speed high density NAND-based 2t-NOR flash memory design

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6954376B2 (en) * 2003-12-15 2005-10-11 Solid State System Co., Ltd. Non-volatile semiconductor memory array structure and operations
KR100725980B1 (en) * 2005-07-23 2007-06-08 삼성전자주식회사 Memory device and method for improving reading speed of data stored non-volatile memory
US8120953B2 (en) * 2008-12-11 2012-02-21 Samsung Electronics Co., Ltd. Reading method of nonvolatile semiconductor memory device
KR101015644B1 (en) * 2009-05-29 2011-02-22 주식회사 하이닉스반도체 Nonvolatile memory device and method of programing the same
US8995195B2 (en) * 2013-02-12 2015-03-31 Sandisk Technologies Inc. Fast-reading NAND flash memory

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001014858A (en) * 1999-06-29 2001-01-19 Toshiba Corp Memory device and coupling noise eliminating device
CN1287362A (en) * 1999-09-08 2001-03-14 株式会社东芝 Non-volatile semiconductor memory
CN1677569A (en) * 2004-04-01 2005-10-05 海力士半导体有限公司 NAND flash memory device and method of reading the same
CN102498475A (en) * 2009-07-10 2012-06-13 柰米闪芯积体电路有限公司 Novel high speed high density NAND-based 2t-NOR flash memory design

Also Published As

Publication number Publication date
CN107507639A (en) 2017-12-22

Similar Documents

Publication Publication Date Title
US9620217B2 (en) Sub-block erase
US10354718B2 (en) Systems and methods for reducing standby power in floating body memory devices
US10163491B2 (en) Memory circuit having shared word line
US8503221B1 (en) SRAM cell with common bit line and source line standby voltage
US9847133B2 (en) Memory array capable of performing byte erase operation
EP2854136B1 (en) Non-volatile memory for high rewrite cycles applications.
KR101461799B1 (en) Methods for operating sram cells
US6577523B2 (en) Reduced area sense amplifier isolation layout in a dynamic RAM architecture
JP4110115B2 (en) Semiconductor memory device
US8854883B2 (en) Fusion memory
US7940566B2 (en) Flash memory device adapted to prevent read failures due to dummy strings
US20130322179A1 (en) Hot carrier programming in nand flash
US10622062B2 (en) 2T-1R architecture for resistive ram
US6992928B2 (en) Semiconductor memory device with an improved memory cell structure and method of operating the same
US8705290B2 (en) Memory device having improved programming operation
TWI446524B (en) Nand flash memory having multiple cell substrates
US7257017B2 (en) SRAM cell for soft-error rate reduction and cell stability improvement
US9412432B2 (en) Semiconductor storage device and system provided with same
US6781915B2 (en) Semiconductor memory device
US8773918B2 (en) Semiconductor memory device and method of writing into semiconductor memory device
EP3190590B1 (en) Semiconductor storage device
US20120281471A1 (en) Memory Page Buffer
US7709893B2 (en) Circuit layout for different performance and method
JP4068781B2 (en) Semiconductor integrated circuit device and method for manufacturing semiconductor integrated circuit device
US7436710B2 (en) EEPROM memory device with cell having NMOS in a P pocket as a control gate, PMOS program/erase transistor, and PMOS access transistor in a common well

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant