CN107490916A - Dot structure and array base palte, liquid crystal display panel - Google Patents
Dot structure and array base palte, liquid crystal display panel Download PDFInfo
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- CN107490916A CN107490916A CN201710909091.4A CN201710909091A CN107490916A CN 107490916 A CN107490916 A CN 107490916A CN 201710909091 A CN201710909091 A CN 201710909091A CN 107490916 A CN107490916 A CN 107490916A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mathematical Physics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Optics & Photonics (AREA)
- Liquid Crystal (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention provides a kind of dot structure, the data wire being arranged side by side including a plurality of vertical direction, the gate line that a plurality of horizontal direction is arranged side by side, multiple sub-pixels, each sub-pixel includes at least two thin film transistor (TFT)s and pixel electrode, every two grid line groups are connected into one group of grid line groups, thin film transistor (TFT) of the every group of grid line groups respectively with every row sub-pixel in a plurality of gate line；Thin film transistor (TFT) is also connected with adjacent data wire and pixel electrode respectively in each sub-pixel；The opposite polarity of two gate lines in every group of grid line groups；The opposite polarity for two data lines being connected with thin film transistor (TFT) in each sub-pixel.Present invention also offers a kind of array base palte and liquid crystal display panel, including described dot structure.Compared with prior art, the problem of improving the electrical leakage problems under line inversion driving mode and causing picture exception, while the jump in potential mode of data line signal is changed, so as to effectively reduce the driving power consumption of data wire.
Description
Technical field
The present invention relates to a kind of display panel technology, more particularly to a kind of dot structure and array base palte, liquid crystal display
Panel.
Background technology
In current information-intensive society, TFT LCD (Thin Film Transistor, thin film transistor (TFT)；Liquid Crystal
Display, liquid crystal display) various aspects of our lives are had been widely used for, from the mobile phone, video camera, number of small size
Code-phase machine, notebook computer, the desktop computer of middle size, large-sized domestic TV to large-scale projector equipment etc., TFT LCD exist
Gently, on the basis of thin advantage, plus perfect picture and quick response characteristic, it is ensured that it monopolizes huge legendary turtle on monitor market
Head.
In active matrix LCD, each sub-pixel has a TFT device (thin film transistor (TFT)), its grid
(gate) scan line (Gate) of horizontal direction is connected to, drain electrode (drain) is connected to the data wire (Date) of vertical direction, and
Source electrode (source) is then connected to pixel electrode.
In same scan line in the horizontal direction, the grid of all TFT devices all links together, so the electricity applied
Pressure is to interlock, if applying sufficiently large positive voltage in a certain bar scan line, all TFT devices all can in this scan line
It is opened, now the pixel electrode in this scan line can be connected with the data wire of vertical direction, and be sent via vertical data line
Enter corresponding vision signal, pixel electrode is charged to appropriate voltage, then apply sufficiently large negative voltage and close TFT devices
Part, signal is re-write again until next time, therebetween electric charge is stored on liquid crystal capacitance.Now restart a time level to sweep
Line is retouched, is sent into its corresponding vision signal.So sequentially the video data of whole picture is write, then again from first again
Write signal (this general frequency repeated is 60~70Hz).
The mode that the driving voltage of liquid crystal panel is typically employed to polarity inversion is driven, row reversion (Column
Inversion) a kind of common type of drive is turned into because the taste of its picture is preferable and driving power consumption is relatively low, such as Fig. 1 and Fig. 2 institutes
Show.But under the type of drive for reversion of being expert at, the diverse location of the liquid crystal panel drain conditions different by degree occurs, such as
A certain grey menu shown in Fig. 3, corresponding data line voltage waveform is as shown in Figure 4 in vertical direction.
With scanning direction in Fig. 3 from A to B, A, B are positive potential during nth frame, and A, B are to carry out exemplified by negative potential during N+1 frames
Explanation.In N+1 frames, before the inswept A points of scan line its pixel electrode polarities of potentials be just, data wire polarity be negative, one
In frame image time, the time in electric leakage is about the 1/3 of a frame image time, its sub-pixel electricity after scan line inswept A points
Electrode potential polarity be bear, data wire polarity is negative, the time in non-electric leakage is about the 2/3 of a frame image time；Work as scan line
Before inswept B points its pixel electrode polarities of potentials be just, data wire polarity be negative, when the time in electric leakage is about a frame picture
Between 2/3, after scan line inswept B points its pixel electrode polarities of potentials be bear, data wire polarity is negative, in non-electric leakage
Time is about the 1/3 of a frame image time.Therefore, in liquid crystal panel vertical direction diverse location sub-pixel can due in
The time of positive and negative half cycle is different and different drain conditions occurs, causes picture is abnormal, influences picture to sample.
The content of the invention
For overcome the deficiencies in the prior art, the present invention provides a kind of dot structure and array base palte, liquid crystal display panel, changed
Picture abnormal problem caused by electrical leakage problems under benefaction inversion driving mode.
A kind of dot structure of the present invention, including the data wire that a plurality of vertical direction is arranged side by side, a plurality of horizontal direction is simultaneously
The gate line of arrangement, multiple sub-pixels, each sub-pixel include at least two thin film transistor (TFT)s and pixel electrode, a plurality of grid
Every two grid line groups connect with the thin film transistor (TFT) of every row sub-pixel respectively into one group of grid line groups, every group of grid line groups in line
Connect；Thin film transistor (TFT) is also connected with adjacent data wire and pixel electrode respectively in each sub-pixel；
The opposite polarity of two gate lines in every group of grid line groups；
The opposite polarity for two data lines being connected with thin film transistor (TFT) in each sub-pixel.
Further, in the two neighboring sub-pixel of every row, one of thin film transistor (TFT) in previous sub-pixel
Grid is connected a gate line in one group of grid line groups with the grid of one of thin film transistor (TFT) in the latter sub-pixel；
The grid of the grid of another thin film transistor (TFT) in previous sub-pixel and another thin film transistor (TFT) in the latter sub-pixel
Pole connects another gate line in this group of grid line groups；Two adjacent films in previous sub-pixel and the latter sub-pixel
The drain electrode of transistor connects same data lines.
Further, in the two neighboring sub-pixel of every row, one of thin film transistor (TFT) in previous sub-pixel
Grid is connected a gate line in one group of grid line groups with the grid of one of thin film transistor (TFT) in the latter sub-pixel；
The grid of the grid of another thin film transistor (TFT) in previous sub-pixel and another thin film transistor (TFT) in the latter sub-pixel
Pole connects another gate line in this group of grid line groups；Every two data line forms one group of data line group in a plurality of data lines,
Thin film transistor (TFT) is connected with one group of data line group respectively in each sub-pixel.
Further, two thin film transistor (TFT)s, respectively first film transistor, the second film are provided with each sub-pixel
Transistor, the first film transistor are connected with the second thin film transistor (TFT), wherein, the source electrode of first film transistor and second
The source electrode of thin film transistor (TFT) is connected and connected with pixel electrode, the drain electrode of first film transistor and the second thin film transistor (TFT)
Drain electrode be connected respectively with adjacent data wire, the grid of first film transistor connects a grid in this group of grid line groups
Line, the grid of the second thin film transistor (TFT) connect another gate line in this group of grid line groups.
Further, in the two neighboring sub-pixel of every row, the grid of the first film transistor in previous sub-pixel
A gate line being connected with the grid of the first film transistor in the latter sub-pixel in one group of grid line groups；Previous height
The grid of the second thin film transistor (TFT) in pixel is connected this group of grid with the grid of the second thin film transistor (TFT) in the latter sub-pixel
Another gate line in polar curve group；The second thin film transistor (TFT) in previous sub-pixel and second in the latter sub-pixel are thin
The drain electrode of film transistor connects same data lines.
Further, in the two neighboring sub-pixel of every row, the grid of the first film transistor in previous sub-pixel
A gate line being connected with the grid of the first film transistor in the latter sub-pixel in one group of grid line groups；Previous height
The grid of the second thin film transistor (TFT) in pixel is connected this group of grid with the grid of the second thin film transistor (TFT) in the latter sub-pixel
Another gate line in polar curve group；Every two data line forms one group of data line group in a plurality of data lines, in each sub-pixel
First film transistor, the second thin film transistor (TFT) are connected with one group of data line group respectively.
Further, often the color of capable multiple sub-pixels comprises at least three kinds of different colors.
Further, the color of multiple sub-pixels of often going includes three kinds of different colors, respectively red, green, blue or often goes
The color of multiple sub-pixels includes four kinds of different colors, respectively red, green, blue, white.
Present invention also offers a kind of array base palte, including described dot structure.
Present invention also offers a kind of liquid crystal display panel, including described dot structure.
The present invention compared with prior art, by setting at least two thin film transistor (TFT)s on a sub-pixel, two
Thin film transistor (TFT) connects on opposite polarity data wire adjacent thereto respectively, and utilizes one group of two opposite polarity gate line
It is controlled by, the problem of causing picture exception by this electrical leakage problems under improving in a manner of line inversion driving, while also makes data
Jump in potential (change of low and high level) mode of line signal changes, so as to effectively reduce the driving power consumption of data wire.
Brief description of the drawings
Fig. 1 is the schematic diagram of the driving voltage of nth frame picture in the prior art；
Fig. 2 is the schematic diagram of the driving voltage of N+1 frames picture in the prior art；
Fig. 3 is the schematic diagram of a certain grey menu；
Fig. 4 is using Fig. 3 as nth frame picture to data line voltage oscillogram during N+1 frame pictures；
Fig. 5 is the circuit diagram of sub-pixel structure of the present invention；
Fig. 6 is the first connection circuit diagram of two sub-pixel structures of the present invention；
Fig. 7 is second of connection circuit diagram of two sub-pixel structures of the present invention.
Embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.
The dot structure of the present invention is suitable for the liquid crystal display panel under line inversion driving mode.
As shown in figure 5, a kind of dot structure of the present invention, including the data wire Date that a plurality of vertical direction is arranged side by side,
The gate lines G ate that a plurality of horizontal direction is arranged side by side, multiple sub-pixels, wherein, it is brilliant that each sub-pixel includes at least two films
Every two grid line groups are into one group of grid line groups in body pipe TFT 1, TFT 2 and pixel electrode Pixel, a plurality of gate lines G ate,
Every group of grid line groups scan as a line, and sub-pixel is located at every group of grid line groups and data wire Date infalls, every group of gate line
The thin film transistor (TFT) TFT 1 with every row sub-pixel, TFT 2 are connected group respectively；Thin film transistor (TFT) TFT 1 in each sub-pixel,
TFT 2 is also connected with adjacent data wire Data and pixel electrode Pixel respectively；Two gate lines in every group of grid line groups
Gate opposite polarity；With the two data line Data being connected of thin film transistor (TFT) TFT 1, TFT 2 in each sub-pixel polarity
Conversely.
The sub-pixel of the present invention has two kinds of connected modes：
One of which is, in the two neighboring sub-pixel of every row, one of thin film transistor (TFT) in previous sub-pixel
Grid a grid in one group of grid line groups is connected with the grid of one of thin film transistor (TFT) in the latter sub-pixel
Line；The grid of another thin film transistor (TFT) in previous sub-pixel and another thin film transistor (TFT) in the latter sub-pixel
Grid connects another gate line in this group of grid line groups；It is adjacent two thin in previous sub-pixel and the latter sub-pixel
The drain electrode of film transistor connects same data lines.
Another kind is, in the two neighboring sub-pixel of every row, one of thin film transistor (TFT) in previous sub-pixel
Grid is connected a gate line in one group of grid line groups with the grid of one of thin film transistor (TFT) in the latter sub-pixel；
The grid of the grid of another thin film transistor (TFT) in previous sub-pixel and another thin film transistor (TFT) in the latter sub-pixel
Pole connects another gate line in this group of grid line groups；Every two data line forms one group of data line group in a plurality of data lines,
Thin film transistor (TFT) is connected with one group of data line group respectively in each sub-pixel.
In the present invention, often the color of capable multiple sub-pixels comprises at least three kinds of different colors, specifically, often goes multiple
The color of sub-pixel includes three kinds of different colors, the respectively arrangement mode of red, green, blue, but the invention is not restricted to this, example
Such as, it is green, blue, red；It is blue, red, green；It is green, red, blue etc..
The present invention, which often goes the colors of multiple sub-pixels, includes four kinds of different colors, respectively red, green, blue, in vain, herein not
The sequencing of arrangement is described in detail, put in order to be adjusted correspondingly as needed.
As one embodiment of the present invention, as shown in figure 5, in the following description, by every group of grid line groups
Two gate lines are respectively defined as first grid polar curve Gate1, second gate line Gate2, and two films are provided with each sub-pixel
Transistor, respectively first film transistor TFT 1, the second thin film transistor (TFT) TFT 2, the first film transistor TFT 1
Connected with the second thin film transistor (TFT) TFT2, wherein, first film transistor TFT 1 source electrode and the second thin film transistor (TFT) TFT 2
Source electrode be connected and connect with pixel electrode Pixel, first film transistor TFT 1 drain electrode and the second thin film transistor (TFT)
TFT 2 drain electrode is connected with adjacent data wire Data respectively, and first film transistor TFT 1 grid connects one group of gate line
First grid polar curve Gate1 in group, the grid of the second thin film transistor (TFT) connect the second gate line in this group of grid line groups
Gate2。
As shown in fig. 6, the first connection to embodiment sub-pixel illustrates below, in order to be easy to manage
Solution, in the two neighboring sub-pixel of every row, left side is the first sub-pixel in figure, and right side is the second sub-pixel, three numbers in figure
It is respectively the first data wire Data 1, the second data wire Data2, the 3rd data wire Data3 according to line, first in the first sub-pixel
Thin film transistor (TFT) TFT 1 grid is connected the row gate line with the grid of the first film transistor TFT 1 in the second sub-pixel
First grid polar curve Gate 1 in group；In the grid and the second sub-pixel of the second thin film transistor (TFT) TFT 2 in first sub-pixel
The second thin film transistor (TFT) TFT 2 grid connect second gate line Gate 2 in the row grid line groups；In first sub-pixel
The second thin film transistor (TFT) TFT 2 drain electrode be connected with the drain electrode of the first film transistor TFT 2 in the second sub-pixel it is same
The second data wire of root Date 2, that is to say, that a data line Data2 can be shared in two neighboring sub-pixel；In first sub-pixel
First film transistor TFT 1 drain electrode is connected with the first data wire Data 1, and the second thin film transistor (TFT) in the second sub-pixel
TFT 2 drain electrode is connected with the 3rd data wire Data 3, here it is worth noting that being clipped in the data wire between two sub-pixels
Polarity with positioned at the left and right sides data wire opposite polarity.
As shown in fig. 7, second of connection to embodiment sub-pixel illustrates, in order to readily appreciate,
Often in the two neighboring sub-pixel of row, left side be the first sub-pixel in figure, and right side is the second sub-pixel, and four data lines divide in figure
Wei not the first data wire Data 1, the second data wire Data2, the 3rd data wire Data3, the 4th data wire Data 4；First son
The grid of first film transistor TFT 2 in the grid and the second sub-pixel of first film transistor TFT 1 in pixel connects
Meet the first grid polar curve Gate 1 in the grid line groups of the row；The grid of the second thin film transistor (TFT) TFT 2 in first sub-pixel
The second gate line Gate being connected with the grid of the second thin film transistor (TFT) TFT 2 in the second sub-pixel in the grid line groups of the row
2；Every two data line forms one group of data line group in a plurality of data lines, as every column data line, wherein the first data wire Data
1 and second data wire Data 2 be used as first group of data line group, the 3rd data wire Data 3 and the conducts of the 4th data wire Data 4
Second group of data line group, first, second thin film transistor (TFT) TFT 1, TFT 2 in the first sub-pixel respectively with first group of data wire
The first data wire Data1, the second data wire Data2 connections in group, first, second thin film transistor (TFT) TFT in the second sub-pixel
1st, threeth data wire Data3, fourth data wire Data4s of the TFT 2 respectively with second group of data line group are connected, the first data wire
Data1 and the 3rd data wire Data3 polarity are identical, and the second data wire Data2 and the 4th data wire Data4 polarity are identical,
That is each sub-pixel corresponds to one group of data line group and one group of grid line groups respectively, it is noted herein that, every group
The opposite polarity of two data lines in data line group, the opposite polarity of two gate lines in every group of grid line groups.
By above two set-up mode, data wire from start to finish only exports same polarity in each sub-pixel, i.e. in Fig. 6
Data 1 and Data 3 exports positive potential signal, and Data 2 exports negative potential signal, similarly, Data1 and Data3 outputs in Fig. 7
Positive potential signal, Data2 and Data4 output negative potential signals, so jump in potential in the absence of big pressure difference, work(are driven to reducing
Consumption has certain improvement.
The operation principle of the present invention is illustrated with reference to Fig. 6：Using nth frame as just, N+1 frames be negative illustrated
Illustrate, during nth frame, first grid polar curve Gate1 is high potential, second gate line Gate2 is low potential, and Data1, Data3 are defeated
Go out anodic potentials signal, Data2 output negative pole electric potential signals, now, the first sub-pixel being connected with first grid polar curve Gate 1
The second thin film transistor (TFT) TFT 2 of the sub-pixels of first film transistor TFT 1 and second be in opening, the first sub- picture
Second thin film transistor (TFT) TFT 2 of element and the first film transistor TFT 1 of the second sub-pixel are closed, Pixel
It is charged positive potential signal；During N+1 frames, second gate line Gate2 is high potential, first grid polar curve Gate1 is low potential, the
Second thin film transistor (TFT) TFT 2 of one sub-pixel and the first film transistor TFT 2 of the second sub-pixel are in opening,
Second thin film transistor (TFT) TFT 2 of the sub-pixels of first film transistor TFT 1 and second of the first sub-pixel, which is in, closes shape
State, Pixel are charged negative potential signal, so for any one position in liquid crystal panel, have two it is opposite polarity
Data wire is connected to same sub-pixel, and its situation about leaking electricity all is identical, therefore will not cause picture exception, influence picture product
The problem of taste, occurs.
The dot structure of the present invention is applicable to thin-film transistor array base-plate and liquid crystal display panel, no longer has herein
Body repeats.
Although the present invention has shown and described with reference to specific embodiment, it should be appreciated by those skilled in the art that：
In the case where not departing from the spirit and scope of the present invention limited by claim and its equivalent, can carry out herein form and
Various change in details.
Claims (10)
- A kind of 1. dot structure, it is characterised in that：The data wire being arranged side by side including a plurality of vertical direction, a plurality of horizontal direction is simultaneously The gate line of arrangement, multiple sub-pixels, each sub-pixel include at least two thin film transistor (TFT)s and pixel electrode, a plurality of grid Every two grid line groups connect with the thin film transistor (TFT) of every row sub-pixel respectively into one group of grid line groups, every group of grid line groups in line Connect；Thin film transistor (TFT) is also connected with adjacent data wire and pixel electrode respectively in each sub-pixel；The opposite polarity of two gate lines in every group of grid line groups；The opposite polarity for two data lines being connected with thin film transistor (TFT) in each sub-pixel.
- 2. dot structure according to claim 1, it is characterised in that：In the two neighboring sub-pixel of every row, previous height The grid of the grid of one of thin film transistor (TFT) in pixel and one of thin film transistor (TFT) in the latter sub-pixel connects Connect a gate line in one group of grid line groups；The grid of another thin film transistor (TFT) in previous sub-pixel and latter height The grid of another thin film transistor (TFT) in pixel connects another gate line in this group of grid line groups；Previous sub-pixel and The drain electrode of two adjacent thin film transistor (TFT)s connects same data lines in the latter sub-pixel.
- 3. dot structure according to claim 1, it is characterised in that：In the two neighboring sub-pixel of every row, previous height The grid of the grid of one of thin film transistor (TFT) in pixel and one of thin film transistor (TFT) in the latter sub-pixel connects Connect a gate line in one group of grid line groups；The grid of another thin film transistor (TFT) in previous sub-pixel and latter height The grid of another thin film transistor (TFT) in pixel connects another gate line in this group of grid line groups；It is every in a plurality of data lines Two data lines form one group of data line group, and thin film transistor (TFT) is connected with one group of data line group respectively in each sub-pixel.
- 4. dot structure according to claim 1, it is characterised in that：Two thin film transistor (TFT)s are provided with each sub-pixel, Respectively first film transistor, the second thin film transistor (TFT), the first film transistor are connected with the second thin film transistor (TFT), its In, the source electrode of the source electrode of first film transistor and the second thin film transistor (TFT) is connected and connected with pixel electrode, and first is thin The drain electrode of film transistor and the drain electrode of the second thin film transistor (TFT) are connected with adjacent data wire respectively, the grid of first film transistor Pole connects a gate line in this group of grid line groups, and the grid of the second thin film transistor (TFT) connects another in this group of grid line groups Bar gate line.
- 5. dot structure according to claim 4, it is characterised in that：In the two neighboring sub-pixel of every row, previous height The grid of first film transistor in pixel is connected one group of grid with the grid of the first film transistor in the latter sub-pixel A gate line in polar curve group；The grid of the second thin film transistor (TFT) in previous sub-pixel and the in the latter sub-pixel The grid of two thin film transistor (TFT)s connects another gate line in this group of grid line groups；The second film in previous sub-pixel is brilliant Body pipe is connected same data lines with the drain electrode of the second thin film transistor (TFT) in the latter sub-pixel.
- 6. dot structure according to claim 4, it is characterised in that：In the two neighboring sub-pixel of every row, previous height The grid of first film transistor in pixel is connected one group of grid with the grid of the first film transistor in the latter sub-pixel A gate line in polar curve group；The grid of the second thin film transistor (TFT) in previous sub-pixel and the in the latter sub-pixel The grid of two thin film transistor (TFT)s connects another gate line in this group of grid line groups；Every two data lines group in a plurality of data lines Into one group of data line group, first film transistor, the second thin film transistor (TFT) connect with one group of data line group respectively in each sub-pixel Connect.
- 7. according to the dot structure described in claim 1-6 any one, it is characterised in that：Often go multiple sub-pixels color extremely Include three kinds of different colors less.
- 8. dot structure according to claim 7, it is characterised in that：Often the color of capable multiple sub-pixels includes three kinds of differences Color, respectively red, green, blue or the color of multiple sub-pixels of often going include four kinds of different colors, respectively red, green, blue, In vain.
- A kind of 9. array base palte, it is characterised in that：Including the dot structure as described in claim 1-8 any one.
- A kind of 10. liquid crystal display panel, it is characterised in that：Including the dot structure as described in claim 1-8 any one.
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| CN201710909091.4A CN107490916A (en) | 2017-09-29 | 2017-09-29 | Dot structure and array base palte, liquid crystal display panel |
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| CN201710909091.4A CN107490916A (en) | 2017-09-29 | 2017-09-29 | Dot structure and array base palte, liquid crystal display panel |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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