CN107483103A - OLT device and OLT device redundancy protected method - Google Patents
OLT device and OLT device redundancy protected method Download PDFInfo
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- CN107483103A CN107483103A CN201710942399.9A CN201710942399A CN107483103A CN 107483103 A CN107483103 A CN 107483103A CN 201710942399 A CN201710942399 A CN 201710942399A CN 107483103 A CN107483103 A CN 107483103A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/03—Arrangements for fault recovery
- H04B10/032—Arrangements for fault recovery using working and protection systems
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/25—Arrangements specific to fibre transmission
- H04B10/2589—Bidirectional transmission
- H04B10/25891—Transmission components
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/27—Arrangements for networking
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Abstract
The present invention relates to a kind of OLT device and OLT device redundancy protected method, the equipment includes：PON chips, including PSG output ends, PSG inputs and at least two PON mouths；Programmadle logic device, including multiple input/output terminals, the PSG output ends are connected to an input/output terminal, and the PSG inputs are connected to another input/output terminal；Master controller, the control instruction of main PON mouths and standby PON mouths is set for sending, when the link of EPON breaks down, the PSG inputs corresponding with the standby PON mouths of the PSG output ends according to corresponding to the control instruction by the main PON mouths connect the Programmadle logic device.Above-mentioned OLT device and OLT device redundancy protected method design is simple, and cost is low, if link breaks down so that the PSG inputs corresponding with standby PON mouths of PSG output ends corresponding to main PON mouths connect, and so as to complete the function of PSG redundancy protectings, control is flexible, convenient.
Description
Technical field
The present invention relates to EPON field, more particularly to a kind of OLT device and OLT device redundancy protected method.
Background technology
Passive optical network PON (Passive Optical Network, PON) is the direction of access network future development.Due to
The bandwidth that PON is provided can meet the needs of present and following various broadband services, so the quilt on solving the problems, such as broadband access
Generally have an optimistic view of.With PON extensive use, how to ensure in pon the service reliability of corporate client or mobile subscriber into
For operator's question of common concern, PSG redundancy protectings arise at the historic moment.Existing PSG redundancy protected methods master in the market
There are two kinds：1) switching device is set between the PON mouths on optical line terminal (Optical Line Terminal, OLT)
Realize fibre circuit PSG redundancy protectings.This method makes OLT ends complex designing, controls underaction, and switching PON mouths need
Time is longer, and design cost is higher；2) double PON are set on optical network unit (Optical Network Unit, ONU)
Mouthful, and switching device is set to realize fibre circuit PSG redundancy protectings between PON mouths.This method make it that ONU end design is multiple
It is miscellaneous, underaction is controlled, the time that switching PON mouths need is longer, and design cost is higher.
The content of the invention
Based on this, it is necessary to provide a kind of simple design, low cost, the flexible OLT device of control and OLT device redundancy and protect
Maintaining method.
A kind of OLT device, including：
PON chips, including PSG output ends, PSG inputs and at least two PON mouths；
Programmadle logic device, including multiple input/output terminals, the PSG output ends are connected to an input/output terminal, institute
State PSG inputs and be connected to another input/output terminal；
Master controller, the control instruction of main PON mouths and standby PON mouths is set for sending, and the Programmadle logic device exists
When the link of EPON breaks down, according to corresponding to the control instruction by the main PON mouths PSG output ends with it is described
PSG inputs connection corresponding to standby PON mouths.
In one of the embodiments, the master controller includes CPU.
In one of the embodiments, each OLT device includes at least one PON chips.
In one of the embodiments, the model CS8022 of the PON chips.
In one of the embodiments, the master controller is compiled by the data wire and clock line of I2C buses with described
The input/output terminal for collecting logical device is attached；The Programmadle logic device is erasable Programmadle logic device.
On the other hand, the present invention also proposes a kind of OLT device redundancy protected method, the OLT device include PON chips,
Programmadle logic device, master controller, the PON chips include PSG output ends, PSG inputs and at least two PON mouths；Institute
The method of stating includes：
The master controller sends the control instruction for setting main PON mouths and standby PON mouths；
The Programmadle logic device carries out main PON mouths according to the control instruction to the PON chips and standby PON mouths are set
Put, if link breaks down so that the PSG inputs corresponding with the standby PON mouths of PSG output ends corresponding to the main PON mouths connect.
In one of the embodiments, the Programmadle logic device enters according to the control instruction to the PON chips
The row mouth is set, if link breaks down so that PSG output ends corresponding to the main PON mouths are corresponding with the standby PON mouths
Also include after the step of PSG inputs connect：
After checking link breaks down, the input corresponding with the standby PON mouths of output end corresponding to the main PON mouths is
It is no to have completed to connect.
In one of the embodiments, the PON chips include m PON mouth, and m is the natural number more than 1；It is described to compile
Collect logical device and the mouth setting is carried out to the PON chips according to the control instruction, if link breaks down so that described
The step of PSG inputs corresponding with the standby PON mouths of PSG output ends corresponding to main PON mouths connect be specially：
The first control register, the control second of first PON mouth of control are set in the Programmadle logic device
Second control register ... ... of individual PON mouths, control the m control registers of m-th of PON mouth；
After the Programmadle logic device receives the control instruction, according to the judgment rule of setting to the PON chips
Each PON mouths judged, determine the main PON mouths and the standby PON mouths.
If link breaks down, control the PSG corresponding with the standby PON mouths of PSG output ends corresponding to the main PON mouths defeated
Enter end connection.
In one of the embodiments, the first of first PON mouth of control is set in the Programmadle logic device
Control register, the second control register ... ... for controlling second PON mouth, control the m control deposits of m-th of PON mouth
The step of device is specially：
First control register, the second control deposit are set in the Programmadle logic device
Device ..., the address of the m control registers and each corresponding PON mouths.
In one of the embodiments, after the Programmadle logic device receives the control instruction, advised according to the judgement of setting
The step of then judging each PON mouths of the PON chips, determining the main PON mouths and the standby PON mouths includes：
After the Programmadle logic device receives the control instruction, according to case statement determine the main PON mouths and
The standby PON mouths.
Above-mentioned OLT device and OLT device redundancy protected method, OLT device include PON chips, Programmadle logic device and
Master controller, PON chips include at least two PON mouths, PSG output ends and PSG inputs, and design is simple, and cost is low；Pass through master
Controller sends the control instruction for setting main PON mouths and standby PON mouths, and Programmadle logic device is according to control instruction to PON chips
The setting of main PON mouths and standby PON mouths is carried out, if link breaks down so that PSG output ends corresponding to main PON mouths and standby PON mouths
Corresponding PSG inputs connection, so as to complete the function of PSG redundancy protectings, control is flexible, convenient.
Brief description of the drawings
Fig. 1 is the block diagram of OLT device in an embodiment；
Fig. 2 is the flow chart of OLT device redundancy protected method in an embodiment；
Fig. 3 is the flow chart of OLT device redundancy protected method in another embodiment.
Embodiment
Fig. 1 is the block diagram of OLT device in an embodiment.
In the present embodiment, the OLT device includes master controller 10, Programmadle logic device 20 and PON chips 30.PON
Chip 30 includes PSG output ends, PSG inputs and at least two PON mouths.Programmadle logic device 20 includes multiple input and output
End, the PSG output ends of PON chips 30 are connected to an input/output terminal, and PSG inputs are connected to another input/output terminal.Main control
Device 10 is used to send the control instruction for setting main PON mouths and standby PON mouths, and Programmadle logic device 20 is sent out in the link of EPON
During raw failure, the PSG inputs corresponding with standby PON mouths of the PSG output ends according to corresponding to the control instruction by main PON mouths connect.
In one embodiment, master controller 10 includes CPU.
In one embodiment, each OLT device includes two PON chips 30, and wherein the one of a PON chip 30
Individual PON mouths are set to be arranged to for PON mouths, in EPON for main PON mouths, one of PON mouths of another PON chip 30
Link when breaking down, Programmadle logic device 20 is according to corresponding to the control instruction that master controller 10 is sent by main PON mouths
PSG output ends PSG inputs corresponding with standby PON mouths connect.In one of the embodiments, the model of PON chips
CS8022。
In one embodiment, Programmadle logic device 20 is erasable Programmadle logic device.
In one embodiment, the data wire and clock line and Programmadle logic device that master controller 10 passes through I2C buses
20 input/output terminal is attached.
Fig. 2 is the flow chart of OLT device redundancy protected method in an embodiment.
In the present embodiment, the OLT device redundancy protected method includes：
S100, master controller send the control instruction for setting main PON mouths and standby PON mouths.
Master controller 10 sends the control instruction of the main PON mouths of setting and standby PON mouths to Programmadle logic device 20, into step
Rapid S200.
S200, Programmadle logic device carry out the setting of main PON mouths and standby PON mouths according to control instruction to PON chips.
Because PON chips 30 comprise at least two PON mouths, control of the Programmadle logic device 20 in step S100 refers to
Order carries out main PON mouths to the PON chips 30 and standby PON mouths are set so that when the link of EPON breaks down, into step
Rapid S300.
S300, the PSG inputs corresponding with standby PON mouths of PSG output ends corresponding to main PON mouths connect.
The internal logic of Programmadle logic device 20 is by the PSG corresponding with standby PON mouths of PSG output ends corresponding to main PON mouths
Input connects, and during so as to ensure that the primary link where main PON mouths breaks down, the data of primary link can pass through standby PON mouths institute
Reserve link be transmitted.
Above-mentioned OLT device and OLT device redundancy protected method, OLT device include PON chips 30, Programmadle logic device
20 and master controller 10, PON chips 30 include at least two PON mouths, PSG output ends and PSG inputs, and design is simple, cost
It is low；The control instruction that main PON mouths and standby PON mouths are set is sent by master controller 10, Programmadle logic device 20 is according to control
Instruction carries out the setting of main PON mouths and standby PON mouths to PON chips, if link breaks down so that PSG corresponding to main PON mouths is defeated
Go out end PSG inputs corresponding with standby PON mouths to connect, so as to complete the function of PSG redundancy protectings, control is flexible, convenient.
Fig. 3 is the flow chart of OLT device redundancy protected method in another embodiment.
In the present embodiment, OLT device includes PON chips 30, Programmadle logic device 20, master controller 10, the PON
Chip includes PSG output ends, PSG inputs and at least two PON mouths, and the OLT device redundancy protected method includes：
S110, master controller send the control instruction for setting main PON mouths and standby PON mouths.
Master controller 10 sends the control instruction of the main PON mouths of setting and standby PON mouths to Programmadle logic device 20, into step
Rapid S120.
S120, set in Programmadle logic device the first control register, the second control register ..., m
The address of control register and each corresponding PON mouths.
PON chips 30 include m PON mouth, and m is the natural number more than 1, is set in Programmadle logic device 20 correspondingly
First control register of first PON mouth, correspondingly the second control register of second PON mouth ..., correspond to m-th
The respective address of m control registers of PON mouths and PSG conversions.
In one embodiment, a PON chip 30 includes 4 PON mouths, and two PON chips 30 include 8 PON mouths.When
Write register address for 04 when, write PSG_REG0 control registers, when write register address for 05 when, write-in PSG_REG1 control
Register processed, when it is 06 to write register address, PSG_REG2 control registers are write, when it is 07 to write register address, write
Enter PSG_REG3 control registers, when it is 08 to write register address, PSG_REG4 control registers are write, when with writing register
When location is 09, PSG_REG5 control registers are write, when it is 0A to write register address, write PSG_REG6 control registers,
When it is 0B to write register address, PSG_REG7 control registers are write.In one of the embodiments, using Verilog
HDL language is realized as follows：
It is as follows to define control register：
S130, after Programmadle logic device receives control instruction, main PON mouths and standby PON mouths are determined according to case statement.
After Programmadle logic device 20 receives the main PON mouths of setting of the transmission of master controller 10 and the control instruction of standby PON mouths,
Main PON mouths and standby PON mouths are determined according to case statement.
S140, if link breaks down, the PSG corresponding with standby PON mouths of PSG output ends corresponding to main PON mouths is controlled to input
End connection.
If link breaks down, Programmadle logic device 20 according to the main PON mouths judged in step S130 and standby PON mouths,
The PSG inputs corresponding with standby PON mouths of PSG output ends corresponding to main PON mouths are controlled to connect.
In one embodiment, in the step s 120 on the basis of control register definition, step S130 and step S140
Verilog HDL language can also be used to realize, detailed process is as follows：
0x10 represents first PON mouth, and 0x11 represents second PON mouth, and 0x12 represents the 3rd PON mouth, and 0x13 is represented
4th PON mouth, 0x14 represent the 5th PON mouth, and 0x15 represents the 6th PON mouth, and 0x16 represents the 7th PON mouth, 0x17
Represent the 8th PON mouth.
In one of the embodiments, it is for PON mouths, specific master controller that master controller 10, which sets first PON mouth,
10 can be toward controlling the control register PSG_REG0 of the PON mouths to write 1, and Programmadle logic device 20 is according to corresponding to other PON mouths
Control register PSG_REG [n] value judges main PON mouths, and then controls PSG output ends (PSG_OUT corresponding to main PON mouths
[x]) corresponding with standby PON mouths PSG inputs (PSG_IN [0]) connect.Realized using Verilog HDL language as follows：
Assign PSG_IN [0]=(PSG_REG0==8'h11)PSG_OUT[1]:
(PSG_REG0==8'h12)PSG_OUT[2]:
(PSG_REG0==8'h13)PSG_OUT[3]:
(PSG_REG0==8'h14)PSG_OUT[4]:
(PSG_REG0==8'h15)PSG_OUT[5]:
(PSG_REG0==8'h16)PSG_OUT[6]:
(PSG_REG0==8'h17)PSG_OUT[7]:1'b0；
In one of the embodiments, it is for PON mouths, specific master controller that master controller 10, which sets second PON mouth,
10 can be toward controlling the control register PSG_REG1 of the PON mouths to write 1, and Programmadle logic device 20 is according to control register PSG_
REG [n] value judges main PON mouths, controls PSG output ends corresponding to main PON mouths (PSG_OUT [x]) corresponding with standby PON mouths
PSG inputs (PSG_IN [1]) connect.Realized using Verilog HDL language as follows：
Assign PSG_IN [1]=(PSG_REG1==8'h10)PSG_OUT[0]:
(PSG_REG1==8'h12)PSG_OUT[2]:
(PSG_REG1==8'h13)PSG_OUT[3]:
(PSG_REG1==8'h14)PSG_OUT[4]:
(PSG_REG1==8'h15)PSG_OUT[5]:
(PSG_REG1==8'h16)PSG_OUT[6]:
(PSG_REG1==8'h17)PSG_OUT[7]:1'b0；
In one of the embodiments, it is for PON mouths, specific master controller that master controller 10, which sets the 3rd PON mouth,
10 can be toward controlling the control register PSG_REG2 of the PON mouths to write 1, and Programmadle logic device 20 is according to control register PSG_
REG [n] value judges main PON mouths, controls PSG output ends corresponding to main PON mouths (PSG_OUT [x]) corresponding with standby PON mouths
PSG inputs (PSG_IN [2]) connect.Realized using Verilog HDL language as follows：
Assign PSG_IN [2]=(PSG_REG2==8'h10)PSG_OUT[0]:
(PSG_REG2==8'h11)PSG_OUT[1]:
(PSG_REG2==8'h13)PSG_OUT[3]:
(PSG_REG2==8'h14)PSG_OUT[4]:
(PSG_REG2==8'h15)PSG_OUT[5]:
(PSG_REG2==8'h16)PSG_OUT[6]:
(PSG_REG2==8'h17)PSG_OUT[7]:1'b0；
In one of the embodiments, it is for PON mouths, specific master controller that master controller 10, which sets the 4th PON mouth,
10 can be toward controlling the control register PSG_REG3 of the PON mouths to write 1, and Programmadle logic device 20 is according to control register PSG_
REG [n] value judges main PON mouths, controls PSG output ends corresponding to main PON mouths (PSG_OUT [x]) corresponding with standby PON mouths
PSG inputs (PSG_IN [3]) connect.Realized using Verilog HDL language as follows：
Assign PSG_IN [3]=(PSG_REG3==8'h10)PSG_OUT[0]:
(PSG_REG3==8'h11)PSG_OUT[1]:
(PSG_REG3==8'h12)PSG_OUT[2]:
(PSG_REG3==8'h14)PSG_OUT[4]:
(PSG_REG3==8'h15)PSG_OUT[5]:
(PSG_REG3==8'h16)PSG_OUT[6]:
(PSG_REG3==8'h17)PSG_OUT[7]:1'b0；
In one of the embodiments, it is for PON mouths, specific master controller that master controller 10, which sets the 5th PON mouth,
10 can be toward controlling the control register PSG_REG4 of the PON mouths to write 1, and Programmadle logic device 20 is according to control register PSG_
REG [n] value judges main PON mouths, controls PSG output ends corresponding to main PON mouths (PSG_OUT [x]) corresponding with standby PON mouths
PSG inputs (PSG_IN [4]) connect.Realized using Verilog HDL language as follows：
Assign PSG_IN [4]=(PSG_REG4==8'h11)PSG_OUT[1]:
(PSG_REG4==8'h12)PSG_OUT[2]:
(PSG_REG4==8'h13)PSG_OUT[3]:
(PSG_REG4==8'h10)PSG_OUT[0]:
(PSG_REG4==8'h15)PSG_OUT[5]:
(PSG_REG4==8'h16)PSG_OUT[6]:
(PSG_REG4==8'h17)PSG_OUT[7]:1'b0；
In one of the embodiments, it is for PON mouths, specific master controller that master controller 10, which sets the 6th PON mouth,
10 can be toward controlling the control register PSG_REG5 of the PON mouths to write 1, and Programmadle logic device 20 is according to control register PSG_
REG [n] value judges main PON mouths, controls PSG output ends corresponding to main PON mouths (PSG_OUT [x]) corresponding with standby PON mouths
PSG inputs (PSG_IN [5]) connect.Realized using Verilog HDL language as follows：
Assign PSG_IN [5]=(PSG_REG5==8'h11)PSG_OUT[1]:
(PSG_REG5==8'h12)PSG_OUT[2]:
(PSG_REG5==8'h13)PSG_OUT[3]:
(PSG_REG5==8'h14)PSG_OUT[4]:
(PSG_REG5==8'h10)PSG_OUT[0]:
(PSG_REG5==8'h16)PSG_OUT[6]:
(PSG_REG5==8'h17)PSG_OUT[7]:1'b0；
In one of the embodiments, it is for PON mouths, specific master controller that master controller 10, which sets the 7th PON mouth,
10 can be toward controlling the control register PSG_REG6 of the PON mouths to write 1, and Programmadle logic device 20 is according to control register PSG_
REG [n] value judges main PON mouths, controls PSG output ends corresponding to main PON mouths (PSG_OUT [x]) corresponding with standby PON mouths
PSG inputs (PSG_IN [6]) connect.Realized using Verilog HDL language as follows：
Assign PSG_IN [6]=(PSG_REG6==8'h11)PSG_OUT[1]:
(PSG_REG6==8'h12)PSG_OUT[2]:
(PSG_REG6==8'h13)PSG_OUT[3]:
(PSG_REG6==8'h14)PSG_OUT[4]:
(PSG_REG6==8'h15)PSG_OUT[5]:
(PSG_REG6==8'h10)PSG_OUT[0]:
(PSG_REG6==8'h17)PSG_OUT[7]:1'b0；
In one of the embodiments, it is for PON mouths, specific master controller that master controller 10, which sets the 8th PON mouth,
10 can be toward controlling the control register PSG_REG7 of the PON mouths to write 1, and Programmadle logic device 20 is according to control register PSG_
REG [n] value judges main PON mouths, controls PSG output ends corresponding to main PON mouths (PSG_OUT [x]) corresponding with standby PON mouths
PSG inputs (PSG_IN [7]) connect.Realized using Verilog HDL language as follows：
Assign PSG_IN [7]=(PSG_REG7==8'h11)PSG_OUT[1]:
(PSG_REG7==8'h12)PSG_OUT[2]:
(PSG_REG7==8'h13)PSG_OUT[3]:
(PSG_REG7==8'h14)PSG_OUT[4]:
(PSG_REG7==8'h15)PSG_OUT[5]:
(PSG_REG7==8'h16)PSG_OUT[6]:
(PSG_REG7==8'h10)PSG_OUT[0]:1'b0；
S150, after checking link breaks down, whether the input corresponding with standby PON mouths of output end corresponding to main PON mouths
Complete to connect.
After the completion of step S140, analog link breaks down, and after verifying that the link breaks down, main PON mouths are corresponding
PSG output ends PSG inputs corresponding with standby PON mouths whether completed to connect, so that it is guaranteed that the link realizes that data are superfluous
Remaining protection.
Above-mentioned OLT device redundancy protected method, OLT device include PON chips 30, Programmadle logic device 20 and main control
Device 10, PON chips 30 include at least two PON mouths, PSG output ends and PSG inputs, and design is simple, and cost is low；Pass through master control
Device 10 processed sends the control instruction for setting main PON mouths and standby PON mouths, and Programmadle logic device 20 is according to control instruction to PON cores
Piece carries out the setting of main PON mouths and standby PON mouths, if link breaks down so that PSG output ends corresponding to main PON mouths and standby PON
PSG inputs connection corresponding to mouthful；Analog link breaks down, after verifying that the link breaks down, corresponding to main PON mouths
Whether output end input corresponding with standby PON mouths has been completed to connect, so as to complete the function of PSG redundancy protectings, control spirit
It is living, it is convenient.
Each technical characteristic of embodiment described above can be combined arbitrarily, to make description succinct, not to above-mentioned reality
Apply all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, the scope that this specification is recorded all is considered to be.
Embodiment described above only expresses the several embodiments of the present invention, and its description is more specific and detailed, but simultaneously
Can not therefore it be construed as limiting the scope of the patent.It should be pointed out that come for one of ordinary skill in the art
Say, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the present invention
Scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (10)
- A kind of 1. OLT device, it is characterised in that including：PON chips, including PSG output ends, PSG inputs and at least two PON mouths；Programmadle logic device, including multiple input/output terminals, the PSG output ends are connected to an input/output terminal, the PSG Input is connected to another input/output terminal；Master controller, the control instruction of main PON mouths and standby PON mouths is set for sending, and the Programmadle logic device is passive When the link of optical-fiber network breaks down, according to corresponding to the control instruction by the main PON mouths PSG output ends with it is described standby PSG inputs corresponding to PON mouths connect.
- 2. OLT device according to claim 1, it is characterised in that the master controller includes CPU.
- 3. OLT device according to claim 1, it is characterised in that each OLT device includes at least one PON Chip.
- 4. OLT device according to claim 1, it is characterised in that the model CS8022 of the PON chips.
- 5. OLT device according to claim 1, it is characterised in that the master controller by the data wires of I2C buses and The input/output terminal of clock line and the Programmadle logic device is attached；The Programmadle logic device is erasable compiles Collect logical device.
- 6. a kind of OLT device redundancy protected method, it is characterised in that the OLT device includes PON chips, Programmadle logic device Part, master controller, the PON chips, which include PSG output ends, PSG inputs and at least two PON mouths, methods described, to be included：The master controller sends the control instruction for setting main PON mouths and standby PON mouths；The Programmadle logic device carries out main PON mouths according to the control instruction to the PON chips and standby PON mouths are set Put, if link breaks down so that the PSG inputs corresponding with the standby PON mouths of PSG output ends corresponding to the main PON mouths Connection.
- 7. OLT device redundancy protected method according to claim 6, it is characterised in that the Programmadle logic device root The mouth setting is carried out to the PON chips according to the control instruction, if link breaks down so that the main PON mouths are corresponding PSG output ends PSG inputs corresponding with standby PON mouths the step of connecting after also include：After checking link breaks down, whether the input corresponding with the standby PON mouths of output end corresponding to the main PON mouths Through completing to connect.
- 8. OLT device redundancy protected method according to claim 6, it is characterised in that the PON chips include m PON Mouthful, m is the natural number more than 1；The Programmadle logic device carries out the mouth according to the control instruction to the PON chips Set, if link breaks down so that the PSG inputs corresponding with the standby PON mouths of PSG output ends corresponding to the main PON mouths End connection the step of be specially：Second the first control register, the control PON of first PON mouth of control are set in the Programmadle logic device Second control register ... ... of mouth, control the m control registers of m-th of PON mouth；After the Programmadle logic device receives the control instruction, according to the judgment rule of setting to each of the PON chips The individual PON mouths are judged, determine the main PON mouths and the standby PON mouths.If link breaks down, the PSG inputs corresponding with the standby PON mouths of PSG output ends corresponding to the main PON mouths are controlled Connection.
- 9. OLT device redundancy protected method according to claim 8, it is characterised in that in the Programmadle logic device Inside set the second control deposit of second the first control register, control PON mouth of first PON mouth of control Device ... ..., it is specially the step of the m control registers for controlling m-th PON mouth：Set in the Programmadle logic device first control register, second control register ..., The address of the m control registers and each corresponding PON mouths.
- 10. OLT device redundancy protected method according to claim 8, it is characterised in that the Programmadle logic device connects After receiving the control instruction, each PON mouths of the PON chips are judged according to the judgment rule of setting, judged The step of going out the main PON mouths and the standby PON mouths includes：After the Programmadle logic device receives the control instruction, main PON mouths and described are determined according to case statement Standby PON mouths.
Priority Applications (1)
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