CN107482020A - A kind of array base palte and its manufacture method - Google Patents

A kind of array base palte and its manufacture method Download PDF

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Publication number
CN107482020A
CN107482020A CN201710718137.4A CN201710718137A CN107482020A CN 107482020 A CN107482020 A CN 107482020A CN 201710718137 A CN201710718137 A CN 201710718137A CN 107482020 A CN107482020 A CN 107482020A
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China
Prior art keywords
pixel electrode
substrate
array base
base palte
hole
Prior art date
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Pending
Application number
CN201710718137.4A
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Chinese (zh)
Inventor
王跃林
赵艳艳
徐敬义
李磊
方业周
刘铁男
任艳伟
付弋珊
秦伟达
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Application filed by BOE Technology Group Co Ltd, Ordos Yuansheng Optoelectronics Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201710718137.4A priority Critical patent/CN107482020A/en
Publication of CN107482020A publication Critical patent/CN107482020A/en
Priority to US16/106,105 priority patent/US10504938B2/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
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    • G02—OPTICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
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Abstract

The invention discloses a kind of array base palte and its manufacture method.Array base palte includes：First substrate, the first substrate have the drain electrode exposed from its side；The flatness layer for exposing drain electrode side in the first substrate is formed, the flatness layer is provided with the stepped hole on the drain electrode, and the aperture of the stepped hole diminishes from the direction of the laterally closer first substrate of one of the flatness layer away from the first substrate；Pixel electrode, the pixel electrode are formed at the stepped hole and connected with the drain electrode；Cover the passivation layer of the flatness layer and the pixel electrode；The public electrode formed on the passivation layer.The array base palte and its manufacture method of the present invention, compared with prior art, solve passivation layer caused by existing array base palte passivation layer has the high segment difference of a pixel electrode thickness in the intersecting position of pixel electrode and flatness layer and easily crimp the technical problem to come off.

Description

A kind of array base palte and its manufacture method
Technical field
The present invention relates to field of liquid crystal display, more particularly to a kind of array base palte and its manufacture method.
Background technology
Existing array base palte, as shown in figure 1, including glass substrate 10, cushion 20, active layer 30, gate insulator 41, grid 42, source electrode 51, drain electrode 52, interlayer insulating film 53, flatness layer 60, pixel electrode 70, passivation layer 80 and public electrode 90.Flatness layer 60 is provided with the via on drain electrode 52, and pixel electrode 70 covers via and is connected with drain electrode 52；Passivation layer 80 covers Flatness layer 60 and pixel electrode 70, public electrode 90 are formed on passivation layer 80.Array base palte shown in Fig. 1, pixel electrode 70 and the Electric Field Distribution that is formed of two layers electrode of public electrode 90 it is more uniform, the dead angle of no electric field is few, uses the array base palte The transmitance of display panel is higher.But because pixel electrode 70 is formed in the surface of flatness layer 60, cause pixel electrode 70 Flatness layer 60 is protruded from, and the height for protruding from flatness layer is the thickness of pixel electrode 70, i.e., pixel electrode protrudes flatness layer one The thickness of individual pixel electrode.So, passivation layer will necessarily have a pixel electricity in the intersecting position of pixel electrode and flatness layer The segment difference of pole thickness, the height of this segment difference are directly to be determined by pixel electrode, are immutable.Because passivation layer is in pixel electricity There is the high segment difference of a pixel electrode thickness in the position that pole and flatness layer intersect, cause passivation layer in pixel electrode and flatness layer Intersecting position easily occurs curling and come off, and then causes the fraction defective of array base palte higher, uses the liquid crystal of the array base palte The bad of stain be present in panel.
The content of the invention
The invention provides a kind of array base palte and its manufacture method, compared with prior art, solves existing array Passivation caused by substrate passivation layer has the high segment difference of a pixel electrode thickness in the intersecting position of pixel electrode and flatness layer Layer easily crimps the technical problem to come off.
To reach above-mentioned purpose, the present invention provides following technical scheme：
A kind of array base palte, including：
First substrate, the first substrate have the drain electrode exposed from its side；
The flatness layer for exposing drain electrode side in the first substrate is formed, the flatness layer is provided with the drain electrode Stepped hole, and the aperture of the stepped hole is from laterally closer first base of one of the flatness layer away from the first substrate The direction of plate diminishes；
Pixel electrode, the pixel electrode are formed at the stepped hole and connected with the drain electrode；
Cover the passivation layer of the flatness layer and the pixel electrode；
The public electrode formed on the passivation layer.
As a kind of optional mode, the height between the upper surface of the flatness layer and the upper surface of the pixel electrode The absolute value of difference is less than the height of the pixel electrode；
Wherein, the upper surface of the flatness layer refers to beyond the flatness layer stepped hole partially away from the first substrate The surface of side, the upper surface of the pixel electrode is that the pixel electrode is located at first substrate described in distance in the stepped hole The surface of the side of the remote first substrate of the upper part of farthest step.
It is equal with the upper surface of the flatness layer as a kind of optional mode, the upper surface of the pixel electrode；
Or the upper surface of the pixel electrode protrudes from the upper surface of flatness layer and the height of protrusion is less than pixel electrode Thickness；
Or the upper surface of the pixel electrode recessed is less than pixel electricity in the upper surface of the flatness layer and recessed depth The thickness of pole.
As a kind of optional mode, in the stepped hole shape in the aperture in the farthest hole of first substrate described in distance and Size is consistent with the shape and size of the pixel electrode of the array base palte.
As a kind of optional mode, the array base palte is bottom gate type array base palte or top gate type array base palte.
The present invention also provides following technical scheme：
A kind of manufacture method of array base palte, comprises the following steps：
First substrate is formed, the first substrate has the drain electrode exposed from its side；
Formed and cover the flatness layer that the first substrate exposes the drain electrode side；
Stepped hole is opened up in the position that the flatness layer is located on the drain electrode, and the aperture of the stepped hole is described in The direction of the laterally closer first substrate of the flatness layer away from the first substrate diminishes；
Pixel electrode is formed, the pixel electrode is formed at the stepped hole and connected with the drain electrode；
Form the passivation layer for covering the flatness layer and the pixel electrode；
Public electrode is formed on the passivation layer.
As a kind of optional mode, the step of opening up stepped hole in the position that the flatness layer is located on the drain electrode Specifically comprise the following steps：
Described in being opened up by the exposure and etching of mask plate in the position that the flatness layer be located on the drain electrode Stepped hole, the mask plate crosses through hole and the part around through hole and being attached thereto is crossed positioned at the full impregnated including full impregnated passes through area Domain；
Wherein, the full impregnated crosses through hole and is used to form the hole that first substrate described in distance is nearest in the stepped hole, described Part penetrating region is used for the hole formed beyond the hole that first substrate described in distance is nearest in the stepped hole.
As a kind of optional mode, first substrate described in distance in the stepped hole that the part penetrating region is formed The absolute value of the depth in farthest hole and the thickness difference of the pixel electrode of the array base palte is less than the thickness value of pixel electrode.
As a kind of optional mode, first substrate described in distance in the stepped hole that the part penetrating region is formed The depth in farthest hole is equal to the thickness of the pixel electrode needed for the array base palte；
Or in the stepped hole that is formed of the part penetrating region the farthest hole of first substrate described in distance depth Less than the thickness of the pixel electrode needed for the array base palte；
Or in the stepped hole that is formed of the part penetrating region the farthest hole of first substrate described in distance depth Twice of thickness more than the pixel electrode needed for the array base palte and the thickness less than pixel electrode.
As a kind of optional mode, the shape and chi of the part penetrating region and full penetrating region as an entirety The very little shape and size with the pixel electrode of the array base palte are engaged so that first substrate described in distance in the stepped hole The shape in farthest hole is consistent with the shape and size of the pixel electrode of the array base palte with size.
Array base palte provided by the invention, including first substrate, flatness layer, pixel electrode, passivation layer and public electrode, its In, first substrate has the drain electrode exposed from its side, and flatness layer is formed exposes drain electrode side in first substrate, and flatness layer is provided with Stepped hole on drain electrode, and the aperture of stepped hole is from the laterally closer first substrate of one of flatness layer away from first substrate Direction diminishes；Pixel electrode is formed at stepped hole and connected with drain electrode；Passivation layer covers flatness layer and pixel electrode；Common electrical Pole is formed on passivation layer.So, the position due to flatness layer on drain electrode is provided with stepped hole, and the aperture of stepped hole is certainly The direction of a laterally closer first substrate of the flatness layer away from first substrate diminishes, at the stepped hole that pixel electrode is formed, i.e. picture Plain electrode is formed at the stepped hole in the direction being recessed to first substrate direction, and pixel electrode is with flatness layer stepped hole with outside The surface of the side away from first substrate is divided to compare, the height of pixel electrode protrusion is bound to less than the thickness of pixel electrode, or Person's pixel electrode is less than the surface of the side partially away from first substrate beyond flatness layer stepped hole.So, in pixel electricity , can be by controlling the height in the step pitch-row hole farthest from first substrate to control pixel electrode with putting down when the thickness of pole is definite value Partially away from the segment difference between the surface of the side of first substrate beyond smooth layer stepped hole, realize passivation layer in pixel electrode and The segment difference of the intersecting position of flatness layer is controllable.By controlling passivation layer in the section of the intersecting position of pixel electrode and flatness layer Difference is less than the thickness of pixel electrode, it is possible to achieve reduces passivation layer because being crimped in the intersecting position of pixel electrode and flatness layer The probability to come off, and then the yield of array base palte is improved, the bad probability that stain using the liquid crystal panel of the substrate be present Also just decrease.
Brief description of the drawings
Fig. 1 is the schematic diagram of existing array base palte；
Fig. 2 is the schematic diagram of the array base palte of one embodiment of the present of invention；
Fig. 3 is the schematic diagram in the flatness layer top bar hole of the array base palte shown in Fig. 2；
Fig. 4 is the flow chart of the manufacture method of the array base palte of the present invention；
Fig. 5 be Fig. 4 described in array base palte manufacture method in used by flatness layer opens up stepped hole mask plate Partial schematic diagram.
Main element description of reference numerals：
In the prior art：
10 glass substrates, 20 cushions, 30 active layers, 41 gate insulators, 42 grids, 51 source electrodes,
52 drain electrodes, 53 interlayer insulating films, 60 flatness layers, 70 pixel electrodes, 80 passivation layers,
90 public electrodes.
In the present invention：
100 drain electrodes,
200 flatness layers, 210 stepped holes,
The hole nearest apart from first substrate in 211 stepped holes, the hole farthest apart from first substrate in 212 stepped holes,
300 pixel electrodes, 400 passivation layers, 500 public electrodes,
600 first substrates, 610 glass substrates, 620 cushions, 630 active layers, 641 gate insulators,
642 grids, 651 source electrodes, 652 interlayer insulating films.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made Embodiment, belong to the scope of protection of the invention.
Embodiment one
The array base palte of embodiments of the invention one, as shown in Figures 2 and 3, including：
First substrate 600, first substrate have the drain electrode 100 exposed from its side；
The flatness layer 200 for exposing drain electrode side in first substrate is formed, flatness layer 200 is provided with drain electrode 100 Stepped hole 210, and the aperture of stepped hole 210 is from the direction of the laterally closer first substrate of one of flatness layer 200 away from first substrate Diminish, the hole nearest apart from first substrate is represented with 211 in stepped hole, and the hole farthest apart from first substrate is with 212 in stepped hole；
Pixel electrode 300, pixel electrode 300 are formed at stepped hole 210 and are connected with drain electrode 100；
Cover the passivation layer 400 of flatness layer 200 and pixel electrode 300；
The public electrode 500 formed on passivation layer 400.
The array base palte of the present embodiment, including first substrate, flatness layer, pixel electrode, passivation layer and public electrode, its In, first substrate has the drain electrode exposed from its side, and flatness layer is formed exposes drain electrode side in first substrate, and flatness layer is provided with Stepped hole on drain electrode, and the aperture of stepped hole is from the laterally closer first substrate of one of flatness layer away from first substrate Direction diminishes；Pixel electrode is formed at stepped hole and connected with drain electrode；Passivation layer covers flatness layer and pixel electrode；Common electrical Pole is formed on passivation layer.So, the position due to flatness layer on drain electrode is provided with stepped hole, and the aperture of stepped hole is certainly The direction of a laterally closer first substrate of the flatness layer away from first substrate diminishes, at the stepped hole that pixel electrode is formed, i.e. picture Plain electrode is formed at the stepped hole in the direction being recessed to first substrate direction, and pixel electrode is with flatness layer stepped hole with outside The surface of the side away from first substrate is divided to compare, the height of pixel electrode protrusion is bound to less than the thickness of pixel electrode, or Person's pixel electrode is less than the surface of the side partially away from first substrate beyond flatness layer stepped hole.So, in pixel electricity When the thickness of pole is definite value, can by control hole farthest apart from first substrate in stepped hole height control pixel electrode with Partially away from the segment difference between the surface of the side of first substrate beyond flatness layer stepped hole, passivation layer is realized in pixel electrode The segment difference for the position intersected with flatness layer is controllable.By controlling passivation layer in the intersecting position of pixel electrode and flatness layer Segment difference is less than the thickness of pixel electrode, it is possible to achieve reduces passivation layer because being rolled up in the intersecting position of pixel electrode and flatness layer The probability that song comes off, and then improve the yield of array base palte, the bad several of stain be present using the liquid crystal panel of the substrate Rate also just decreases.
Segment difference of the passivation layer in the intersecting position of pixel electrode and flatness layer is controllable, and it is targeted that we, which control, , the specific aim of control is specially：The absolute value of difference in height between the upper surface of flatness layer and the upper surface of pixel electrode is small In the height of pixel electrode；
Wherein, the upper surface of flatness layer refers to the surface of the side partially away from first substrate beyond flatness layer stepped hole, The upper surface of pixel electrode is the upper part that pixel electrode is located at step farthest apart from first substrate in stepped hole away from the The surface of the side of one substrate.
So, segment difference of the passivation layer in the intersecting position of pixel electrode and flatness layer is less than the thickness of pixel electrode, can be with Realizing reduces the probability that passivation layer comes off because curling occurs in the intersecting position of pixel electrode and flatness layer, and then improves array The yield of substrate, the bad probability that stain using the liquid crystal panel of the substrate be present also just are decreased.
The absolute value of difference in height between the upper surface of flatness layer and the upper surface of pixel electrode is less than the height of pixel electrode Degree, including following three kinds of enforceable modes：
The first enforceable mode：As shown in Figure 2, the upper surface of flatness layer 200 and the upper surface of pixel electrode 300 It is equal.I.e. passivation layer does not have difference in height in the intersecting position of pixel electrode and flatness layer, is optimal embodiment.So, Passivation layer does not have segment difference in the intersecting position of pixel electrode and flatness layer, is a plane, at utmost reduce passivation layer because The probability that curling comes off occurs for the position that pixel electrode and flatness layer intersect, and then improves the yield of array base palte.
Second of enforceable mode：The depth in the hole farthest apart from first substrate is less than the thickness of pixel electrode in stepped hole Degree, i.e. the upper surface of pixel electrode protrudes from the upper surface of flatness layer and the height of protrusion is less than the thickness of pixel electrode.
Second of enforceable mode：The depth in the stepped hole hole farthest apart from first substrate is more than the thickness of pixel electrode And less than twice of thickness of pixel electrode, i.e. the upper surface of pixel electrode it is recessed in the upper surface of flatness layer and recessed depth it is small In the thickness of pixel electrode.
These three enforceable modes, can realize reduces passivation layer because in the intersecting position hair of pixel electrode and flatness layer The probability that raw curling comes off, and then the yield of array base palte is improved, the bad of stain be present using the liquid crystal panel of the substrate Probability also just decrease.
The shape and size of pixel electrode be it is related to array base palte and the matched color membrane substrates that use, therefore, The shape and size of pixel electrode are determined according to array base palte and the matched color membrane substrates used, distance in stepped hole The shape and size in the farthest hole 212 of first substrate are that needs are consistent with the shape and size of the pixel electrode of array base palte.
So, hole 212 farthest apart from first substrate in stepped hole is consistent with pixel electrode so that stepped hole can be with battle array The other structures of row substrate are adapted, and reduce the change of the structure of array substrate.
The array base palte of the present invention is to be all disposed within for pixel electrode and public electrode on array base palte and between the two Insulation, pixel electrode are located at lower section picture in first substrate side, the side of public electrode remote first substrate above The improvement of plain electrode forming position, the type for the array base palte being not limited in diagram.The array base palte of the present invention can be bottom gate The array base palte of type, can be the array base palte of top gate type, it is also possible to be polysilicon array substrate, can also be non-polycrystalline Silicon array substrate.
First substrate in array base palte of the present invention, structure that first substrate include different according to the type of array base palte May also difference, array base palte as shown in Figures 2 and 3, first substrate 600 includes glass substrate 610, cushion 620, Active layer 630, gate insulator 641, grid 642, source electrode 651, interlayer insulating film 652 etc. structure, wherein, interlayer insulating film 652 provide insulation for source electrode and drain electrode；If array base palte is the array base palte of polysilicon, active layer uses polycrystalline silicon material shape Into active layer, and form between glass substrate and cushion the light blocking layer for blocking polysilicon active layer.
Embodiment two
As shown in figure 4, the array base palte of embodiments of the invention two comprises the following steps：
First substrate is formed, first substrate has the drain electrode exposed from its side；
Form the flatness layer that covering first substrate exposes drain electrode side；
Open up stepped hole in position of the flatness layer on drain electrode, and the aperture of stepped hole from flatness layer away from described the The direction of one laterally closer first substrate of one substrate diminishes；
Pixel electrode is formed, pixel electrode is formed at stepped hole and connected with drain electrode；
Form the passivation layer of covering flatness layer and pixel electrode；
Public electrode is formed on passivation layer.
In the manufacture method of array base palte of the prior art there is the position in flatness layer on drain electrode to open up The step of hole.The manufacture method of the array base palte of embodiments of the invention two, do not increase extra manufacturing process, simply will be existing There is the step of position in technology in flatness layer on drain electrode opens up via, be substituted in flatness layer on drain electrode Position open up stepped hole, and the aperture of stepped hole is from the direction of the laterally closer first substrate of one of flatness layer away from first substrate The step of diminishing, and segment difference of the array base palte passivation layer produced in the intersecting position of pixel electrode and flatness layer is controllable , by controlling segment difference of the passivation layer in the intersecting position of pixel electrode and flatness layer to be less than the thickness of pixel electrode, Ke Yishi The probability that passivation layer comes off because curling occurs in the intersecting position of pixel electrode and flatness layer is now reduced, and then improves array base The yield of plate, the bad probability that stain using the liquid crystal panel of the substrate be present also just are decreased.
Specifically comprise the following steps the step of position of the flatness layer on drain electrode opens up stepped hole：
Stepped hole, such as Fig. 5 are opened up by position of the exposure and etching of a mask plate in flatness layer on drain electrode Shown, mask plate includes the part penetrating region 720 that full impregnated crosses through hole 710 and crosses around through hole and be attached thereto positioned at full impregnated；
Wherein, full impregnated crosses through hole and is used to form hole 211 nearest apart from first substrate in stepped hole, and part penetrating region is used In forming the hole beyond hole nearest apart from first substrate in stepped hole.
So, through hole and the mask plate of part penetrating region are crossed by using with full impregnated, it is only necessary to a mask plate, warp Cross single exposure and etching, you can obtain stepped hole.
The depth in the hole farthest apart from first substrate is and mask in the stepped hole that the part penetrating region of mask plate is formed The transmitance correlation of the part penetrating region of version, by controlling the transmitance of part penetrating region of mask plate to reach part thoroughly Cross the depth in hole farthest apart from first substrate in the stepped hole of region formation and the thickness difference of the pixel electrode of array base palte Absolute value be less than pixel electrode thickness value.
The depth in hole and the pixel of array base palte farthest apart from first substrate in the stepped hole that part penetrating region is formed The thickness value that the absolute value of the thickness difference of electrode is less than pixel electrode includes three kinds of enforceable modes：
The first enforceable mode is：The hole farthest apart from first substrate in the stepped hole that part penetrating region is formed Depth is equal to the thickness of the pixel electrode needed for array base palte；
Second of enforceable mode be：The hole farthest apart from first substrate in the stepped hole that part penetrating region is formed Depth is less than the thickness of the pixel electrode needed for array base palte；
The third enforceable mode is：The hole farthest apart from first substrate in the stepped hole that part penetrating region is formed Depth is more than twice of the thickness of the pixel electrode needed for array base palte and the thickness less than pixel electrode.
The array base palte that these three enforceable modes produce, can realize reduces passivation layer because in pixel electrode peace The probability that curling comes off occurs for the intersecting position of smooth layer, and then improves the yield of array base palte, uses the liquid crystal surface of the substrate The bad probability that plate has stain also just decreases.
The shape and size of pixel electrode be it is related to array base palte and the matched color membrane substrates that use, therefore, The shape and size of pixel electrode are determined according to array base palte and the matched color membrane substrates used, distance in stepped hole The shape and size in the farthest hole of first substrate are that needs are consistent with the shape and size of the pixel electrode of array base palte.In order to Reach this effect, it is necessary to which part penetrating region and full penetrating region are as an entirety in the manufacture method of array base palte Shape be engaged with size with the shape and size of the pixel electrode of array base palte so that in stepped hole apart from first substrate most The shape in remote hole is consistent with the shape and size of the pixel electrode of array base palte with size.
The type of array base palte is different, and required manufacture method is also different, and other steps required for array base palte are adopted Completed with corresponding step.
Obviously, those skilled in the art can carry out various changes and modification without departing from this hair to the embodiment of the present invention Bright spirit and scope.So, if these modifications and variations of the present invention belong to the claims in the present invention and its equivalent technologies Within the scope of, then the present invention is also intended to comprising including these changes and modification.

Claims (10)

  1. A kind of 1. array base palte, it is characterised in that including：
    First substrate, the first substrate have the drain electrode exposed from its side；
    The flatness layer for exposing drain electrode side in the first substrate is formed, the flatness layer is provided with the platform on the drain electrode Rank hole, and the aperture of the stepped hole is from the laterally closer first substrate of one of the flatness layer away from the first substrate Direction diminishes；
    Pixel electrode, the pixel electrode are formed at the stepped hole and connected with the drain electrode；
    Cover the passivation layer of the flatness layer and the pixel electrode；
    The public electrode formed on the passivation layer.
  2. 2. array base palte according to claim 1, it is characterised in that the upper surface of the flatness layer and the pixel electrode Upper surface between difference in height absolute value be less than the pixel electrode height；
    Wherein, the upper surface of the flatness layer refers to beyond the flatness layer stepped hole partially away from the side of the first substrate Surface, it is farthest that the upper surface of the pixel electrode is that the pixel electrode is located at first substrate described in distance in the stepped hole Step upper part the remote first substrate side surface.
  3. 3. array base palte according to claim 2, it is characterised in that the upper surface of the pixel electrode and the flatness layer Upper surface it is equal；
    Or the upper surface of the pixel electrode protrudes from the upper surface of flatness layer and the height of protrusion is less than the thickness of pixel electrode Degree；
    Or the upper surface of the pixel electrode recessed is less than pixel electrode in the upper surface of the flatness layer and recessed depth Thickness.
  4. 4. array base palte according to claim 1, it is characterised in that first substrate described in distance is farthest in the stepped hole Hole aperture shape and size it is consistent with the shape and size of the pixel electrode of the array base palte.
  5. 5. array base palte according to claim 1, it is characterised in that the array base palte is bottom gate type array base palte or top Grid-type array base palte.
  6. 6. a kind of manufacture method of array base palte, it is characterised in that comprise the following steps：
    First substrate is formed, the first substrate has the drain electrode exposed from its side；
    Formed and cover the flatness layer that the first substrate exposes the drain electrode side；
    Open up stepped hole in the position that the flatness layer is located on the drain electrode, and the aperture of the stepped hole is from described flat The direction of the laterally closer first substrate of the layer away from the first substrate diminishes；
    Pixel electrode is formed, the pixel electrode is formed at the stepped hole and connected with the drain electrode；
    Form the passivation layer for covering the flatness layer and the pixel electrode；
    Public electrode is formed on the passivation layer.
  7. 7. the manufacture method of array base palte according to claim 6, it is characterised in that be located at the leakage in the flatness layer The step of position on pole opens up stepped hole specifically comprises the following steps：
    The step is opened up in the position that the flatness layer is located on the drain electrode by the exposure and etching of mask plate Hole, the mask plate include the part penetrating region that full impregnated crosses through hole and crosses around through hole and be attached thereto positioned at the full impregnated；
    Wherein, the full impregnated crosses through hole and is used to form the hole that first substrate described in distance is nearest in the stepped hole, the part Penetrating region is used for the hole formed beyond the hole that first substrate described in distance is nearest in the stepped hole.
  8. 8. the manufacture method of array base palte according to claim 7, it is characterised in that what the part penetrating region was formed The depth in the farthest hole of first substrate described in distance and the thickness difference of the pixel electrode of the array base palte in the stepped hole Absolute value be less than pixel electrode thickness value.
  9. 9. the manufacture method of array base palte according to claim 8, it is characterised in that what the part penetrating region was formed The depth in the farthest hole of first substrate described in distance is equal to the thickness of the pixel electrode needed for the array base palte in the stepped hole Degree；
    Or the depth in the farthest hole of first substrate described in distance is less than in the stepped hole of the part penetrating region formation The thickness of pixel electrode needed for the array base palte；
    Or the depth in the farthest hole of first substrate described in distance is more than in the stepped hole of the part penetrating region formation The thickness of pixel electrode needed for the array base palte and less than twice of thickness of pixel electrode.
  10. 10. the manufacture method of array base palte according to claim 7, it is characterised in that the part penetrating region and complete Penetrating region is engaged as the shape of an entirety with size with the shape and size of the pixel electrode of the array base palte, is made Obtain the shape in the hole that first substrate described in distance is farthest and size and the pixel electrode of the array base palte in the stepped hole Shape and size are consistent.
CN201710718137.4A 2017-08-21 2017-08-21 A kind of array base palte and its manufacture method Pending CN107482020A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109148481A (en) * 2018-08-21 2019-01-04 武汉华星光电半导体显示技术有限公司 A kind of flexible array substrate and preparation method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101114668A (en) * 2006-03-27 2008-01-30 三星Sdi株式会社 Organic light emitting display device and method of fabricating the same
CN102540539A (en) * 2012-02-22 2012-07-04 信利半导体有限公司 Wide-visual-angle liquid crystal display
CN102929022A (en) * 2012-10-23 2013-02-13 友达光电股份有限公司 Liquid crystal display device and manufacture method thereof
CN104183648A (en) * 2014-07-25 2014-12-03 京东方科技集团股份有限公司 Film transistor and preparation method thereof, array substrate and display device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7061114B2 (en) * 2004-03-25 2006-06-13 Texas Instruments Incorporated Structure and method for contact pads having a protected bondable metal plug over copper-metallized integrated circuits
CN103167721A (en) * 2011-12-09 2013-06-19 鸿富锦精密工业（深圳）有限公司 Printed circuit board
US10321836B2 (en) * 2015-11-30 2019-06-18 Physio-Control, Inc. Context scores to enhance accuracy of ECG readings
CN105789219B (en) * 2016-03-22 2018-07-27 京东方科技集团股份有限公司 A kind of method, display panel and display device for manufacturing display panel
CN106020545B (en) * 2016-05-20 2019-01-15 京东方科技集团股份有限公司 Array substrate and preparation method thereof, touch screen
CN106252217B (en) * 2016-08-25 2019-05-24 京东方科技集团股份有限公司 Thin film transistor (TFT) and preparation method thereof, array substrate and display device
KR102631905B1 (en) * 2017-01-05 2024-02-01 삼성디스플레이 주식회사 Display apparatus
CN106647014A (en) * 2017-03-23 2017-05-10 京东方科技集团股份有限公司 Color film substrate, preparation method thereof and display panel
CN108873509A (en) * 2017-05-08 2018-11-23 中华映管股份有限公司 The method for forming dot structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101114668A (en) * 2006-03-27 2008-01-30 三星Sdi株式会社 Organic light emitting display device and method of fabricating the same
CN102540539A (en) * 2012-02-22 2012-07-04 信利半导体有限公司 Wide-visual-angle liquid crystal display
CN102929022A (en) * 2012-10-23 2013-02-13 友达光电股份有限公司 Liquid crystal display device and manufacture method thereof
CN104183648A (en) * 2014-07-25 2014-12-03 京东方科技集团股份有限公司 Film transistor and preparation method thereof, array substrate and display device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109148481A (en) * 2018-08-21 2019-01-04 武汉华星光电半导体显示技术有限公司 A kind of flexible array substrate and preparation method thereof
CN109148481B (en) * 2018-08-21 2020-09-01 武汉华星光电半导体显示技术有限公司 Flexible array substrate and manufacturing method thereof

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