CN1074773A

CN1074773A - Digital type scanning check monitor

Info

Publication number: CN1074773A
Application number: CN 92107284
Authority: CN
Inventors: 吴金泉
Original assignee: Individual
Current assignee: Individual
Priority date: 1992-01-24
Filing date: 1992-01-24
Publication date: 1993-07-28

Abstract

The present invention relates to a kind of touring monitor, be used for supervising electric power, chemical industry operator on duty's tours of inspection quality.The present invention can open counter periodically in official hour, press count button for the operator on duty; Surpass official hour, the counter locking does not receive external button signal, can prevent cheating effectively.The present invention can be used as the foundation of checking operator on duty's quality on duty, so that safety in production.

Description

Digital type scanning check monitor

The present invention relates to a kind of counter that is used to write down the tours of inspection number of times.

In electric power, chemical process, often need the ruuning situation of operations staff's quantitative check plant equipment, the various data of time recording equipment.Also there is not at present special-purpose device can write down operations staff's quality on duty effectively.

The object of the present invention is to provide a kind of digital type scanning check monitor, can regularly open a period of time periodically and trigger for the operations staff, thus can write down the operations staff in official hour whether at the scene, can also prevent cheating simultaneously effectively.

Purpose of the present invention can realize by following technical proposal:

The present invention includes the reference generator that is used to produce the benchmark oscillator signal; Be used for the oscillator signal of described reference generator output is carried out different fractions frequency divider frequently; Be used for the square-wave signal of frequency divider output is taken a sample and the period 1 signal sampling circuit of cycle output useful signal; Be used to accept first pulse signal of hand push button input, all signals that elimination is imported subsequently, the self-lock switch of a useful signal of output, the output signal of described period 1 signal sampling circuit is connected to the gating control end of self-lock switch; Be used for counter that the useful signal of self-lock switch output is counted; Be used for decoder driver that the digital signal of counter output is deciphered, driven; Be used to show the display of the demonstration sign indicating number of decoder driver output.Described reference generator can produce the square wave of fixed cycle, carry out frequency division not at the same level as required by frequency divider, the period 1 signal sampling circuit is from the frequency divider square-wave signal of taking a sample, export one tunnel periodic signal of square wave, the cycle that the cycle of square-wave signal should regularly patrol and examine for the operations staff, the effective value time of each cycle square wave (time of high level or low level time) can be triggered the present invention to record the permission time of play number for the operations staff, in this time, counter is opened, can count pulse from hand push button, self-lock switch only can guarantee in the above-mentioned permission time by once from the pulse of hand push button, block all pulses subsequently, make counter once add " 1 " counting at the most in the time that allows, the data in the counter send display to show behind decoder driver.The present invention can also comprise and be used for the square-wave signal of frequency divider output is taken a sample and signal sampling circuit second round of cycle output useful signal, and described second round, the output signal of signal sampling circuit was connected to the reseting controling end of counter.Described second round, signal sampling circuit was in order to reset to counter cycle, made counter O reset in for example per 24 hours or per 8 hours, also can be without signal sampling circuit second round, and self-zeroing when the counter data full scale.The present invention can also comprise and be used for the square-wave signal of frequency divider output is taken a sample and the period 3 signal sampling circuit of cycle output useful signal; The input signal of described period 3 signal sampling circuit is by gauge tap K ₁Control, its output signal is connected to the gating control end of self-lock switch.Described period 3 signal sampling circuit is opened at the time inside counting device of quick gating in order to the quick gating of counter, can write down the pulse from hand push button, with the shown data of levelling counter.The present invention can also comprise the reset button that can export the effective impulse signal, and the effective impulse signal of being exported is connected on the reseting controling end of frequency divider.This reset button is in order to determine counting zero-time of the present invention.K ₁All be sealed in inside of the present invention with reset button, to prevent cheating.

The present invention has the following advantages:

Since adopted self-lock switch, can only be by first pulse, so can prevent cheating effectively from hand push button.

The period 3 signal sampling circuit can be when needed by pressing K switch ₁Gated counter is adjusted the usefulness that shows number for managerial personnel fast.Reset button can arbitrarily be set the zero-time of counter for managerial personnel in addition.K ₁All be sealed in inside of the present invention with reset button, can prevent cheating.

The invention will be further described below in conjunction with drawings and Examples:

Accompanying drawing 1 is a circuit block diagram of the present invention;

Accompanying drawing 2 is the circuit theory diagrams of one embodiment of the present of invention;

With reference to accompanying drawing, IC in the accompanying drawing 2 ₁Model be ZC ₇₀₂, be a second reference generator; IC ₂Model be CC ₄₅₁₈B is two decade counters; IC ₃Model be CC ₄₅₁₈B is two decade counters; IC ₂, IC ₃Use as frequency divider at this.IC ₄Model be CC ₄₀₁₃, be double D trigger; IC ₅Model be CC ₄₅₁₈B is two decade counters; IC ₆And IC ₇Model be CC ₄₅₄₃, be the liquid crystal decoder driver; IC ₈And IC ₉It is LCD.The square wave of the 12nd pin output 256HZ of second reference generator, this signal is through double D trigger IC ₄In first trigger frequency division after by IC ₄The 1st pin obtain the 128HZ square-wave signal, this signal is as the AC driving signal of LCD.IC ₁The 5th pin output 1HZ square-wave signal, this signal is input to IC as of the present invention second reference signal ₂The 10th pin, IC ₂The 11st pin output cycle be 2 seconds square-wave signal, this signal through rejection gate 30 and or door 32 deliver to IC respectively ₆And IC ₇The 7th pin, as the gating flashing signal of display (be display with 2 seconds cycle flicker).IC ₂The 14th pin output cycle be 10 seconds, 8 seconds effective square-wave signals in the phase weekly, this signal send IC ₂Counting input end the 2nd pin of second counter, with the 22 output cycles of door be 60 seconds square-wave signal, through or door 23 send IC ₂The reset terminal of second counter, so IC ₂The every mistake of second counter 60 seconds clearly once zero, IC ₂The 5th pin output cycle be the square-wave signal of 1 minute (60 seconds), this signal is input to IC ₃The 10th pin, IC ₃The 14th pin output cycle be 10 minutes, 8 fens effective square-wave signals in the phase weekly.And IC ₂Principle identical, IC ₃The 4th pin and the 5th pin connect and door 25 input end, so with the 25 output cycles of door be one hour square-wave signal, this square-wave signal through or 24 deliver to IC ₃The reset terminal of second counter, IC ₃Per 1 hour of second counter clearly once zero.By or door 27, rejection gate 28, rejection gate 29 are formed the period 1 signal sampling circuit, are the cycle by rejection gate 29 outputs with 1 hour, interior 0～10 fen effective square-wave signal is as electronics self-lock switch IC the phase weekly ₄The gating control signal.The input signal of rejection gate 28 has five the tunnel, and wherein when arbitrary road was high level, rejection gate 28 was output as low level, and it is oppositely with door 21 output signals that the signal of rejection gate 29 outputs equals.Under the normal condition, quick gating button K ₁And reset button K ₂All lead to 0, therefore close with door 21, it is output as 0.IC ₂8 seconds useful signals of the 14th pin output can not be by arriving rejection gates 29 with door 21.For or the door 27, IC is depended in its output ₃The 3rd pin, therefore in normal operation, have only the IC of working as ₃In the 3rd, 4,5 pins be at 0 o'clock, rejection gate 29 just equals level "0", this level gating is as the IC of self-lock switch ₄, this state is since 0 minute, up to first 10 sub-signal from IC ₃The 2nd pin imported and broken, so self-lock switch stays open 10 minutes, and in after this 50 minutes, IC ₃The 3rd, 4,5 pins always have one to be not equal to level "0", so the self-lock switch locking kept 50 minutes.After 60 minutes because of IC ₃Automatically return-to-zero, cycle count again so self-lock switch is opened again, and kept 10 minutes, and so forth endlessly.By reverser 20, with door 21, rejection gate 29 forms the period 3 signal sampling circuit, by IC ₂The effective square-wave signal of 10 second cycle, 8 seconds of the 14th pin output through reverser 20 to arrive rejection gate 29 again with door 21, be the cycle by rejection gate 29 outputs with 10 seconds, interior 8 seconds effective square-wave signals of phase weekly, quick gating switch K ₁As the gauge tap of this signal, this signal is as self-lock switch IC ₄Quick gating signal.Under quick strobe state, self-lock switch was opened once in per 10 seconds, continued to open 8 seconds at every turn, and strobe state can be set the interior data of counter for the commissioning staff fast.IC ₄Be double D trigger, one of them trigger is as frequency division usefulness, with IC ₁The 256HZ square-wave signal frequency division of the 12nd pin input becomes 128HZ.Another trigger is as self-lock switch, and when by gating, self-lock switch is used to select hand push button K ₃All pulses except that first pulse of first pulse signal that sends, elimination, and from IC ₄The 13rd pin output count pulse, for counter IC ₅Counting is used; When the self-lock switch locking, self-lock switch does not receive any extraneous signal.IC ₅Be 24 system counters, to IC ₅The step-by-step counting of the 1st pin input, 3rd, the binary code of 4,5,6 a pins output position, 11st, 12,13,14 pins are exported ten binary code, this counter is self-zeroing behind meter full 24, thus do not need signal sampling circuit second round, for the count cycle of different needs, can design signal sampling circuit second round, regularly counter is carried out zero clearing, also can set the range of counter, behind the counting full scale, it is resetted.Counter IC ₅Data by IC ₆And IC ₇Decoding drives, by IC ₈And IC ₉Display it.K ₁Be quick gating button, R ₁Resistance be 10K.K ₂Be reset button, R ₄Resistance be 10K, reset signal is divided into five the tunnel, wherein four tunnel IC that send as frequency divider ₂, IC ₃Reset terminal, another road is sent or door 27, makes or door 27 moments output equals high level, causes or non-28 is output as low level owing to also equal low level with door 21 outputs, thereby rejection gate 29 outputs equal high level, i.e. IC ₄The 10th pin moment equal 1, make IC ₄Reset IC ₄The 13rd pin recover 0.Rejection gate 30 is because IC ₄The the 13rd, the 10th pin be 0, so IC ₂The 11st pin output 2 seconds being that the square-wave signal in cycle can pass through rejection gate 30, the demonstration control end (IC of arrival code translator ₇And IC ₆The 7th pin) make display after zero clearing reliably the flash of light, represent gating.K ₃Be hand push button, R ₂Resistance be 10K, R ₃Resistance be 500 ohm, the signal inversion of 26 pairs of hand push buttons of not gate is so that IC ₄Receive.Be used to make IC with door 23 ₅Self-zeroing after counting reaches 24.Can identify IC with rejection gate 31 ₅0 numeral of tens, at 0～24(decimal system) scope in, have only when two input ends of rejection gate 31 are equal to 0, the output of rejection gate 31 just equals 1, otherwise exports 0,31 output may command IC of rejection gate ₇The demonstration control end, work as IC ₅Tens equal at 0 o'clock, the tens of display does not show.

Claims

1, a kind of digital type scanning check monitor is characterized in that: it comprises the reference generator that is used to produce the benchmark oscillator signal; Be used for the oscillator signal of described reference generator output is carried out different fractions frequency divider frequently; Be used for the square-wave signal of frequency divider output is taken a sample and the period 1 signal sampling circuit of cycle output useful signal; Be used to accept first pulse signal of hand push button input, all signals that elimination is imported subsequently, the self-lock switch of a useful signal of output, the output signal of described period 1 signal sampling circuit is connected to the gating control end of self-lock switch; Be used for counter that the useful signal of self-lock switch output is counted; Be used for decoder driver that the digital signal of counter output is deciphered, driven; Be used to show the display of the demonstration sign indicating number of decoder driver output.

2, digital type scanning check monitor according to claim 1, it is characterized in that: it can also comprise and be used for the square-wave signal of frequency divider output is taken a sample and signal sampling circuit second round of cycle output useful signal, and described second round, the output signal of signal sampling circuit was connected to the reseting controling end of counter.

3, digital type scanning check monitor according to claim 1 is characterized in that: it can also comprise and be used for the square-wave signal of frequency divider output is taken a sample and the period 3 signal sampling circuit of cycle output useful signal; The input signal of described period 3 signal sampling circuit is by gauge tap K ₁Control, its output signal is connected to the gating control end of self-lock switch.

4, digital type scanning check monitor according to claim 1 is characterized in that: it can also comprise the reset button that can export the effective impulse signal, and the effective impulse signal of being exported is connected on the reseting controling end of frequency divider.