CN107465892A - Digital signal processing image identifying system and recognition methods - Google Patents
Digital signal processing image identifying system and recognition methods Download PDFInfo
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- CN107465892A CN107465892A CN201710571331.4A CN201710571331A CN107465892A CN 107465892 A CN107465892 A CN 107465892A CN 201710571331 A CN201710571331 A CN 201710571331A CN 107465892 A CN107465892 A CN 107465892A
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- digital signal
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- identifying system
- signal processing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/18—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/40—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/91—Television signal processing therefor
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Image Processing (AREA)
Abstract
The present invention provides a kind of digital signal processing image identifying system.The digital signal processing image identifying system includes video capture device, video decoding chip, the first programming device, the second programming device, storage device, digital signal processor, universal port.The digital signal processing image identifying system provided by the invention solves the video surveillance program construction cycle length of prior art, the technical problem that cost is high, alterability is poor.
Description
Technical field
The present invention relates to single-chip microcomputer field, and in particular to a kind of digital signal processing image identifying system.
Background technology
Image is identified in the environment of variation processing requirement has good real-time, data can be carried out timely
Processing.Exported after CCD camera, video decoding chip, FPGA/CPLD analysis are usually used in existing video surveillance program
The pattern of low and high level is realized.Wherein video decoding chip is used for being AD converted the analog signal of CCD camera collection,
FPGA/CPLD finally carries out processing to data and is controlled in output to data acquisition.This solution development cycle is long, cost is high, can
Alterability is poor.
The content of the invention
To solve the technical problem that the video surveillance program construction cycle of prior art is long, cost is high, alterability is poor, this
Invention provides a kind of digital signal processing image identifying system to solve the above problems.
A kind of digital signal processing image identifying system, including it is video capture device, video decoding chip, first programmable
Device, the second programming device, the first storage device, digital signal processor, the second storage device, universal port；
The video capture device gathers and exports analog signal；
The analog signal is inputted to the video decoding chip, and 8 YCrCb 4 are exported after decoding:2:The video of 2 forms
Data；
The video data inputs to first programming device, first programming device and is provided with format converting module,
The video data of rgb format is exported after conversion, is designated as two level video data；
The two level video data inputs to second programming device, second programming device and is provided with image interception mould
Block, intercept partial pixel in the two level video data and exported, be designated as pixel data；
First storage device is data cached under second programming device control；
The universal port includes input module and output module, and the pixel data is inputted to described via the input module
Digital signal processor, the digital signal processor are provided with image processing module, count each gray scale in the pixel data
The quantity of the pixel of value, the pixel proportion of each gray value, count after terminating by the output module output level；
Second storage device is data cached under the DSP CONTROL.
In a kind of preferred embodiment of digital signal processing image identifying system provided by the invention, the video decoding
Chip is provided with clock module, while exporting the video data, in addition to line synchronising signal, field sync signal, parity field mark
The clock signals such as will signal.
In a kind of preferred embodiment of digital signal processing image identifying system provided by the invention, described image interception
Module coordinates the clock signal, intercepts partial pixel in the two level video data.
In a kind of preferred embodiment of digital signal processing image identifying system provided by the invention, described first can compile
Journey device and second programming device are additionally provided with communication module, and the communication module is received to first Programmable
The control command of part and second programming device.
In a kind of preferred embodiment of digital signal processing image identifying system provided by the invention, the communication module
The pixel data is also transferred, generates simultaneously output image.
In a kind of preferred embodiment of digital signal processing image identifying system provided by the invention, first storage
Equipment includes two random access memory and read-only storage, data cached under second programming device control；
Second storage device includes random access memory and read-only storage, is cached under the DSP CONTROL
Data.
Compared to prior art, the digital signal processing image identifying system provided by the invention utilizes FPGA interceptions portion
Partial image completes intensity histogram map analysis in DSP, effectively reduces the operand in data handling procedure, makes whole processing system
The structure of system tends to be simplified, reduces development cost.Thus response speed has also been speeded, has ensured the real-time of processing procedure.
Brief description of the drawings
Fig. 1 is the structural representation of digital signal processing image identifying system provided by the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only the part of the embodiment of the present invention, rather than whole embodiments.
Referring to Fig. 1, it is the structural representation of digital signal processing image identifying system 1 provided by the invention.
The digital signal processing image identifying system 1 includes camera 11, video decoding chip 12, the first FPGA device
13rd, the SRAM memory 15, two of the second FPGA device 14, three FLASH memory 51, DSP Processor 16, GPIO port 17.
The video decoding chip 12 is additionally provided with clock module 21；First FPGA device 13 is provided with format converting module
31st, the first UART modules 32；Second FPGA device 14 is provided with image interception module 41, the 2nd UART modules 42；The DSP
Processor 16 is provided with image processing module 61；The GPIO port 17 is provided with input module 71 and output module 72.
When it is implemented, the video capture device 11 gathers and exports analog signal.
The analog signal is inputted to the video decoding chip 12, and 8 YcrCb 4 are exported after decoding:2:2 forms
Video data.
The video data inputs to first FPGA device 13, first FPGA device 13 and is provided with form modulus of conversion
Block 31, the video data of rgb format is exported after conversion, is designated as two level video data.
The serial ports at PC ends sends the control command of related brightness, contrast etc., respectively via the first UART modules
32nd, the 2nd UART modules 42, first FPGA device 13, second FPGA device 14 are controlled.
Wherein, the 2nd UART modules 42 also call the function of structural map picture to the pixel data with different parameters,
And image caused by exporting.
The two level video data is inputted to second FPGA device 14, second FPGA device 14 and cut provided with image
Modulus block 41, intercept it is being shown in the two level video data, effective 640 be multiplied by 480 pixels and exported, be designated as picture
Prime number evidence.
Two SRAM memories 15 and a FLASH memory 51 control in second FPGA device 14
Under it is data cached.
The pixel data is inputted to the DSP Processor 16 via the input module 71.The DSP Processor 16 is set
There is image processing module 61, count the quantity of the pixel of each gray value in the pixel data, the pixel institute of each gray value
Accounting example.
Under normal circumstances, image is all made up of Continuous Gray Scale, is being that gray scale occurs using abscissa as grey level, ordinate
Frequency, form one " peak " in the grey level histogram formed.The DSP Processor 16 is by judging in the histogram
Whether " peak " produces displacement, you can judges whether picture produces change, thus exports varying level, and pass through the output module
72 outputs carry out the driving of next stage.
The control of one SRAM memory 15 and a FLASH memory 51 in the DSP Processor 16
Under it is data cached.
Compared to prior art, the digital signal processing image identifying system 1 provided by the invention is intercepted using FPGA
Parts of images completes intensity histogram map analysis in DSP, effectively reduces the operand in data handling procedure, makes entirely to handle
The structure of system tends to be simplified, reduces development cost.Thus response speed has also been speeded, has ensured the real-time of processing procedure.
Embodiments of the invention are the foregoing is only, are not intended to limit the scope of the invention, it is every to utilize this hair
The equivalent structure or equivalent flow conversion that bright description is made, or directly or indirectly it is used in other related technology necks
Domain, similarly it is included within the scope of patent protection of the present invention.
Claims (6)
- A kind of 1. digital signal processing image identifying system, it is characterised in that：Including video capture device, video decoding chip, First programming device, the second programming device, the first storage device, digital signal processor, the second storage device, general end Mouthful；The video capture device gathers and exports analog signal；The analog signal is inputted to the video decoding chip, and 8 YCrCb 4 are exported after decoding:2:The video of 2 forms Data；The video data inputs to first programming device, first programming device and is provided with format converting module, The video data of rgb format is exported after conversion, is designated as two level video data；The two level video data inputs to second programming device, second programming device and is provided with image interception mould Block, intercept partial pixel in the two level video data and exported, be designated as pixel data；First storage device is data cached under second programming device control；The universal port includes input module and output module, and the pixel data is inputted to described via the input module Digital signal processor, the digital signal processor are provided with image processing module, count each gray scale in the pixel data The quantity of the pixel of value, the pixel proportion of each gray value, count after terminating by the output module output level；Second storage device is data cached under the DSP CONTROL.
- 2. digital signal processing image identifying system according to claim 1, it is characterised in that：The video decoding chip Provided with clock module, while exporting the video data, in addition to line synchronising signal, field sync signal, odd even field mark are believed Number wait clock signal.
- 3. digital signal processing image identifying system according to claim 2, it is characterised in that：Described image interception module Coordinate the clock signal, intercept partial pixel in the two level video data.
- 4. digital signal processing image identifying system according to claim 1, it is characterised in that：First Programmable Part and second programming device are additionally provided with communication module, the communication module receive to first programming device and The control command of second programming device.
- 5. digital signal processing image identifying system according to claim 4, it is characterised in that：The communication module is also adjusted The pixel data is taken, generates simultaneously output image.
- 6. digital signal processing image identifying system according to claim 1, it is characterised in that：First storage device It is data cached under second programming device control including two random access memory and read-only storage；Second storage device includes random access memory and read-only storage, is cached under the DSP CONTROL Data.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109036263A (en) * | 2018-09-13 | 2018-12-18 | 天长市辉盛电子有限公司 | LED display image processing apparatus and its processing method |
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Application publication date: 20171212 |