CN107465500A - MD5 Brute Force system and methods based on FPGA - Google Patents
MD5 Brute Force system and methods based on FPGA Download PDFInfo
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Abstract
The invention discloses a kind of MD5 Brute Force system and methods based on FPGA, the system includes the input interface unit being linked in sequence, N cores MD5 Brute Forces arithmetic element and output interface unit, wherein, N cores MD5 Brute Forces arithmetic element is made up of the N number of monokaryon MD5 Brute Force arithmetic elements being connected in parallel, using multi-core parallel concurrent treatment mechanism, each monokaryon while parallel generation key, MD5 computings and then progress Hash values match respectively obtain matching result, monokaryon MD5 Brute Forces arithmetic element includes key policy generation module, MD5 algorithm computing modules, Hash values match module.The maximum limitation for reducing the computing of MD5 algorithms and clock frequency being run to FPGA of the invention, improve the clock frequency that FPGA realizes MD5 Brute Force algorithm computings, and using the design philosophy of multi-core parallel concurrent treatment mechanism, the speed of MD5 Brute Forces is significantly improved, solves the problems, such as that MD5 Brute Force efficiency is low.
Description
Technical field
The present invention relates to field of information security technology, and in particular to a kind of MD5 Brute Forces system and side based on FPGA
Method.
Background technology
The brief narration of MD5 algorithms：MD5 is grouped with 512 to handle the information of input, and each packet is divided into again
16 32 seats packets, after have passed through a series of processing, the output of algorithm is formed by four 32, by this four 32
128 hashed values will be generated after packet concatenation, the hashed value has uniqueness.
MD5 major cycles 4 are taken turns, and often wheel circulation is all much like.Often wheel carries out 16 arithmetic operations, i.e. 16 step computings；The first round
It is 16 FF (a, b, c, d, Mj, s, ti) arithmetic operations, the second wheel is 16 GG (a, b, c, d, Mj, s, ti) arithmetic operations, the
Three-wheel is 16 HH (a, b, c, d, Mj, s, ti) arithmetic operations, and fourth round is 16 II (a, b, c, d, Mj, s, ti) computings behaviour
Make, finally export the hashed value of 128 of 4 32bit a, b, c, d composition.
Because MD5 is irreversible, different numerals, upper and lower case letter, character combination can only be used, exhaustive one by one, i.e. violence is broken
Solution, key are sent into MD5 arithmetic elements and carry out calculation process, operation result cracks into as MD5 cryptographic Hash to be cracked
Work(.
Patent retrieval to prior art finds that the patent No. 201110099441 " is handled up based on the FPGA superelevation realized
Amount md5 Brute Forces device " provides a kind of design method based on FPGA hardware Brute Force MD5 algorithms, the patent defect
It is：MD5 Brute Force its main operationals unit one, each computing one-level stream treatment, i.e. 64 level production lines handle 64 behaviour
Make computing (MD5 major cycles 4 are taken turns, 64 operations), once-through operation single-stage stream treatment limits MD5 Brute Force computings and existed
Operating rate in FPGA, that is, FPGA clock frequency is limited, and the patent is monokaryon MD5 Brute Forces.It is another existing
" Hardware-implemented MD5function " propose the design method based on FPGA to publication, but MD5 cores
The processing of the level production line of center algorithm 64 is realized, limits FPGA clock frequencies, only monokaryon MD5 Brute Forces arithmetic element, does not have
The processing of parallel multi-core MD5 arithmetic elements." the Efficient Implementation of Hash of the patent No. 3/440,264
The scheme of MD5 algorithms is realized in Algorithm on a Processor " propositions based on arm processor, and the patent defect is：
Arm processor speed and efficiency are not so good as FPGA, and are also the processing of monokaryon MD5 Brute Forces arithmetic element.Another existing disclosure
Patent " crack method of file password " proposes that the method for exhaustion based on PC cracks scheme, and PC is serial process mechanism, can only
Monokaryon MD5 Brute Force arithmetic elements are handled, and FPGA is parallel processing, while can be with multinuclear MD5 Brute Force arithmetic elements
Parallel processing, therefore the Patent design defect is that time-consuming, efficiency is low for MD5 Brute Forces.
In summary, the more of the MD5 Brute Force arithmetic elements based on FPGA hardware technology are not directed in the prior art
Core treatment mechanism, also operate multi-stage pipeline design philosophy without reference to using single-step run；How MD5 Brute Force fortune is improved
Calculate speed and efficiency, how multinuclear MD5 Brute Force arithmetic element parallel processing mechanism, be to improve PDR and data
Handling capacity is crucial, where the bottleneck for even more improving MD5 Brute Force speed, and has the problem of to be solved in the prior art.
The content of the invention
The invention aims to solve drawbacks described above of the prior art, there is provided a kind of MD5 violences based on FPGA
Crack system and method.
According to disclosed embodiment, the first aspect of the present invention discloses a kind of MD5 Brute Force systems based on FPGA,
Described MD5 Brute Forces system includes input interface unit, N cores MD5 Brute Forces arithmetic element and the output being linked in sequence
Interface unit, wherein,
Described input interface unit is connected with the controller equiment of outside, FPGA and controller communication is realized, to control
The message that device processed issues carries out parsing distribution, and N core MD5 Brute Force arithmetic elements are managed；
Described N cores MD5 Brute Forces arithmetic element is by N number of monokaryon MD5 Brute Forces arithmetic element group for being connected in parallel
Into using multi-core parallel concurrent treatment mechanism, simultaneously then parallel generation key, MD5 computings carry out Hash values match difference to each monokaryon
Obtain matching result；
Described output interface unit is connected with the controller equiment of outside, manages described N core MD5 Brute Forces fortune
Row unit cracks result, and carries out message analysis and framing to cracking result, cracks and successfully uploads controller, stops task；
Failure is cracked, uploads controller, wait lower subtask cracks startup.
Further, described monokaryon MD5 Brute Forces arithmetic element include be linked in sequence key policy generation module,
MD5 algorithms computing module, Hash values match module, wherein,
Described key policy generation module realizes the combination producing of finite length key according to controller distributing policy；
Described MD5 algorithms computing module includes major cycle 4 and takes turns computing, often takes turns 16 operations, totally 64 operation fortune
Calculate, to each operation, carry out N level production line processing, i.e. MD5 single -step operations computing N level production lines processing is realized；
The data that described Hash values match module obtains described MD5 algorithm computing modules and cryptographic Hash to be cracked
Matched, the match is successful, i.e. the corresponding key of the data is the result cracked, that is, cracks success, otherwise crack failure.
Further, for different policy selections, the cipher key combinations of described key policy generation module generation can be with
It is numeral and spcial character, numeral and upper and lower case letter, upper and lower case letter and spcial character, pure digi-tal, pure alphabetical, pure character
Combination.
According to disclosed embodiment, the second aspect of the present invention discloses a kind of MD5 Brute Force methods based on FPGA,
Described MD5 Brute Force methods comprise the following steps：
Input interface unit is connected with the controller equiment of outside, FPGA and controller communication is realized, under controller
The message of hair carries out parsing and is distributed to N core MD5 Brute Force arithmetic elements；
N cores MD5 Brute Forces arithmetic element is made up of N number of monokaryon MD5 Brute Forces arithmetic element parallel connection, wherein,
Key policy generation module in monokaryon MD5 Brute Force arithmetic elements realizes that finite length is close according to controller distributing policy
The combination producing of key；
MD5 algorithms computing module in monokaryon MD5 Brute Force arithmetic elements carries out major cycle 4 and takes turns computing, often takes turns 16 times
Operation, totally 64 operations, to each operation, carry out N level production line processing, i.e. MD5 single -step operations computing N levels
Pipeline processes are realized；
What the Hash values match module in monokaryon MD5 Brute Force arithmetic elements obtained above-mentioned MD5 algorithms computing module
Data are matched with cryptographic Hash to be cracked, and the match is successful, i.e. the corresponding key of the data is the result cracked, i.e., broken
Solve successfully, otherwise crack failure；
Output interface unit is connected with the controller equiment of outside, manages described N core MD5 Brute Force running units
Crack result, and carry out message analysis and framing to cracking result, crack and successfully upload controller, stop task；Crack mistake
Lose, upload controller, wait lower subtask cracks startup.
The present invention is had the following advantages relative to prior art and effect：
The present invention is based on FPGA high-speed parallel disposal abilities, single-step run multistage flowing water design philosophy, multi-core parallel concurrent computing
Treatment mechanism, improve the nucleus module data-handling capacity of MD5 Brute Force algorithms and the handling capacity of data operation；Relative to
Traditional each operation one-level pipeline processes of MD5 Brute Force arithmetic elements, operation realizes 3 grades to the present invention every time
Flowing water, the i.e. level production line of single -step operation computing 3 design, the MD5 Brute Forces algorithm unit operation clock frequency of raising, so single
It is higher that speed is cracked in the time of position, it is better to crack efficiency；Designed relative to traditional monokaryon MD5 Brute Forces, the present invention is set
Multinuclear MD5 Brute Forces unit parallel processing mechanism simultaneously is counted, speed is cracked and improves N times, it is more powerful to crack aging performance.
Brief description of the drawings
Fig. 1 is the MD5 Brute Force block diagrams of system based on FPGA disclosed in the present invention；
Fig. 2 is monokaryon MD5 algorithm arithmetic element module frame charts；
Fig. 3 is key policy generation module flow chart；
Fig. 4 is MD5 algoritic module flow charts；
Fig. 5 is Hash values match block flow diagram.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
Part of the embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
Embodiment one
MD5 Brute Force design of the present embodiment based on FPGA realizes that, using FPGA hardware technology, single-step run operation is more
Level flowing water design philosophy, multinuclear MD5 Brute Force arithmetic element parallel processing mechanism；It it is exactly the unit interval for Brute Force
Interior raising cracks speed, and raising, which cracks speed, mainly two schemes, first, improving the operation speed of MD5 Brute Force arithmetic elements
Rate, second, multinuclear MD5 Brute Force arithmetic element parallel processings；Based on the two design philosophys, maximum reduces MD5 algorithm computings
Limitation to FPGA operation clock frequencies, that is, improve FPGA and realize the clock frequency of MD5 Brute Force algorithm computings, and use
The design philosophy of multi-core parallel concurrent treatment mechanism, has thus significantly improved the speed of MD5 Brute Forces, solves well existing
The problem of MD5 Brute Forces efficiency is low in technology.
As shown in Figure 1, the MD5 Brute Forces block diagram of system based on FPGA disclosed in the present invention, which provides, is based on
FPGA MD5 Brute Forces design realizes that its core is N core MD5 Brute Force arithmetic element parallel processing mechanism.Monokaryon
MD5 Brute Forces arithmetic element includes three key policy generation module, MD5 algorithms computing module, Hash values match module portions
Point.Key policy generation module completes the cipher key combinations generation of finite length, and key length can support maximum N byte.MD5 is calculated
Method computing module includes major cycle 4 and takes turns computing, often takes turns 16 operations, totally 64 operations, to each operation, enter
The processing of row N level production lines, i.e. MD5 single -step operations computing N level production lines processing are realized, therefore 64*N is in whole MD5 algorithm computings
Level production line processing, so design can improve the operation clock frequency that FPGA realizes MD5 algorithm computings.
The MD5 Brute Force systems based on FPGA disclosed in the present invention include：Input interface unit, N core MD5 violences are broken
Solve arithmetic element and output interface unit.
Outside controller equiment is connected with input interface unit, realizes FPGA and controller communication；Input interface list
The message that member issues to controller carries out parsing distribution, and N core MD5 Brute Force arithmetic elements are managed.
N cores MD5 Brute Forces running unit is connected in parallel by N number of monokaryon MD5 Brute Forces arithmetic element, is to carry out parallel
Computing, each monokaryon are separate, and relative to monokaryon MD5 Brute Force arithmetic elements, arithmetic speed improves N times.
Monokaryon MD5 Brute Force arithmetic elements mainly include：Key policy generation module, MD5 algorithms computing module, Hash
It is worth matching module.
Key policy generation module：According to controller distributing policy, the combination producing of finite length key is realized, for not
Same policy selection, cipher key combinations can be numeral and spcial character, numeral and upper and lower case letter, upper and lower case letter and special word
All combinations such as symbol, pure digi-tal, pure alphabetical, pure character.
MD5 algorithm computing modules：The bottleneck of Brute Force is to crack speed, the computing of raising MD5 algorithm computing modules
Speed is the core of design, therefore operation each time, does the processing of N level production lines, and so design is greatly improved MD5 algorithms and transported
The operating rate of calculation.
Hash values match module：The key of key policy generation module generation is sent into MD5 algorithm arithmetic elements, by MD5
Algorithm arithmetic element module arithmetic obtains 4 32 a, b, c, d, and 4 data are spliced into the data of one 128, this 128
Data matched with cryptographic Hash to be cracked, the match is successful, i.e. the corresponding key of the data is the result cracked, i.e.,
Success is cracked, otherwise cracks failure.
Output interface unit：Management N core MD5 Brute Force running units crack result, and are reported to cracking result
Text analysis and framing, crack and successfully upload controller, stop task；Failure is cracked, uploads controller, waits the broken of lower subtask
Solution starts.
Embodiment two
A kind of MD5 Brute Force systems based on FPGA are disclosed in the present embodiment, including：Input interface unit, 8 cores
MD5 Brute Forces arithmetic element, output interface unit.
8 core MD5 Brute Force arithmetic elements are made up of 8 monokaryon MD5 Brute Force arithmetic element parallel connections, wherein, it is single
Core MD5 Brute Force arithmetic elements are to realize the core of MD5 Brute Force system operations, it is crucial that design realizes that MD5 is calculated
Method computing.
MD5 Brute Force of the present embodiment based on FPGA uses the pipeline design thought, monokaryon MD5 Brute Force computing lists
Member is connected in parallel whole the pipeline designs, and single step MD5 arithmetic operations improve FPGA using multi-stage pipeline design and realize that MD5 is calculated
The operation clock frequency of method computing, the clock frequency that the MD5 algorithms that the present invention designs are run in FPGA is 250MHz, main real
It is now as follows：
Key policy generation module：The character set issued according to controller, character set length, character set order, key length
The parameters such as degree, key start sequence position, strategically generate key.Such as the numeral and monogram one of key length 6
123abc keys, letter and character group the unification key of key length 6；When key policy generation module is run
Clock frequency 250MHz, i.e. 2.5 hundred million keys of generation per second.Such as key length is 8, character set length is 10, character set be Ah
Arabic numbers, then caused key range is 100,000,000 keys altogether between 00000000 to 99999999.
MD5 algorithms computing module takes turns major cycle computings using 4, often takes turns 16 operations, totally 64 operations, in order to
The clock rate that MD5 algorithms are run in FPGA is improved, each operation carries out 3 level production line processing, i.e. single -step operation computing
Design the processing of 3 level production lines, then MD5 often takes turns 16 operations, then to carry out 48 level production line processing, the wheel of MD5 algorithms 4 is altogether
The processing of 192 level production lines is counted, MD5 algorithms is improved and operation clock frequency is realized in FPGA, ensure that FPGA runs MD5 algorithms
Sequential not in violation of rules and regulations.The FPGA operation clock frequency 250MHz of design, therefore monokaryon MD5 Brute Force arithmetic elements crack speed
Rate is 2.5 hundred million times/s.
In order to match the clock frequency of FPGA operations, three sub- module clock frequencies of MD5 Brute Forces arithmetic element are all
250MHz, therefore Hash values match module 2.5 hundred million times/s of rate matched, i.e. 2.5 hundred million secondary keys of matching per second.Hash values match mould
Block directly abandons to the result that it fails to match, and the result that the match is successful directly reports output interface unit.For same subtask,
Hash values match module produces most 2 useful informations, and one is that the match is successful, and one is that cipher key match traversal is completed, so
Hash values match module output data quantity is seldom.
The speed of monokaryon MD5 Brute Force units improves, and improves and cracks efficiency；It is sudden and violent that multinuclear has even more significantly improved MD5
What power cracked cracks efficiency.Therefore the present embodiment is devised at the concurrent operation simultaneously of 8 core MD5 Brute Force arithmetic element modules
Reason, 8 cores are separate, the speed of 8 times of monokaryon MD5 Brute Force arithmetic elements, and the speed of monokaryon MD5 Brute Force units is
2.5 hundred million times/s, 8 cores then reach 2,000,000,000 times/s；For 10 keys of pure digi-tal combination, 10,000,000,000 secondary keys traversal is completed within 5 seconds,
The MD5 Brute Force efficiency being greatly improved, reduces the MD5 Brute Force times.
The FPGA of the present embodiment realizes that MD5 algorithm clocks are 250MHz, and the input data bit wides of MD5 algorithms is 512bit, 8
The data processing of core FPGA MD5 algorithm computings and data throughout are up to 128GB, i.e. data processing in 1 second reaches 128G words
Section, it can be seen that the data-handling capacity in the unit interval of the present embodiment is extremely strong.
Actually crack situation to see, simple key is substantially the second and broken, relative to existing MD5 breaking techniques, MD5 violences
Thousands of times of reductions of the time cracked, crack efficiency and greatly improve.
Embodiment three
The present embodiment proposes that one kind is based on based on the MD5 Brute Force systems based on FPGA disclosed in above-described embodiment
FPGA MD5 Brute Force methods, described MD5 Brute Force methods comprise the following steps：
Input interface unit is connected with the controller equiment of outside, FPGA and controller communication is realized, under controller
The message of hair carries out parsing and is distributed to N core MD5 Brute Force arithmetic elements；
N cores MD5 Brute Forces arithmetic element is made up of N number of monokaryon MD5 Brute Forces arithmetic element parallel connection, wherein,
Key policy generation module in monokaryon MD5 Brute Force arithmetic elements realizes that finite length is close according to controller distributing policy
The combination producing of key；
MD5 algorithms computing module in monokaryon MD5 Brute Force arithmetic elements carries out major cycle 4 and takes turns computing, often takes turns 16 times
Operation, totally 64 operations, to each operation, carry out N level production line processing, i.e. MD5 single -step operations computing N levels
Pipeline processes are realized；
What the Hash values match module in monokaryon MD5 Brute Force arithmetic elements obtained above-mentioned MD5 algorithms computing module
Data are matched with cryptographic Hash to be cracked, and the match is successful, i.e. the corresponding key of the data is the result cracked, i.e., broken
Solve successfully, otherwise crack failure；
Output interface unit is connected with the controller equiment of outside, manages described N core MD5 Brute Force running units
Crack result, and carry out message analysis and framing to cracking result, crack and successfully upload controller, stop task；Crack mistake
Lose, upload controller, wait lower subtask cracks startup.
In summary, the MD5 Brute Force system and methods based on FPGA disclosed in above-described embodiment make full use of multinuclear
Parallel processing mechanism and single-step run operation multi-stage pipeline processing thought, improve monokaryon MD5 Brute Force arithmetic elements
Speed, the design of multinuclear MD5 Brute Force arithmetic element concurrent operation treatment mechanisms, has significantly improved the effect of MD5 Brute Forces
Rate, reduces the time of MD5 Brute Forces, solves MD5 Brute Forces in the prior art well time-consuming, efficiency is low asks
Topic.
Above-described embodiment is the preferable embodiment of the present invention, but embodiments of the present invention are not by above-described embodiment
Limitation, other any Spirit Essences without departing from the present invention with made under principle change, modification, replacement, combine, simplification,
Equivalent substitute mode is should be, is included within protection scope of the present invention.
Claims (4)
1. a kind of MD5 Brute Force systems based on FPGA, it is characterised in that described MD5 Brute Forces system includes order
Input interface unit, N cores MD5 Brute Forces arithmetic element and the output interface unit of connection, wherein,
Described input interface unit is connected with the controller equiment of outside, FPGA and controller communication is realized, to controller
The message issued carries out parsing distribution, and N core MD5 Brute Force arithmetic elements are managed；
Described N cores MD5 Brute Forces arithmetic element is made up of the N number of monokaryon MD5 Brute Force arithmetic elements being connected in parallel, and is adopted
With multi-core parallel concurrent treatment mechanism, parallel generation key, the MD5 computings simultaneously of each monokaryon and then carry out Hash values match and respectively obtain
With result；
Described output interface unit is connected with the controller equiment of outside, and it is single to manage described N core MD5 Brute Forces operation
Member cracks result, and carries out message analysis and framing to cracking result, cracks and successfully uploads controller, stops task；Crack
Failure, controller is uploaded, wait lower subtask cracks startup.
2. the MD5 Brute Force systems according to claim 1 based on FPGA, it is characterised in that described monokaryon MD5 is sudden and violent
Power cracks the key policy generation module, MD5 algorithms computing module, Hash values match module that arithmetic element includes being linked in sequence,
Wherein,
Described key policy generation module realizes the combination producing of finite length key according to controller distributing policy；
Described MD5 algorithms computing module includes major cycle 4 and takes turns computing, often takes turns 16 operations, totally 64 operations, right
Each operation, carries out N level production line processing, i.e. MD5 single -step operations computing N level production lines processing is realized；
The data that described Hash values match module obtains described MD5 algorithm computing modules are carried out with cryptographic Hash to be cracked
Matching, the match is successful, i.e. the corresponding key of the data is the result cracked, that is, cracks success, otherwise crack failure.
3. the MD5 Brute Force systems according to claim 2 based on FPGA, it is characterised in that for different strategies
Selection, the cipher key combinations of described key policy generation module generation can be that numeral and spcial character, numeral and size are write
Female, upper and lower case letter and spcial character, the combination of pure digi-tal, pure alphabetical, pure character.
A kind of 4. MD5 Brute Force methods based on FPGA, it is characterised in that described MD5 Brute Forces method includes following
Step：
Input interface unit is connected with the controller equiment of outside, realizes FPGA and controller communication, controller is issued
Message carries out parsing and is distributed to N core MD5 Brute Force arithmetic elements；
N cores MD5 Brute Forces arithmetic element is made up of N number of monokaryon MD5 Brute Forces arithmetic element parallel connection, wherein, monokaryon
Key policy generation module in MD5 Brute Force arithmetic elements realizes finite length key according to controller distributing policy
Combination producing；
MD5 algorithms computing module in monokaryon MD5 Brute Force arithmetic elements carries out major cycle 4 and takes turns computing, often takes turns 16 operations
Computing, totally 64 operations, to each operation, carry out N level production line processing, i.e. MD5 single -step operations computing N level flowing water
Line processing is realized；
The data that Hash values match module in monokaryon MD5 Brute Force arithmetic elements obtains above-mentioned MD5 algorithms computing module
Matched with cryptographic Hash to be cracked, the match is successful, i.e. the corresponding key of the data is the result cracked, that is, is cracked into
Work(, otherwise crack failure；
Output interface unit is connected with the controller equiment of outside, manages the broken of described N core MD5 Brute Force running units
Result is solved, and message analysis and framing are carried out to cracking result, cracks and successfully uploads controller, stop task；Failure is cracked, on
Controller is passed, wait lower subtask cracks startup.
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| CN112166414A (en) * | 2018-05-15 | 2021-01-01 | 派泰克集群能力中心有限公司 | Apparatus and method for efficient parallel computing |
| CN116094733A (en) * | 2023-04-03 | 2023-05-09 | 中国电子科技集团公司第三十研究所 | Automatic cracking method and system for challenge/response identity authentication |
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| CN102156434A (en) * | 2011-04-20 | 2011-08-17 | 上海交通大学 | Ultrahigh-throughput MD5 brute-force cracking device implemented based on FPGA |
| CN103714300A (en) * | 2014-01-06 | 2014-04-09 | 武汉虹旭信息技术有限责任公司 | Encryption and analysis system based on distributed GPU and rainbow table and method of encryption and analysis system |
| CN105376061A (en) * | 2015-10-10 | 2016-03-02 | 广州慧睿思通信息科技有限公司 | Decryption hardware platform based on FPGA |
| CN106357384A (en) * | 2016-08-26 | 2017-01-25 | 广州慧睿思通信息科技有限公司 | Word2003 document cracking system based on FPGA hardware and method |
| CN106712928A (en) * | 2016-12-13 | 2017-05-24 | 云南电网有限责任公司电力科学研究院 | Big data rainbow table based decryption method and device |
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| CN112166414A (en) * | 2018-05-15 | 2021-01-01 | 派泰克集群能力中心有限公司 | Apparatus and method for efficient parallel computing |
| CN109344633A (en) * | 2018-09-28 | 2019-02-15 | 山东超越数控电子股份有限公司 | A kind of software decryption method based on mixed logic processor platform |
| CN116094733A (en) * | 2023-04-03 | 2023-05-09 | 中国电子科技集团公司第三十研究所 | Automatic cracking method and system for challenge/response identity authentication |
| CN116094733B (en) * | 2023-04-03 | 2023-08-22 | 中国电子科技集团公司第三十研究所 | Automatic cracking method and system for challenge/response identity authentication |
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