CN107464839A - A kind of grid-controlled transistor device for preventing shut-off from failing - Google Patents
A kind of grid-controlled transistor device for preventing shut-off from failing Download PDFInfo
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- CN107464839A CN107464839A CN201710707119.6A CN201710707119A CN107464839A CN 107464839 A CN107464839 A CN 107464839A CN 201710707119 A CN201710707119 A CN 201710707119A CN 107464839 A CN107464839 A CN 107464839A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 118
- 238000001465 metallisation Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 4
- 239000004020 conductor Substances 0.000 claims description 5
- 238000005036 potential barrier Methods 0.000 claims description 3
- 230000001413 cellular effect Effects 0.000 description 21
- 230000000694 effects Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- NOWRLNPOENZFHP-ARHDFHRDSA-N 1-[(1S,2S,4S,5R)-4-hydroxy-5-(hydroxymethyl)bicyclo[3.1.0]hexan-2-yl]thymine Chemical group O=C1NC(=O)C(C)=CN1[C@@H]1[C@H]2C[C@@]2(CO)[C@@H](O)C1 NOWRLNPOENZFHP-ARHDFHRDSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
- H01L29/745—Gate-turn-off devices with turn-off by field effect
- H01L29/7455—Gate-turn-off devices with turn-off by field effect produced by an insulated gate structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention provides a kind of grid-controlled transistor device for preventing shut-off from failing, and stacks gradually metallization anode, the first conductive type semiconductor substrate, the second conductive type semiconductor epitaxial layer, metallization negative electrode from top to bottom；Also include the first conductive type semiconductor well region, the second conductive type semiconductor well region, the first conductive type semiconductor of heavy doping area, grid structure；Only there is the first low-doped conductive type semiconductor area in the side of the second conductive type semiconductor well region and by the half of metal filled groove, the width in the first conductive type semiconductor area and the width sum of groove less than or equal to the second conductive type semiconductor well region width；The present invention can effectively prevent the shut-off of grid-controlled transistor device from failing, and improve the reliability of grid-controlled transistor device.
Description
Technical field
The present invention relates to technical field of semiconductor device, and in particular to a kind of grid-controlled transistor device for preventing shut-off from failing
Part.
Background technology
With the continuous development of human society, the consumption of the energy is continuously increased, while increasing energy output, energy profit
Also there is higher and higher requirement with rate.The realization of these requirements, depend on the development of power electronic devices.Mos gate control crystalline substance lock
Pipe obtains the concern of more and more people as novel semi-conductor device for power switching.
Fig. 1 show traditional N-type grid-controlled transistor structural representation.Grid-controlled transistor (MOS Controlled
Thyristor, MCT), it is a kind of compound power device for combining MOSFET characteristics and thyristor characteristics, has simultaneously
High MOSFET input impedance, fast switching speed, the blocking voltage that gate pole is easy to control and IGCT is high, low conducting work(
The advantages that consumption, big driving current, it is widely used in power switch field.As shown in Fig. 2 there are two MOSFET knots in N-MCT
Structure, ON-FET and OFF-FET, the two MOSFET share a grid, control MCT turn-on and turn-off respectively.When grid phase
During to negative electrode plus positive pulse voltage, ON-FET conductings, its drain current turns on PNP transistor, due to two transistors just
Feedback effect, finally turn on MCT.When grid opposing cathode adds negative pulse voltage, OFF-FET conductings, by NPN transistor
Emitter junction bypasses, and turns off NPN, destroy IGCT holds up condition, forces MCT to turn off.
Easily occur when off yet with device the uneven phenomenon of CURRENT DISTRIBUTION cause shut-off fail, device can
It is poor by property.Its reason needs to make grid voltage decline (by taking N-MCT as an example) to gate capacitance charging when being due to shut-off, and reach can
The grid voltage for turning off MCT cellulars needs the regular hour；Again because interconnection resistance between grid and grid be present, therefore from signal source
The more remote cellular grid charging interval will be longer, and when the cellular shut-off nearest from signal source, plasma therein " will be squeezed
To " in the cellular remote from signal source, increase cellular electric current.When the translational speed of plasma is too fast and signal source transmits signal
To farthest cellular overlong time, and make cellular begin to turn off required grid voltage it is too high when, the cellular mos gate being not turned off can be caused
Drop to before can successfully turning off, electric current has increased beyond the maximum controllable current of MCT cellulars, causes electric current collection
In, device can not turn off.
Therefore the grid voltage for making cellular shut-off required is reduced, i.e. threshold voltage needed for OFF-FET unlatchings can effectively be prevented
Only shut-off failure, improve MCT reliabilities.Manufacturing process yet with traditional grid-controlled transistor is based on the triple of DMOS technologies
Diffusion technique, the p-well and N traps of cathode side are diffuseed to form by injection, therefore the doping concentration of N traps is more than under normal circumstances
The doping concentration of p-well, adjustable scope very little, therefore the doping concentration for adjusting N traps can not effectively reduce OFF-FET threshold
Threshold voltage.Therefore traditional grid-controlled transistor structure can not be effectively reduced OFF-FET threshold voltage.
The content of the invention
The problem of purpose of the present invention exists aiming at above-mentioned traditional grid-controlled transistor, propose that one kind prevents shut-off from failing
Grid-controlled transistor device.
To achieve the above object, the present invention adopts the following technical scheme that：
A kind of grid-controlled transistor device for preventing shut-off from failing, metallization anode, the first conduction are stacked gradually from top to bottom
Type semiconductor substrate, the second conductive type semiconductor epitaxial layer, metallization negative electrode；The second conductive type semiconductor extension
The internal upper strata of layer has the first conductive type semiconductor well region；Upper strata has the inside the first conductive type semiconductor well region
Two conductive type semiconductor well regions；The top both sides of the second conductive type semiconductor well region have the conductive-type of heavy doping first
Type semiconductor region；At the top of the second conductive type semiconductor well region and the first conductive type semiconductor area with the negative electrode that metallizes
Connection；The second conductive type semiconductor well region both sides have grid structure；The grid structure is under metallization negative electrode
Surface sequentially passes through the first conductive type semiconductor area, the second conductive type semiconductor well region, the first conduction type vertically downward
Semiconductor well region；There are polygate electrodes, the polygate electrodes are partly led with the second conduction type in the grid structure
Body epitaxial layer, the first conductive type semiconductor well region, the second conductive type semiconductor well region and the first conductive type semiconductor area
Isolated between four by gate oxide, insulating medium layer is filled between the polygate electrodes and metallization negative electrode, it is described
Junction depth of the lower surface depth of polygate electrodes more than the first conductive type semiconductor well region；Only in second conduction type
The side of semiconductor well region has the first low-doped conductive type semiconductor area and led by metal filled groove, described first
The lower surface in electric type semiconductor area is in contact with the first conductive type semiconductor well region, the first conductive type semiconductor area
Upper surface and the first conductive type semiconductor of heavy doping area be in contact, the side in the first conductive type semiconductor area and grid
Oxide layer is in contact, the opposite side in the first conductive type semiconductor area and the second conductive type semiconductor well region and groove phase
Contact；The top of the groove is in contact with metallization negative electrode；The depth of the groove lower surface is less than the second conduction type half
The junction depth of conductor well region lower surface；The width in the first conductive type semiconductor area and the width sum of groove are less than or equal to
The half of second conductive type semiconductor well region width；The groove and the first conductive type semiconductor area form schottky junctions
Touch, the groove and the first conductive type semiconductor of heavy doping area form Ohmic contact；The first conductive type semiconductor area
Width be less than or equal to the barrier region of schottky junction that groove and the first conductive type semiconductor area are formed when being not added with biasing
Width.
It is preferred that the first conduction type is p-type, the second conduction type is N-type；Or first conduction type be N
Type, the second conduction type are p-type.
Beneficial effects of the present invention are：Effectively prevent the shut-off of grid-controlled transistor device from failing, improve grid-controlled transistor
The reliability of device.
Brief description of the drawings
Fig. 1 is traditional N-type grid-controlled transistor structural representation；
Fig. 2 is the schematic equivalent circuit of N-type grid-controlled transistor；
Fig. 3 is a kind of grid-controlled transistor device architecture schematic diagram for preventing shut-off from failing provided by the invention.
Wherein, 301 be metallization anode, and 302 be the first conductive type semiconductor substrate, and 303 be the second conduction type half
Conductor epitaxial layer, 304 be polygate electrodes, and 305 be gate oxide, and 306 be the first conductive type semiconductor of heavy doping area,
307 be the first conductive type semiconductor well region, and 308 be the second conductive type semiconductor well region, and 309 be insulating medium layer, and 310 are
Metallize negative electrode, and 311 be the first conductive type semiconductor area, and 312 be groove.
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
As shown in figure 3, a kind of grid-controlled transistor device for preventing shut-off from failing, stacks gradually metallization anode from top to bottom
301st, the first conductive type semiconductor substrate 302, the second conductive type semiconductor epitaxial layer 303, metallization negative electrode 310；It is described
The inside upper strata of second conductive type semiconductor epitaxial layer 303 has the first conductive type semiconductor well region 307；Described first is conductive
The inside upper strata of type semiconductor well region 307 has the second conductive type semiconductor well region 308；Second conductive type semiconductor
The top both sides of well region 308 have the first conductive type semiconductor of heavy doping area 306；The second conductive type semiconductor well region
308 and the top of the first conductive type semiconductor area 306 be connected with metallization negative electrode 310；Second conductive type semiconductor
The both sides of well region 308 have grid structure；The grid structure sequentially passes through the vertically downward from the lower surface of metallization negative electrode 310
One conductive type semiconductor area 306, the second conductive type semiconductor well region 308, the first conductive type semiconductor well region 307；Institute
Stating has polygate electrodes 304 in grid structure, the conductive type semiconductor epitaxial layer of polygate electrodes 304 and second
303rd, the first conductive type semiconductor well region 307, the second conductive type semiconductor well region 308 and the first conductive type semiconductor area
Isolated between 306 4 by gate oxide 305, fill and insulate between the polygate electrodes 304 and metallization negative electrode 310
Dielectric layer 309, the junction depth of the lower surface depth of the polygate electrodes 304 more than the first conductive type semiconductor well region 307；
Only there is the low-doped He of the first conductive type semiconductor area 311 in the side of the second conductive type semiconductor well region 308
By metal filled groove 312, the lower surface in the first conductive type semiconductor area 311 and the first conductive type semiconductor trap
Area 307 is in contact, the upper surface and the first conductive type semiconductor of heavy doping area in the first conductive type semiconductor area 311
306 are in contact, and the side in the first conductive type semiconductor area 311 is in contact with gate oxide 305, first conductive-type
The opposite side of type semiconductor region 311 is in contact with the second conductive type semiconductor well region 308 and groove 312；The groove 312
Top is in contact with metallization negative electrode 310；The depth of the lower surface of groove 312 is less than the second conductive type semiconductor well region
The junction depth of 308 lower surfaces；The width in the first conductive type semiconductor area 311 and the width sum of groove 312 are less than or waited
In the half of the width of the second conductive type semiconductor well region 308；The shape of 312 and first conductive type semiconductor area of groove 311
Into Schottky contacts, the groove 312 and the first conductive type semiconductor of heavy doping area 306 form Ohmic contact；Described first
The width in conductive type semiconductor area 311 is less than or equal to the Xiao Te that the conductive type semiconductor area 311 of groove 312 and first is formed
Potential barrier sector width of the base junction when being not added with biasing.
When the first conductive type semiconductor is P-type semiconductor, the second conduction type is N-type, the present embodiment prevents from closing
The grid-controlled transistor of disconnected failure is N-type grid-controlled transistor, below by taking N-type grid-controlled transistor as an example, describes the work of the present invention in detail
Make principle：
The grid-controlled transistor device of this example, electrode connection mode during its forward conduction are：Metallization anode 301 connects high electricity
Position, metallization negative electrode 310 connect low potential, and polygate electrodes 304 are relative to connect positive voltage for metallization negative electrode 310.In zero-bias
When, the schottky junction that groove 312 and the formation of p type island region 311 are less than or equal to due to the width of p type island region 311 in the cellular of right side half is existed
Potential barrier sector width during biasing is not added with, so p type island region 311 is completely depleted, hole is not present between p-well region 307 and P+ areas 306
Passage.When the voltage on polygate electrodes 304 gradually increases and is more than threshold voltage, half in no side of p type island region 311
In cellular, transoid is formed raceway groove by the surface of p-well region 307 between the area of N traps 308 and N- epitaxial layers 303.And opposite side half dollar
Due to introducing p type island region 311 in born of the same parents, the surface of p-well region 307 and p type island region 311 forms inversion layer, but N well regions 308 and transoid
There is the barrier of the non-inverting portions in p type island region 311 between layer raceway groove, therefore can not turn on.Therefore, the grid-control that this example is provided
Thyristor device only has the cellular forward conduction of half, although the conducting speed of device has certain reduction, works as IGCT
Into after latch mode, its forward conduction voltage drop is unrelated with mos gate control part, can't be affected.
The grid-controlled transistor device of this example, electrode connection mode when it is reversely turned off are：Metallization anode 301 connects high electricity
Position, metallization negative electrode 310 connect low potential, and the opposing metallic negative electrode 310 of polygate electrodes 304 connects negative voltage.Work as polysilicon gate
When on electrode 304 plus the negative voltage of very little, in half cellular with the side of p type island region 311, p type island region 311 is close to grid oxygen
The surface for changing layer forms hole accumulation layer, and hole passage, i.e. OFF-FET ditch are formed between p-well region 307 and P+ areas 306
Road is opened, and the cellular of right side half enters off state, starts to extract electric current.When the negative voltage on polygate electrodes 304 continues to increase
Greatly, when reaching the OFF-FET of half cellular of no side of p type island region 311 threshold voltage, whole grid-controlled transistor cellular all enters
Off state.
Due to the presence of hole accumulation layer, reduce OFF-FET open needed for threshold voltage, need to give grid electricity during shut-off
Time of capacity charge shortens, effectively prevent from having little time to turn off because of part cellular caused by turn off failure caused by current convergence.
During gate voltage rises, because the cellular of half is first turned off, shut-off cellular and it is not turned off cellular and is alternately arranged, effectively
Current convergence is alleviated, improves the reliability of grid-controlled transistor.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, all those of ordinary skill in the art without departing from disclosed spirit with being completed under technological thought
All equivalent modifications or change, should by the present invention claim be covered.
Claims (2)
1. a kind of grid-controlled transistor device for preventing shut-off from failing, metallization anode (301) is stacked gradually from top to bottom, first is led
Electric type semiconductor substrate (302), the second conductive type semiconductor epitaxial layer (303), metallization negative electrode (310)；Described second
The internal upper strata of conductive type semiconductor epitaxial layer (303) has the first conductive type semiconductor well region (307)；Described first is conductive
The internal upper strata of type semiconductor well region (307) has the second conductive type semiconductor well region (308)；Second conduction type half
The top both sides of conductor well region (308) have the first conductive type semiconductor of heavy doping area (306)；Second conduction type half
It is connected at the top of conductor well region (308) and the first conductive type semiconductor area (306) with metallization negative electrode (310)；Described second
Conductive type semiconductor well region (308) both sides have grid structure；The grid structure from metallization negative electrode (310) lower surface
The first conductive type semiconductor area (306), the second conductive type semiconductor well region (308) are sequentially passed through vertically downward, first are led
Electric type semiconductor well region (307)；There are polygate electrodes (304), the polygate electrodes in the grid structure
(304) with the second conductive type semiconductor epitaxial layer (303), the first conductive type semiconductor well region (307), the second conduction type
Isolated between semiconductor well region (308) and the first conductive type semiconductor area (306) four by gate oxide (305), it is described
Insulating medium layer (309), the polygate electrodes are filled between polygate electrodes (304) and metallization negative electrode (310)
(304) junction depth of the lower surface depth more than the first conductive type semiconductor well region (307)；It is characterized in that：Only described
The side of two conductive type semiconductor well regions (308) has the first low-doped conductive type semiconductor area (311) and by metal
The groove (312) of filling, lower surface and the first conductive type semiconductor well region of the first conductive type semiconductor area (311)
(307) it is in contact, the upper surface and the first conductive type semiconductor of heavy doping area of the first conductive type semiconductor area (311)
(306) it is in contact, the side of the first conductive type semiconductor area (311) is in contact with gate oxide (305), and described first
The opposite side in conductive type semiconductor area (311) is in contact with the second conductive type semiconductor well region (308) and groove (312)；
The top of the groove (312) is in contact with metallization negative electrode (310)；The depth of groove (312) lower surface is less than second
The junction depth of conductive type semiconductor well region (308) lower surface；The width and groove of the first conductive type semiconductor area (311)
(312) width sum is less than or equal to the half of second conductive type semiconductor well region (308) width；The groove (312)
Schottky contacts, the groove (312) and the conduction type of heavy doping first half are formed with the first conductive type semiconductor area (311)
Conductor region (306) forms Ohmic contact；The width of the first conductive type semiconductor area (311) is less than or equal to groove
(312) the potential barrier sector width with the schottky junction that the first conductive type semiconductor area (311) is formed when being not added with biasing.
A kind of 2. grid-controlled transistor device for preventing shut-off from failing according to claim 1, it is characterised in that：First is conductive
Type is p-type, and the second conduction type is N-type；Or first conduction type be N-type, the second conduction type is p-type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710707119.6A CN107464839B (en) | 2017-08-17 | 2017-08-17 | Gate controlled thyristor device for preventing turn-off failure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710707119.6A CN107464839B (en) | 2017-08-17 | 2017-08-17 | Gate controlled thyristor device for preventing turn-off failure |
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| Publication Number | Publication Date |
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| CN107464839A true CN107464839A (en) | 2017-12-12 |
| CN107464839B CN107464839B (en) | 2020-02-04 |
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| CN201710707119.6A Expired - Fee Related CN107464839B (en) | 2017-08-17 | 2017-08-17 | Gate controlled thyristor device for preventing turn-off failure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110927546A (en) * | 2018-09-20 | 2020-03-27 | 清华大学 | Method for testing cell characteristics of thyristor |
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| JPS599968A (en) * | 1982-07-07 | 1984-01-19 | Mitsubishi Electric Corp | Gate turn-off thyristor |
| JP2007258591A (en) * | 2006-03-24 | 2007-10-04 | Ngk Insulators Ltd | Electrostatic inductive thyristor with current control layer and protect circuit/pulse generating circuit of electrostatic inductive thyristor with current control layer |
| CN101393927A (en) * | 2008-10-31 | 2009-03-25 | 电子科技大学 | Accumulation layer controlled insulation gate type bipolar transistor |
| CN101821852A (en) * | 2007-08-08 | 2010-09-01 | 先进模拟科技公司 | The cascode current sensor that is used for discrete power semiconductor devices |
| CN102623492A (en) * | 2012-04-06 | 2012-08-01 | 电子科技大学 | MOS (Metal Oxide Semiconductor) field control thyristor |
| CN103956381A (en) * | 2014-05-07 | 2014-07-30 | 电子科技大学 | MOS grid-control thyristor |
| EP2237319B1 (en) * | 1999-02-17 | 2015-04-08 | Hitachi Power Semiconductor Device, Ltd. | Seminconductor device and power converter using the same |
| US20150144992A1 (en) * | 2013-11-28 | 2015-05-28 | Samsung Electro-Mechanics Co., Ltd. | Power semiconductor device |
-
2017
- 2017-08-17 CN CN201710707119.6A patent/CN107464839B/en not_active Expired - Fee Related
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS599968A (en) * | 1982-07-07 | 1984-01-19 | Mitsubishi Electric Corp | Gate turn-off thyristor |
| EP2237319B1 (en) * | 1999-02-17 | 2015-04-08 | Hitachi Power Semiconductor Device, Ltd. | Seminconductor device and power converter using the same |
| JP2007258591A (en) * | 2006-03-24 | 2007-10-04 | Ngk Insulators Ltd | Electrostatic inductive thyristor with current control layer and protect circuit/pulse generating circuit of electrostatic inductive thyristor with current control layer |
| CN101821852A (en) * | 2007-08-08 | 2010-09-01 | 先进模拟科技公司 | The cascode current sensor that is used for discrete power semiconductor devices |
| CN101393927A (en) * | 2008-10-31 | 2009-03-25 | 电子科技大学 | Accumulation layer controlled insulation gate type bipolar transistor |
| CN102623492A (en) * | 2012-04-06 | 2012-08-01 | 电子科技大学 | MOS (Metal Oxide Semiconductor) field control thyristor |
| US20150144992A1 (en) * | 2013-11-28 | 2015-05-28 | Samsung Electro-Mechanics Co., Ltd. | Power semiconductor device |
| CN103956381A (en) * | 2014-05-07 | 2014-07-30 | 电子科技大学 | MOS grid-control thyristor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110927546A (en) * | 2018-09-20 | 2020-03-27 | 清华大学 | Method for testing cell characteristics of thyristor |
| CN110927546B (en) * | 2018-09-20 | 2021-01-05 | 清华大学 | Method for testing cell characteristics of thyristor |
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| Publication number | Publication date |
|---|---|
| CN107464839B (en) | 2020-02-04 |
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