CN107452740B - 具有备用单元的集成电路 - Google Patents

具有备用单元的集成电路 Download PDF

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CN107452740B
CN107452740B CN201710323954.XA CN201710323954A CN107452740B CN 107452740 B CN107452740 B CN 107452740B CN 201710323954 A CN201710323954 A CN 201710323954A CN 107452740 B CN107452740 B CN 107452740B
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CN107452740A (zh
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安德里亚斯·罗兰·斯特尔
休伯特·马丁·博德
伊尔汉·哈齐尔纳兹
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NXP USA Inc
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Abstract

本发明涉及一种集成电路(50)，其包括第一电压端(VDD)；第二电压端(VSS)；以及多个逻辑单元(52)，所述逻辑单元(52)包括具有p型通道的一个或多个场效应晶体管和具有n型通道的一个或多个场效应晶体管。所述多个逻辑单元包括单元(54)的常规子集和单元(56)的备用子集。电连接器(57、58、59)被布置成：连接单元(54)的所述常规子集的栅极以便提供功能性逻辑布置；将单元(56)的所述备用子集的具有p型通道的所述一个或多个场效应晶体管的所述栅极连接到所述第一电压端(VDD)；且将单元(56)的所述备用子集的具有n型通道的所述一个或多个场效应晶体管的所述栅极连接到所述第二电压端(VSS)。

Description

具有备用单元的集成电路
技术领域
本发明大体上涉及具有常规单元和备用单元的集成电路，且具体地但非排他性地说，涉及减少包括备用单元的IC中的功率消耗。
背景技术
传统的基于单元的专用集成电路(ASIC)布局设计通常包括被互连以执行ASIC的所要功能或逻辑的常规单元的集合。具体地说，ASIC布局设计在复杂集成电路(例如，处理器)的超大规模集成(VLSI)中很常见。除了功能性逻辑单元的基本集合之外，ASIC布局设计通常包括贯穿常规单元随机分散的多个备用单元。出于在工程变更单(ECO)过程期间校正、更改或改变ASIC的功能性的目的将备用单元包括于ASIC设计中。
行业中需要提高常规单元的密度。也需要提高散布的备用单元的密度以改进互连性和功能性选择。然而，随着单元的密度不断增大，整体功率消耗已更显著增加。通常，无论是常规单元还是备用单元，每个单元都促成ASIC的整体功率消耗。因此希望减少ASIC的功率消耗，且特别是备用单元，以便改进集成电路的整体效率。
发明内容
根据本发明的第一方面，提供一种集成电路，所述集成电路包括：
第一电压端；
第二电压端，其中第一电压端被配置成接收相对于第二电压端的正电压；
多个逻辑单元，每个逻辑单元包括具有p型通道的一个或多个场效应晶体管和具有n型通道的一个或多个场效应晶体管，其中每个晶体管具有栅极，且其中多个逻辑单元包括单元的常规子集和单元的备用子集；以及
电连接器，其被配置成：
连接单元的常规子集的栅极以便提供功能性逻辑布置；
将单元的备用子集的具有p型通道的一个或多个场效应晶体管的栅极连接到第一电压端；且
将单元的备用子集的具有n型通道的一个或多个场效应晶体管的栅极连接到第二电压端。
电连接器可包括金属迹线或导电迹线。金属迹线或导电迹线可提供于单个层中或多个层中。每个单元可提供逻辑栅极。单元的常规子集中的每个常规子集可与单元的备用子集具有相同结构。单元的备用子集中的不同单元可提供不同相应的逻辑结构。
根据本发明的另一方面，提供一种修改前述的集成电路的方法，所述方法包括：
任选地接收集成电路；
将单元的备用子集中的至少一个备用子集的具有p型通道的一个或多个场效应晶体管的栅极与第一电压端断开连接；
将单元的至少一个备用子集的具有n型通道的一个或多个场效应晶体管的栅极与第二电压端断开连接；以及
将单元的至少一个备用子集的场效应晶体管的栅极连接到单元的常规子集的栅极，以便提供修改的功能性逻辑布置。
可使用蚀刻或研磨(例如，离子束研磨)来实现断开连接。金属迹线或导电迹线可沉积于衬底上以便将单元的至少一个备用子集的场效应晶体管的栅极连接到单元的常规子集的栅极。
根据本发明的另一方面，提供一种制造集成电路的方法，所述方法包括：
形成集成电路衬底，所述集成电路衬底包括：
第一电压端；
第二电压端，其中第一电压端被配置成接收相对于第二电压端的正电压；
多个逻辑单元，每个逻辑单元包括具有p型通道的一个或多个场效应晶体管和具有n型通道的一个或多个场效应晶体管，其中每个晶体管具有栅极，且其中多个逻辑单元包括单元的常规子集和单元的备用子集；
将单元的常规子集与布置为提供功能性逻辑布置的一个或多个电连接器连接；
使用一个或多个电连接器将单元的备用子集的具有p型通道的一个或多个场效应晶体管的栅极连接到第一电压端；且
使用一个或多个电连接器将单元的备用子集的具有n型通道的一个或多个场效应晶体管的栅极连接到第二电压端。
一个或多个电连接器可包括金属迹线或导电迹线。半导体衬底可包括所述多个单元。方法可包括将金属迹线或导电迹线沉积在衬底的表面上。金属迹线或导电迹线可提供于单个层中或多个层中。每个晶体管可具有源极和漏极。金属层可用以将具有n型通道的一个或多个场效应晶体管的漏极与具有p型通道的一个或多个场效应晶体管的源极连接。备用单元与电压端之间的电连接器可包括多晶硅电线。
虽然本发明容许各种修改和可替换形式，但其细节已经借助于例子在附图中示出且将详细地描述。然而，应理解，也可能存在除所描述的特定实施例以外的其它实施例。还涵盖属于所附权利要求书的精神和范围内的所有修改、等效物和可替换实施例。
以上论述并不旨在呈现当前或未来权利要求集的范围内的每一个示例实施例或每一个实施方案。以下各图和具体实施方式还举例说明了各种示例实施例。结合附图考虑以下具体实施方式可以更全面地理解各种示例实施例。
附图说明
现将仅作为例子且参考附图描述本发明的一个或多个实施例，其中：
图1示出具有常规单元和备用单元的集成电路的单元布局的平面图；
图2示出具有各种电流泄漏路径的场效应晶体管的示意性横截面；
图3示出供用作常规单元的NOR2逻辑栅极的电路图；
图4示出供用作备用单元的NOR2逻辑栅极的电路图；
图5示出具有减少的备用单元功率消耗的集成电路；
图6示出供用作集成电路中的常规单元的NOR2逻辑栅极的电路图；
图7示出供用作集成电路中的备用单元的NOR2逻辑栅极的电路图；
图8示出图6的逻辑栅极的示例电路布局的示意性平面图；
图9示出图7的逻辑栅极的示例电路布局的示意性平面图；
图10示出用于制造集成电路的方法；且
图11示出用于修改集成电路的方法。
具体实施方式
图1示意性地示出集成电路10的半导体衬底的单元布局的平面图。集成电路10包括多个逻辑单元12、14。所述多个逻辑单元包括单元的常规子集或常规单元14，以及单元的备用子集或备用单元12。常规单元14实施集成电路10的原始所要的逻辑。每个逻辑单元12、14包括具有p型通道的一个或多个场效应晶体管(FET-未示出)和具有n型通道的一个或多个FET(未示出)。每个FET具有栅极、源极和漏极，且可由金属氧化物半导体(MOS)装置提供。
使用金属化工艺将导电迹线沉积在半导体衬底上以便将栅极与常规单元14的其它端连接且提供所要的功能性逻辑布置。金属化工艺可沉积金属(例如，铜)或另一种导电材料，例如多晶硅。
在金属化之后，常常需要对IC进行某些功能性维修、修改和/或增强来克服IC的功能中的任何问题或缺点。存在于IC设计内的备用单元12可被转换为“新的常规单元”并用以实现IC的整体功能性逻辑的功能性维修、修改和/或增强。备用单元12选自IC设计内以用于转换且可在IC已进行金属化之前或者之后被转换。建立新的连接以在原始常规单元14和新的常规单元之间互连。选择IC设计中的特定备用单元12并在工程变更单(ECO)过程期间将其布置成具有金属互连的特定电路配置以形成IC的工作功能性的一部分。新的常规单元12与原始常规单元14互连以便在IC的维修、修改或增强期间实现所要的功能性。并非必须选择所有备用单元12来在ECO期间与常规单元14互连。IC设计中未转换的备用单元12不用以实现IC的预期逻辑或工作功能性，但仍促成IC的功率消耗。
图2示意性地示出具有各种电流损失的CMOS场效应晶体管的横截面(此例子中示出p通道(NPN)FET)。晶体管具有源极端22、栅极端24、漏极端26和主体端28。
对于CMOS FET存在四个主要的泄漏电流源极：
1.漏极端26与主体端28之间的反向偏置结泄漏电流(IREV)；
2.栅极区25中的漏极端26与主体端28之间的栅极诱发的漏极泄漏(IGIDL)；
3.栅极端24与主体端28之间的栅极直接隧穿泄漏(IG)；以及
4.栅极区25中的漏极端26与源极端22之间的亚阈(弱反型)泄漏(ISUB)。
虽然从设计灵活性观点来看在IC中放置较多备用单元以便实现仅金属变化并在执行ECO时避免前端层的变化是优选的，但提供其它备用单元占据较大面积且增大泄漏电流。此外，具有相对快速切换时间(例如标准电压阈值(基于SVT)切换)的单元可适用于提供备用单元，这是因为当以功能性逻辑实施时对备用单元的最终时序要求在首次制造时未知。然而，此类单元归因于备用单元提供而趋向于具有相对高的功率消耗且因此加剧与功率损耗相关联的问题，且导致备用单元对CMOS栅极区域中的泄漏电流作出超过平均的贡献。
备用单元可包括具有不同功能的不同单元的集合。每个备用单元通常包括至少一个晶体管且被预配置成用于特定逻辑功能。举例而言，每个备用单元可包括使用PMOS或NMOS设计的至少一个逻辑栅极，例如反相器、NAND、NOR、触发器等等。
图3和图4分别示出常规单元30和备用单元40的示例逻辑栅极的电路图，常规单元30和备用单元40供用作例如先前参考图1所描述的电路等集成电路中的单元。此例子中的常规单元30和备用单元40各自提供NOR2逻辑栅极结构。
NOR2逻辑栅极包括正电压端、负电压或接地端，和被布置成提供NOR2逻辑的多个场效应晶体管(FET)。一般来说，正电压端可被称为第一电压端VDD，且负电压或接地端可被称为第二电压端VSS。所述多个FET包括第一p通道FET 32、42；第二p通道FET 34、44；第一n通道FET 36、46和第二n通道FET 38、48。每个FET 32、42、34、44、36、46；38、48具有栅极端、源极端、漏极端和主体端。
第一和第二p通道FET 32、42、34、44的主体端连接到第一电压端VDD。第一和第二n通道FET 36、46、38、48的主体端连接到第二电压端VSS。
第一p通道FET 32、42的源极端连接到第一电压端VDD。第一p通道FET 32、42的漏极端连接到第二p通道FET 34、44的源极端。第二p通道FET 34、44的漏极端连接到第一和第二n通道FET 36、46、38、48的漏极端。第一和第二n通道FET 36、46、38、48的源极端连接到VSS。
在图3中示出的常规单元布置中，第一p通道FET 32的栅极连接到第一n通道FET36的栅极以便接收第一逻辑输入A。第二p通道FET 34的栅极连接到第二n通道FET 36的栅极以便接收第二逻辑输入B。
在图4中示出的备用单元布置中，所有FET 42、44、46、48的栅极连接到第二电压端VSS。在所有选择的和未选择的备用单元中，PMOS和NMOS晶体管的端始终连接到VDD和VSS。这导致电流通过VDD、VSS和栅漏且增加消散的泄漏功率。
以此方式，无论是原始常规单元、未被转换的备用单元还是新的常规单元，IC的每个单元都接地且连接到电源。每一个备用单元，甚至保持不连接到常规单元且不成为IC的工作功能性的一部分的未被转换的备用单元，都在金属化工艺之前和之后接地且连接到电源，且因此促成IC的整体功率消耗。因此需要将功率消耗降至最低或减少功率消耗同时维持通过提供备用单元来实现的设计灵活性。
图5示出具有减少的备用单元功率消耗的集成电路50的示例实施例。
集成电路50具有第一电压端VDD和第二电压端VSS。第一电压端VDD被配置成接收相对于第二电压端VSS的正电压。也就是说，第一电压端VDD可被认为是正电压端且第二电压端VSS可被认为是负电压端或接地电压端。
如在参考图1所描述的例子中，集成电路50包括多个逻辑单元52。每个逻辑单元52包括具有p型通道的一个或多个场效应晶体管(FET-未示出)和具有n型通道的一个或多个FET(未示出)。每个FET至少具有栅极端、源极端和漏极端子，且可由例如金属氧化物半导体(MOS)装置提供。所述多个逻辑单元52包括单元的常规子集或常规单元54，以及单元的备用子集或备用单元56。常规单元54实施集成电路50原始所要的逻辑，且备用单元为执行工程变更单(ECO)提供功能灵活性。
第一组电连接器57连接单元的常规子集的栅极以便提供功能性逻辑布置。
第二组电连接器58将备用单元56的具有p型通道的一个或多个场效应晶体管的栅极连接到正电压端VDD。第二组电连接器59将备用单元56的具有n型通道的场效应晶体管的栅极连接到负电压端VSS。在此配置中，备用单元56中的所有晶体管被断开，使得备用单元56中的晶体管的输出处于高阻抗状态。栅漏和亚阈泄漏显著减少，且因此集成电路50的布置使得泄漏电流与图4中的例子相比整体减少。然而，集成电路50的布置保持提供的备用单元的核心优点，这是因为可通过修正覆盖的金属化层来改变集成电路50的功能性布局以便实施工程变更单，而不需要修改集成电路50的衬底。
以下关于图6到图9针对NOR2结构描述根据图5的例子的备用和常规单元的特定实施方案。
图6和图7分别示出例如参考图5所描述集成电路中的供用作常规单元60和备用单元70的NOR2逻辑栅极的电路图。
常规单元60的布置与先前参考图3所描述的布置相同。
图7的备用单元70与先前参考图4描述的备用单元的布置具有类似性，这是因为所述多个FET包括第一p通道FET 72、第二p通道FET 74、第一n通道FET 76和第二n通道FET78。每个FET 72、74、76、78具有栅极端、源极端、漏极端和主体端。备用单元70不同于先前参考图4描述的备用单元，这是因为第一和第二p通道FET 72、74的栅极连接到第一电压端VDD而非第二电压端VSS。备用单元70不同于图6中示出的常规单元，这是因为对PMOS晶体管72、74和NMOS晶体管76、78的输入(栅极)分别连到第一电压端VDD和第二电压端VSS。对p装置和n装置的常用输入在备用单元70中分离，这是因为PMOS输入(栅极)连到VDD且NMOS输入(栅极)连到VSS。在此配置中，所有晶体管72、74、76、78被断开，使得晶体管72、74、76、78的输出处于高阻抗状态。
备用单元70的布置与先前参考图4描述的备用单元相比对备用单元70的功率消耗具有有利的影响。举例来说，备用单元70的栅极到孔电压为0V，这使得栅漏(如参考图2所论述的栅极直接隧穿泄漏(IG))显著减少。此外，漏极到源极电压降低且因此亚阈泄漏(ISUB)显著减少。在次页中的表中示出参考图4描述的‘原始’备用单元与‘提议的’备用单元70之间的全部单元泄漏电流的比较。
图8示意性地示出先前参考图6描述的标准单元的逻辑栅极800的示例电路布局的平面图。在此例子中，逻辑栅极800提供NOR2逻辑布置。
逻辑栅极800包括具有第一作用区域802和第二作用区域804的衬底。第一作用区域802包括第一PMOS FET和第二PMOS FET且第二作用区域804包括第一NMOS FET和第二NMOS FET，如先前参考图6所描述。
在衬底上提供第一导电层。第一导电层提供第一电压端VDD和第二电压端VSS。在第一电压端VDD与第一作用区域802之间提供第一金属连接806以便将第一作用区域802中的第一p-FET(未示出)的漏极连接到第一电压端VDD。还在第二电压端VSS与第二作用区域804之间提供第二金属连接808以便将第二作用区域804中的n-FET(未示出)的源极连接到第二电压端VSS。第一导电层另外包括第一作用区域802与第二作用区域804之间的第三金属连接(Z)814。第三金属连接(Z)814在第一作用区域802的第二p-FET(未示出)的源极与第二作用区域804中的第一n-FET和第二n-FET的漏极之间提供电连接。
还提供第二导电层。第二导电层包括第四金属连接816和第五导电连接818。第四和第五导电连接816、818中的每个导电连接在第一作用区域802与第二作用区域804之间提供电连接。第一作用区域802中的第一p通道FET的栅极通过第四导电连接816连接到第二作用区域804中的第一n通道FET的栅极以便接收第一逻辑输入A。第一作用区域802中的第二p通道FET的栅极通过第四导电连接816连接到第二作用区域804中的第二n通道FET 26的栅极以便接收第二逻辑输入B。
第一导电层可与第二导电层电绝缘。具体地说，在一个层覆盖另一层时，第五导电层818不与第三导电层814直接电接触，如图8中所示出。
可由第一类型的材料提供第一导电层且可由第二类型的材料提供第二导电层(其中第一类型的材料是与第二类型的材料不同类型的材料)。多晶硅可沉积于衬底的表面处的沟槽中或沉积于衬底上。金属层可形成于衬底上。举例来说，第一类型的材料可为金属，例如铜，且第二类型的材料可为半导体层，例如多晶硅的沉积层。在一些现代制造技术中，无法使用多晶硅或电线容易地将NMOS和PMOS栅极直接连接，且因此在此类情况下，必须使用金属层连接此类栅极。在一个可替换例子中，可由单种材料的单个层提供第一导电层和第二导电层。
图9示出先前参考图7描述的备用单元的逻辑栅极900的示例电路布局的示意性平面图。
在图8和图9之间使用对应的参考标号来指示类似组件。逻辑栅极900类似于参考图8所描述的逻辑栅极，这是因为第一作用区域902和第二作用区域904以及第一导电层906、908、914的布置与参考图8中的标准单元所描述的布置相同。同样如在图8的标准单元中，可由多个多晶硅连接(也被称为聚合电线)提供图9中的备用单元的第二导电层。然而，备用单元的逻辑栅极900的第二导电层的布置不同于先前参考图8所描述的标准单元的布置。可通过修改单个层或掩模来实现第二导电层的布置中的这种差异。
相比于标准单元，备用单元的第四导电连接和第五导电连接各自被分为第一子部分916a、918a和第二子部分916b、918b。第四导电连接和第五导电连接的第一子部分916a、918a各自在第一作用区902中的晶体管的栅极与第一电压端VDD之间提供连接。第四和第五导电连接的第一子部分916b、918b各自在第二作用区904中的晶体管的栅极与第二电压端VSS之间提供连接。出于清楚起见，在图9中未示出导电连接与第一电压端VDD和第二电压端VSS之间的连接(其通常由金属线提供)。以此方式，提议的备用单元针对每一聚合电线将驱动NMOS晶体管的片段与驱动PMOS晶体管的片段分离。另外，PMOS驱动的聚合电线片段连到VDD且NMOS驱动的聚合电线片段连到VSS。
图10示出用于制造例如参考图5所描述的集成电路等集成电路的方法100。
方法100包括形成102集成电路衬底。集成电路衬底包括第一电压端(VDD)、第二电压端(VSS)和多个逻辑单元。第一电压端被配置成接收相对于第二电压端的正电压。每个逻辑单元包括具有p型通道的一个或多个场效应晶体管和具有n型通道的一个或多个FET。每个晶体管可具有栅极、源极、漏极和主体端。所述多个逻辑单元包括单元的常规子集和单元的备用子集。
完成方法100的三个后续步骤的次序可变化。后续步骤包括：
●将单元的常规子集与布置提供功能性逻辑布置的一个或多个电连接器连接104；
●使用一个或多个电连接器将单元的备用子集的具有p型通道的一个或多个场效应晶体管的栅极连接106到第一电压端；以及
●使用一个或多个电连接器将单元的备用子集的具有n型通道的一个或多个场效应晶体管的栅极连接108到第二电压端。
可使用蚀刻或研磨(例如，离子束研磨)来实现断开连接。金属迹线或导电迹线可沉积于衬底上以便将单元的至少一个备用子集的场效应晶体管的栅极连接到单元的常规子集的栅极。
图11示出用于修改例如参考图5所描述的集成电路或通过参考图10所描述的方法制造的集成电路等集成电路的方法110。
方法110包括最初接收112集成电路(IC)的任选步骤。集成电路包括具有第一电压端、第二电压端和多个逻辑单元的衬底。第一电压端被配置成接收相对于第二电压端的正电压。每个逻辑单元包括具有p型通道的一个或多个场效应晶体管和具有n型通道的一个或多个FET。每个晶体管可具有栅极、源极、漏极和主体端。所述多个逻辑单元包括单元的常规子集和单元的备用子集。
完成方法110的三个后续步骤的次序可变化。后续步骤包括：
●将备用单元中的至少一个备用子集的具有p型通道的一个或多个场效应晶体管的栅极与第一电压端断开连接114；
●将至少一个备用单元的具有n型通道的一个或多个场效应晶体管的栅极与第二电压端断开连接116；以及
●将单元的至少一个备用子集的场效应晶体管的栅极连接118到单元的常规子集的栅极，以便提供修改的功能性逻辑布置。
电连接器可包括金属迹线或导电迹线。金属迹线或导电迹线可提供于单个层中或多个层中，如参考图9所描述。
除非明确陈述特定次序，否则可以任何次序执行以上图式中的指令和/或流程图步骤。而且，本领域的技术人员将认识到，尽管已经论述一个示例指令集/方法，但是本说明书中的材料可以多种方式组合从而也产生其它例子，并且应在由此详细描述提供的上下文内来理解。
在一些示例实施例中，上文描述的指令集/方法实施为体现为可执行指令集的功能和软件指令，其在计算机或用所述可执行指令编程和控制的机器上实现。此类指令被加载用于在处理器(例如，一个或多个CPU)上执行。术语处理器包括微处理器、微控制器、处理器模块或子系统(包括一个或多个微处理器或微控制器)，或其它控制或计算装置。处理器可以指代单个组件或指代多个组件。
在其它例子中，本文示出的指令集/方法以及与其相关联的数据和指令存储在相应存储装置中，所述存储装置实施为一个或多个非暂时性机器或计算机可读或计算机可用存储媒体。此类计算机可读或计算机可用存储媒体被视为物品(或制品)的一部分。物品或制品可以指代任何所制造的单个组件或多个组件。如本文所限定的非暂时性机器或计算机可用媒体不包括信号，但此类媒体能够接收并处理来自信号和/或其它暂时性媒体的信息。
本说明书中论述的材料的示例实施例可整体或部分通过网络、计算机或基于数据的装置和/或服务来实施。这些可包括云、互联网、内联网、移动装置、台式计算机、处理器、查找表、微控制器、消费者设备、基础架构，或其它使能装置和服务。如本文和权利要求书中可使用，提供以下非排他性限定。
在一个例子中，使本文论述的一个或多个指令或步骤自动化。术语自动化或自动(及其类似变化)意味着使用计算机和/或机械/电气装置的设备、系统和/或过程的受控操作，而不需要人类干预、观测、努力和/或决策。

Claims (8)

1.一种集成电路，其特征在于，包括：
第一电压端（VDD）；
第二电压端（VSS），其中所述第一电压端被配置成接收相对于所述第二电压端的正电压；
多个逻辑单元，每个逻辑单元包括具有p型通道的一个或多个场效应晶体管和具有n型通道的一个或多个场效应晶体管，其中每个晶体管具有栅极，且其中所述多个逻辑单元包括单元的常规子集和单元的备用子集；以及
电连接器，其被配置成：
连接单元的所述常规子集的所述栅极以便提供功能性逻辑布置；
将单元的所述备用子集的具有p型通道的所述一个或多个场效应晶体管的所述栅极连接到所述第一电压端；
将单元的所述备用子集的具有n型通道的所述一个或多个场效应晶体管的所述栅极连接到所述第二电压端；
将单元的所述备用子集中的至少一个备用子集的具有p型通道的所述一个或多个场效应晶体管的所述栅极与所述第一电压端断开连接；
将单元的所述至少一个备用子集的具有n型通道的所述一个或多个场效应晶体管的所述栅极与所述第二电压端断开连接；以及
将单元的所述至少一个备用子集的所述场效应晶体管的所述栅极连接到单元的所述常规子集的所述栅极，以提供修改的功能性逻辑布置。
2.根据权利要求1所述的集成电路，其特征在于，所述电连接器包括金属迹线或导电迹线。
3.根据权利要求2所述的集成电路，其特征在于，所述金属迹线或导电迹线提供于单个层中。
4.根据权利要求1-3中任一项所述的集成电路，其特征在于，每个单元提供逻辑栅极。
5.一种制造集成电路的方法，其特征在于，包括：
形成集成电路衬底，所述集成电路衬底包括：
第一电压端；
第二电压端，其中所述第一电压端被配置成接收相对于所述第二电压端的正电压；
多个逻辑单元，每个逻辑单元包括具有p型通道的一个或多个场效应晶体管和具有n型通道的一个或多个场效应晶体管，其中每个晶体管具有栅极，且其中所述多个逻辑单元包括单元的常规子集和单元的备用子集；
将单元的所述常规子集与布置为提供功能性逻辑布置的一个或多个电连接器连接；
使用一个或多个电连接器将单元的所述备用子集的具有p型通道的所述一个或多个场效应晶体管的所述栅极连接到所述第一电压端；
使用一个或多个电连接器将单元的所述备用子集的具有n型通道的所述一个或多个场效应晶体管的所述栅极连接到所述第二电压端；
使用一个或多个电连接器将单元的所述备用子集中的至少一个备用子集的具有p型通道的所述一个或多个场效应晶体管的所述栅极与所述第一电压端断开连接；
使用一个或多个电连接器将单元的所述至少一个备用子集的具有n型通道的所述一个或多个场效应晶体管的所述栅极与所述第二电压端断开连接；以及
使用一个或多个电连接器将单元的所述至少一个备用子集的所述场效应晶体管的所述栅极连接到单元的所述常规子集的所述栅极，以提供修改的功能性逻辑布置。
6.根据权利要求5所述的方法，其特征在于，所述一个或多个电连接器包括金属迹线或导电迹线。
7.根据权利要求6所述的方法，其特征在于，半导体衬底包括所述多个单元，所述方法包括将所述金属迹线或导电迹线沉积在衬底的表面上。
8.根据权利要求6或7所述的方法，其特征在于，所述金属迹线或导电迹线提供于单个层中。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6925953B2 (ja) 2017-12-22 2021-08-25 ルネサスエレクトロニクス株式会社 半導体装置
US11616053B2 (en) * 2018-09-05 2023-03-28 Tokyo Electron Limited Method to vertically route a logic cell incorporating stacked transistors in a three dimensional logic device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6373291B1 (en) * 1999-09-27 2002-04-16 Kabushiki Kaisha Toshiba Pass transistor logic circuit for reducing power consumption
CN102088027A (zh) * 2009-12-08 2011-06-08 S.O.I.Tec绝缘体上硅技术公司 具有绝缘膜下埋入背控制栅极的SeOI上一致晶体管电路

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004336919A (ja) * 2003-05-09 2004-11-25 Ricoh Co Ltd キャパシタ充電回路およびそれに用いる半導体装置
US7458051B2 (en) 2005-11-17 2008-11-25 Taiwan Semiconductor Manufacturing Co., Ltd. ECO cell for reducing leakage power
KR100769128B1 (ko) * 2005-12-29 2007-10-22 동부일렉트로닉스 주식회사 Ｅｃｏ셀 그리고, ｅｃｏ셀의 배치 및 루팅방법
TWI301631B (en) * 2006-07-21 2008-10-01 Via Tech Inc Integrated circuit with spare cells
US8631383B2 (en) * 2008-06-30 2014-01-14 Qimonda Ag Integrated circuits, standard cells, and methods for generating a layout of an integrated circuit
US20100231256A1 (en) 2009-03-10 2010-09-16 Freescale Semiconductor, Inc Spare cell library design for integrated circuit
TWI571058B (zh) * 2011-05-18 2017-02-11 半導體能源研究所股份有限公司 半導體裝置與驅動半導體裝置之方法
US8810280B2 (en) * 2011-10-06 2014-08-19 Oracle International Corporation Low leakage spare gates for integrated circuits
US9431353B2 (en) * 2014-04-09 2016-08-30 Infineon Technologies Ag Method for manufacturing a digital circuit and digital circuit
US9154135B1 (en) 2014-04-27 2015-10-06 Freescale Semiconductor, Inc. Spare gate cell for integrated circuit
US9515077B1 (en) * 2015-12-18 2016-12-06 Taiwan Semiconductor Manufacturing Co., Ltd. Layout of static random access memory cell

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6373291B1 (en) * 1999-09-27 2002-04-16 Kabushiki Kaisha Toshiba Pass transistor logic circuit for reducing power consumption
CN102088027A (zh) * 2009-12-08 2011-06-08 S.O.I.Tec绝缘体上硅技术公司 具有绝缘膜下埋入背控制栅极的SeOI上一致晶体管电路

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