CN107452353B

CN107452353B - Time schedule controller and display device

Info

Publication number: CN107452353B
Application number: CN201710772491.5A
Authority: CN
Inventors: 琳琳; 王月; 刘洪海; 阮永鑫
Original assignee: InfoVision Optoelectronics Kunshan Co Ltd
Current assignee: InfoVision Optoelectronics Kunshan Co Ltd
Priority date: 2017-08-31
Filing date: 2017-08-31
Publication date: 2020-09-29
Anticipated expiration: 2037-08-31
Also published as: CN107452353A

Abstract

The application discloses time schedule controller and display device, this time schedule controller includes: the time sequence control module is used for providing a control signal; and the hot plug signal generation module is used for receiving the control signal and generating a hot plug signal according to the control signal and the reset state of the time sequence control module, so that the hot plug signal keeps an initial potential during the reset operation of the time sequence control module, and the hot plug signal jumps from the initial potential to an activation potential when the time sequence control module finishes the reset operation. The time sequence control module in the time sequence controller can carry out reset operation on the basis of not influencing normal functions and normal activation of a link between the time sequence control module and a front-end system.

Description

Time schedule controller and display device

Technical Field

The present invention relates to the field of liquid crystal display devices, and more particularly, to a timing controller and a display device.

Background

In the prior art, in order to restore normal display of the liquid crystal display device as soon as possible, when the timing controller performs the reset operation, the timing controller sends a hot plug signal to the front-end system to notify the front-end system to train the link again, which is about ten and several ms, so that the liquid crystal display device has bad display in this period of time, which affects the viewing effect.

Disclosure of Invention

In view of the foregoing, it is an object of the present invention to provide a timing controller and a display device, in which a timing control module can perform a reset operation without affecting a normal function and a normal activation of a link with a front end system.

According to an aspect of the present invention, there is provided a timing controller including: the time sequence control module is used for providing a control signal; and the hot plug signal generation module is used for receiving the control signal and generating a hot plug signal according to the control signal and the reset state of the time sequence control module, so that the hot plug signal keeps an initial potential during the reset operation of the time sequence control module, and the hot plug signal jumps from the initial potential to an activation potential when the time sequence control module finishes the reset operation.

Preferably, the hot plug signal generating module comprises: the control module is used for generating an interrupt request signal and an auxiliary control signal; an OR gate having a first input for receiving the control signal and a second input for receiving the auxiliary control signal; and the first input end of the AND gate is electrically connected with the output end of the OR gate, the second input end of the AND gate is used for receiving the interrupt request signal, and the output end of the AND gate is used for outputting the hot plug signal.

Preferably, when the timing controller is in an initial state, the auxiliary control signal is at a low level, and the interrupt request signal is at a high level.

Preferably, when the timing control module starts to reset, the interrupt request signal is at a high level, the auxiliary control signal is at a high level, when the timing control module finishes resetting, the auxiliary control signal jumps from the high level to the low level, and the interrupt request signal jumps from the high level to the low level.

Preferably, the initial level is a high level and the activation potential is a low level.

Preferably, the control module comprises a Micro Control Unit (MCU), a programmable logic array (FPGA), a system on chip (SoC) or an Application Specific Integrated Circuit (ASIC).

According to another aspect of the present invention, there is provided a display device including: a video output device having a transmitting end; and the time schedule controller as described above, wherein a hot plug detection channel is provided between the sending end and the time schedule controller, and the time schedule controller provides a hot plug detection signal for the sending end via the hot plug detection channel.

Preferably, the sender is a sender of an eDP interface.

According to the time sequence controller provided by the embodiment of the invention, when the time sequence control module is reset, the time sequence controller does not provide an effective hot plug signal for the front-end system, but activates the link by adopting the interrupt request signal after the time sequence control module completes the reset operation, so that bad display for a period of time caused by retraining the link is avoided, and the display effect is optimized.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

Fig. 1 shows a circuit diagram of a timing controller according to a first embodiment of the present invention.

Fig. 2a illustrates a timing diagram of an initialization process of the timing controller shown in fig. 1.

Fig. 2b is a timing diagram illustrating a reset operation performed by a timing control block in the timing controller shown in fig. 1.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown.

In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

The present invention may be embodied in various forms, some examples of which are described below.

As shown in fig. 1, the timing controller 100 according to the embodiment of the present invention includes a timing control module 110 and a hot plug signal generating module 120, wherein the timing control module 110 is configured to generate a control signal HPD _ T, and the hot plug signal generating module 120 is configured to receive the control signal HPD _ T and generate a hot plug signal HPD.

The hot plug signal generating module 120 includes a programmable module 121, an OR gate OR, AND gate AND. The programmable module 121 is configured to provide an auxiliary signal M AND an interrupt request signal HPD _ M, a first input terminal of the OR gate OR receives the control signal HPD _ T, a second input terminal of the OR gate OR receives the auxiliary control signal M, a first input terminal of the AND gate AND is electrically connected to an output terminal of the OR gate OR, a second input terminal of the AND gate AND receives the interrupt request signal HPD _ M, AND an output terminal of the OR gate OR is configured to provide the hot plug signal HPD.

In this embodiment, the programmable module 121 is, for example, a micro control unit MCU, and in a further alternative embodiment, the programmable module 121 is any one selected from a programmable logic array FPGA, a system on a chip SoC, and an application specific integrated circuit ASIC.

As shown in fig. 2a, at time a, the timing controller performs an initialization operation, the auxiliary control signal M is set to a low level, the interrupt request signal HPD _ M is set to a high level, and at time b, the control signal HPD _ T jumps from the low level to the high level, as can be seen from fig. 1, at which time the hot plug signal HPD follows the control signal HPD _ T, i.e., at time b, the hot plug signal HPD also jumps from the low level to the high level.

As shown in fig. 2b, when the timing control module 110 in the timing controller is going to perform the reset operation, the auxiliary control signal M jumps from low level to high level, and as can be seen from fig. 1, at the time a, when the auxiliary control signal M jumps from low level to high level, the control of the hot plug signal HPD by the timing control module 110 is masked. Next, the timing control module 110 starts a reset operation, when the programmable module 121 determines that the timing control module 110 has completed the reset operation according to the pre-written data, that is, at the time b, the programmable module 121 controls the interrupt request signal HPD _ M to jump from the high level to the low level, and the time for which the interrupt request signal HPD _ M is kept at the low level is, for example, 0.5 to 1ms, and then, the programmable module 121 controls the auxiliary control signal M to jump from the high level to the low level, and correspondingly, the hot plug signal HPD to jump from the high level to the low level at the time b, so as to complete the activation of the front-end system link.

A second embodiment of the present invention provides a display device, which includes a video output device having a sender and the timing controller provided in the first embodiment of the present invention, where the video output device sends a video data stream corresponding to a video image to the timing controller in units of frames through the sender, where the video data is sent through a main link of the sender, and a control command and a status report are transmitted through an auxiliary link of the sender, where a hot plug detection channel is further included between the sender and the timing controller, and the timing controller transmits a hot plug detection signal to the sender through the channel.

Compared with the prior art, in the time sequence controller provided by the embodiment of the invention, when the time sequence control module is subjected to reset operation, the time sequence controller does not provide an effective hot plug signal for the front-end system, but activates the link by adopting the interrupt request signal after the time sequence control module finishes the reset operation, so that bad display for a period of time caused by retraining the link is avoided, and the display effect is optimized.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching, including but not limited to alterations to the local configuration of the circuit, and substitutions of types or models of components. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A timing controller, comprising:

the time sequence control module is used for providing a control signal; and

a hot plug signal generating module for receiving the control signal and generating a hot plug signal according to the control signal and a reset state of the timing control module, so that the hot plug signal maintains an initial potential during a reset operation of the timing control module, and jumps from the initial potential to an active potential when the timing control module completes the reset operation,

wherein the hot plug signal generation module comprises a hot plug signal generation module,

the control module is used for generating an interrupt request signal and an auxiliary control signal;

an OR gate having a first input for receiving the control signal and a second input for receiving the auxiliary control signal; and

the first input end of the AND gate is electrically connected with the output end of the OR gate, the second input end of the AND gate is used for receiving the interrupt request signal, the output end of the AND gate is used for outputting the hot plug signal,

when the time sequence control module is reset, the interrupt request signal is at a high level, the auxiliary control signal is at a high level, the hot plug signal is irrelevant to the control signal, and the time sequence control module is shielded from controlling the hot plug signal; when the time sequence control module is reset, the auxiliary control signal is changed from high level to low level, the interrupt request signal is changed from high level to low level, and the hot plug signal is changed from high level to low level, so that the front-end system link is activated.

2. The timing controller of claim 1, wherein the auxiliary control signal is low and the interrupt request signal is high when the timing controller is in an initial state.

3. The timing controller of claim 1, wherein the initial potential is high and the activation potential is low.

4. The timing controller of claim 1, wherein the control module comprises a Micro Control Unit (MCU), a programmable logic array (FPGA), a system on a chip (SoC), or an Application Specific Integrated Circuit (ASIC).

5. A display device, comprising:

a video output device having a transmitting end; and

the timing controller of any one of claims 1 to 4,

the system comprises a sending end, a time schedule controller and a time schedule controller, wherein a hot plug detection channel is arranged between the sending end and the time schedule controller, and the time schedule controller provides a hot plug detection signal for the sending end through the hot plug detection channel.

6. The display apparatus according to claim 5, wherein the sender is a sender of an eDP interface.