CN107451361B

CN107451361B - Circuit ID generation method

Info

Publication number: CN107451361B
Application number: CN201710639133.7A
Authority: CN
Inventors: 聂廷远; 马君玉; 高久顼; 王培培
Original assignee: Qingdao University of Technology
Current assignee: Qingdao University of Technology
Priority date: 2017-07-31
Filing date: 2017-07-31
Publication date: 2020-05-05
Anticipated expiration: 2037-07-31
Also published as: CN107451361A

Abstract

The invention discloses a circuit ID generation method, which comprises the following specific steps: (1) firstly, obtaining the physical design of the circuit to be identified, and extracting circuit description information: circuit name, circuit functional description, macroblock (macro) percentage; (2) generating a complex network description matrix according to the elements (or functional modules) in the circuit file and the connection relation between the elements (or functional modules), and extracting complex network characteristic parameters from the complex network description matrix: network average degree, network total node number, network total edge number, network average shortest path and network average aggregation coefficient; (3) fusing the circuits obtained in the step 1 and the step 2 with the complex network information to generate a circuit description character string; (4) performing one-way encryption function processing on the circuit description character string obtained in the step 3 to obtain an information abstract; (5) the information abstract (binary information) obtained in the step 4 is the circuit ID; the invention has the advantages of universality, strong circuit identification capability, high safety and the like.

Description

Circuit ID generation method

Technical Field

The invention relates to a circuit ID generation method.

Background

With the continuous development and progress of semiconductor and integrated technology, System On Chip (SOC) has become the main development direction of very large scale integrated circuit design, and Integrated Circuits (IC) have been widely used in various electronic devices. In real world applications, integrated circuit identification and verification are necessary to protect the intellectual property of the integrated circuit designer/owner.

Disclosure of Invention

The present invention is directed to a circuit ID generation method for identifying and verifying an integrated circuit, so as to reduce intellectual property disputes that may infringe designers/owners of the integrated circuit.

In order to achieve the purpose, the invention adopts the technical scheme that:

a circuit ID generation method comprises the following specific steps:

1. firstly, obtaining the physical design of a circuit to be identified, and extracting circuit description information: circuit name, circuit functional description, macroblock (macro) percentage;

2. generating a complex network description matrix according to the elements (or functional modules) in the circuit file and the connection relation between the elements (or functional modules), and extracting complex network characteristic parameters from the complex network description matrix: network average degree, network total node number, network total edge number, network average shortest path and network average aggregation coefficient;

3. fusing the circuits obtained in the step 1 and the step 2 with the complex network information to generate a circuit description character string;

4. performing one-way encryption function processing on the circuit description character string obtained in the step 3 to obtain an information abstract;

5. the digest of information (binary information) obtained in step 4 is the circuit ID.

The invention provides a circuit ID generation method based on a circuit and a corresponding complex network thereof, which comprises the following steps of firstly obtaining description information of the circuit: circuit name, and circuit function description, macroblock (macro) percentage. Then generating a complex network description matrix of the circuit to be identified, and calculating the complex network characteristic parameters from the complex network description matrix: network average degree, total network edge number, total network node number, average shortest network path and average network aggregation coefficient. And fusing the obtained circuit description information and the complex network characteristic information, and finally obtaining a circuit ID through one-way encryption function processing. The circuit ID generated by the method has low collision probability and high safety.

After adopting the structure, the invention has the beneficial effects that:

1. the method for generating the circuit ID can be applied to the whole circuit or a certain circuit module, and can extract circuit description information and complex network characteristic information of integrated circuit description data files (in formats such as HDL (high density hardware description) format, netlist format and layout format and the like) under different design methods and different processes.

2. The circuit identification capability is strong, the circuit description character string generated by the invention comprises circuit information and corresponding complex network information, and different integrated circuit description character strings have larger difference.

3. The safety is high, the circuit ID is obtained by utilizing the one-way encryption function processing, the collision probability is low, and therefore the safety is high.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a flow chart of the circuit ID generation process in the present invention;

FIG. 2 is a flow chart of the present invention for extracting circuit description information using circuit physical design;

fig. 3 is a flow chart of extracting complex network characteristic parameters in the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings and the detailed description. It should be understood that the detailed description and specific examples, while indicating the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.

As shown in fig. 1, a circuit ID generation method according to this embodiment includes the following steps:

(1) acquiring the physical design of a circuit to be identified, and extracting description information of the circuit;

as shown in fig. 2, fig. 2 extracts circuit description information for the process of obtaining the physical design of the circuit to be identified: circuit name, circuit functional requirements, macro percentage.

(2) And generating a complex network description matrix of the circuit to be identified, and calculating the characteristic parameters of the complex network.

As shown in fig. 3, in the process of obtaining the characteristic information of the complex network of the circuit shown in fig. 3, an element or a functional module in the circuit is equivalent to a node, a complex network description matrix is generated according to a connection relationship between the nodes, and a complex network characteristic parameter is extracted from the complex network description matrix: network average degree, network total node number, network total edge number, network average shortest path, network average aggregation coefficient and the like.

(3): fusing the circuit obtained in the step (1) and the step (2) with complex network information to obtain a circuit description character string;

(4): and (4) performing one-way encryption function processing on the circuit description character string obtained in the step (3) to obtain a corresponding binary information abstract.

(5): (4) the obtained binary information abstract is the circuit ID.

The specific embodiment provides a circuit ID generation method based on a circuit and a corresponding complex network thereof, and firstly, description information of the circuit is obtained: circuit name, and circuit function description, macroblock (macro) percentage. Then generating a complex network description matrix of the circuit to be identified, and calculating the complex network characteristic parameters from the complex network description matrix: network average degree, total network edge number, total network node number, average shortest network path and average network aggregation coefficient. And fusing the obtained circuit description information and the complex network characteristic information, and finally obtaining a circuit ID through one-way encryption function processing. The circuit ID generated by the method has low collision probability and high safety.

Example 1:

the present embodiment provides a circuit ID generation method, which is to identify a circuit before an IC design is released to avoid disputes in intellectual property rights of the circuit, and generate an ID of the circuit by the above steps. When IC design verification is needed, the IDs of the two circuits are compared, the possibility that the circuits are stolen can be preliminarily judged, a basis is provided for copyright ownership of the integrated circuits, and certain convenience is achieved.

In the embodiment, after circuit information and complex network information are fused, a circuit description character string is obtained, and an ID of a description circuit is obtained after the circuit description character string is processed by a one-way encryption function. The method has the characteristics of universality, strong circuit identification capability, high safety and the like

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. A circuit ID generation method characterized by: the method comprises the following specific steps:

(1) firstly, obtaining the physical design of the circuit to be identified, and extracting circuit description information: circuit name, circuit function description, macro percentage of macro;

(2) complex network information: generating a complex network description matrix according to elements or functional modules in the circuit file and the connection relation between the elements or the functional modules, and extracting complex network characteristic parameters from the complex network description matrix: network average degree, network total node number, network total edge number, network average shortest path and network average aggregation coefficient;

(3) fusing the circuit description information with the complex network characteristic parameters in the complex network information to generate a circuit description character string;

(4) and performing one-way encryption function processing on the circuit description character string to obtain a corresponding binary information abstract, wherein the binary information abstract is the circuit ID.