CN107436962A - A kind of radioresistance layout design method of integrated circuit - Google Patents
A kind of radioresistance layout design method of integrated circuit Download PDFInfo
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- CN107436962A CN107436962A CN201610367157.7A CN201610367157A CN107436962A CN 107436962 A CN107436962 A CN 107436962A CN 201610367157 A CN201610367157 A CN 201610367157A CN 107436962 A CN107436962 A CN 107436962A
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- traps
- circuit
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- memory cell
- memory element
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
Abstract
The invention belongs to integrated circuit fields, are related to a kind of radiation-hardened ic layout design method based on isolation N traps and memory cell.The present invention is in circuit layout design, the distance between the N traps of non-memory element circuit and memory cell is set to be more than or equal to preassigned most short license distance, there is the isolated area between the N traps of non-memory element circuit and memory cell to be occupied by nmos pass transistor more than or equal to the region for preassigning minimum area, the area of non-memory element circuit N traps is less than or equal to preassigned maximum license area.The layout design method of the present invention can avoid a large amount of electronics of nmos pass transistor source electrode in storage unit circuit from flowing to drain electrode through substrate P and produce larger leakage current, so that circuit has radioresistance characteristic.
Description
Technical field
The invention belongs to integrated circuit fields, it is related to a kind of radioresistance layout design method of integrated circuit, and in particular to
A kind of radiation-hardened ic layout design method based on isolation N traps and memory cell.
Background technology
Data is disclosed in technical field of integrated circuits, and with the reduction of process, the integrated circuit in chip exists
High-rise space or near-earth spherical space, which becomes increasingly susceptible to heavy particle or proton irradiation, to be influenceed and produces mistake.Studies have shown that spoke
If penetrating influences the memory node of memory cell, memory cell storage erroneous values may be directly resulted in, produce single-particle inversion
Event；If radiation influences combinational circuit node, single event transient pulse may be caused, change the logic state of circuit node,
Improper value caused by the single event transient pulse is transmitted to memory cell and understands the storage that may also be captured, and produces single-particle inversion thing
Part.So single event upset can change the logic state of memory cell storage, integrated circuit capability error may be caused.Cause
This, this area needs to propose about supporting radiation-resistant method of designing integrated circuit.
At present, the design method of radiation hardened integrated circuit mainly includes multi-mode redundant, error correcting code and radiation hardening technology
Deng.Wherein, multi-mode redundant method is shielded wrong using triplication redundancy technology as representative using redundant circuit module and majority voter
The output of circuit module by mistake, but this method can bring very big area overhead；Error correction code approach passes through using Hamming code as representative
The check value of calculation code, the position of Wrong localization bit；Radiation hardening technology using double interlock memory cell as representative,
Increase extra transistor and mutually twisted interconnection line on the basis of basic unit of storage structure, strengthen the radioresistance of sensitive nodes
Ability, but error correcting code and radiation hardening technology can bring larger area overhead, and reduce circuit performance.
Present situation based on prior art, present inventor intend providing a kind of anti-based on isolation N traps and memory cell
Raddiating circuit layout design method, the defects of to overcome prior art to exist, avoid nmos pass transistor source in storage unit circuit
A large amount of electronics of pole flow to drain electrode through substrate P and produce larger leakage current, circuit is had radioresistance characteristic.
Bibliography related to the present invention has：
[1] Baumann R.Soft Errors in Advanced Computer Systems [J], IEEE
Transactions on Device and Materials Reliability, 2005,22 (3), pp.258-266
[2] Oliveira R., Jagirdar A., Chakraborty T.J.：A TMR Scheme for SEU
Mitigation in Scan Flip-Flops [C], in International Symposium on Quality
Electronic Design, 2007, pp.905-910
[3] Tausch H.J.Simplified Birthday Statistics and Hamming EDAC [J], IEEE
Transactions on Nuclear Science, 2009,56 (2), pp.474-478
[4] Calin T., Nicolaidis M., Velazco R.Upset hardened memory design for
Submicron CMOS technology [J], IEEE Transactions on Nuclear Science, 1996,43 (6),
pp.2874-2878
[5] S.Yang.Logic Synthesis and Optimization Benchmarks User Guide,
Research Triangle Park, NC：Microelectronics Center of North Carolina (MCNC),
1991
The content of the invention
The purpose of the present invention is to be directed to technological deficiency existing for integrated circuit fields, there is provided a kind of radioresistance of integrated circuit
A kind of layout design method, and in particular to radiation-hardened ic layout design method based on isolation N traps and memory cell.
Specifically, the present invention circuit layout design in, make between the N traps of non-memory element circuit and memory cell away from
With a distance from more than or equal to preassigned most short license, make the isolated area between the N traps of non-memory element circuit and memory cell
There is the region more than or equal to predesignated minimum area by NMOS (Negative channel Metal Oxide
Semiconductor) transistor occupies, and the area of non-memory element circuit N traps is permitted less than or equal to preassigned maximum
Can area.The N traps of non-memory element circuit can produce unnecessary hole after being radiated, and these unnecessary holes drift about into after substrate P,
The PN junction forward bias that substrate P may be caused to be formed with nmos pass transistor source electrode in storage unit circuit, causes memory cell
A large amount of electronics of nmos pass transistor source electrode are flowed to through substrate P and drained in circuit, produce larger leakage current, cause data storage wrong
By mistake.The layout design method of the present invention can avoid a large amount of electronics of nmos pass transistor source electrode in storage unit circuit through substrate P stream
To drain electrode, so that circuit has radioresistance characteristic.
More specifically, a kind of radiation-hardened ic layout design method based on isolation N traps and memory cell of the invention, its
Including following two steps, it is described in detail separately below.
Step 1：Using traditional circuit emulation or method of testing, determine between the N traps of non-memory element circuit and memory cell
Most short license distance, the nmos pass transistor between non-memory element circuit N traps and memory cell in isolated area should occupy most
The maximum license area of small area, non-memory element circuit N traps；
Using traditional circuit simulation or method of testing, to non-memory unit under specified process conditions and radiation intensity
The N traps of circuit are radiated, it is determined that radiation will not cause memory cell stored data the non-memory element circuit N traps of mistake occur
Nmos pass transistor should in isolated area between most short license distance, non-memory element circuit N traps and memory cell between memory cell
The maximum license area of the minimum area occupied, non-memory element circuit N traps.Fig. 1 shows, the N of a non-memory unit
Trap and a memory cell are all in substrate P, and N traps width and length are respectively W and L, and the distance between N traps and memory cell is D,
High energy particles Radiation can produce unnecessary hole after hitting the N traps of non-memory unit, and these unnecessary holes can drift about into substrate P,
The PN junction forward bias that substrate P may be caused to be formed with nmos pass transistor source electrode in storage unit circuit, causes memory cell
A large amount of electronics of nmos pass transistor source electrode are flowed into substrate P in circuit, and which part electronics passes through substrate P and storage unit circuit
Collected after the reverse biased PN junction that middle nmos transistor drain is formed by nmos transistor drain, produce larger leakage current, can
Data storage mistake (nmos pass transistor in memory cell is not drawn in Fig. 1) can be caused, N trap areas are smaller, because radiation produces
Unnecessary hole it is fewer, the distance between N traps and memory cell is longer, and more unnecessary holes can not reach adjoining memory cell, N
Nmos pass transistor footprint area is bigger in isolated area between trap and memory cell, and more unnecessary holes can be stopped by nmos pass transistor
Neutralize, so, unnecessary hole caused by radiation is just difficult to cause substrate P and nmos pass transistor source electrode institute structure in storage unit circuit
Into PN junction forward bias, a large amount of electronics for avoiding nmos pass transistor source electrode in storage unit circuit flow to substrate P and are leaked again
Pole is collected, so as to greatly reduce leakage current.Therefore, when the distance D between N traps and memory cell be more than or equal to most it is short license away from
From M, N trap width W be less than or equal to most long license width N (assuming that N trap length L is constant, can only adjustment width W, it means that N
Trap area is less than or equal to maximum license area N × L), multiple nmos pass transistors at least account in isolated area between N traps and memory cell
When permitting area according to minimum, because unnecessary hole caused by radiation is difficult the isolated area through between N traps and memory cell in N traps, so as to
Make circuit that there is radioresistance characteristic.In Fig. 1 between N traps and memory cell most short most long license width N, N trap of license distance M, N trap with
The minimum area that multiple nmos pass transistors should occupy between memory cell can be by above-mentioned traditional channel radiation emulation or test side
Method determines；
Step 2：Circuit layout is designed, is more than or equal to the distance between the N traps of non-memory element circuit and memory cell
The most short license distance determined in step 1, make the nmos pass transistor in isolated area between non-memory element circuit N traps and memory cell
Occupy more than or equal to the minimum area determined in step 1, the area of non-memory element circuit N traps is less than or equal to step 1
The maximum license area of middle determination；
Step 2.1, step 2.2, step 2.3, step 2.4, step 2.5 are performed by below scheme；
In step 2.1, circuit layout is designed by traditional layout design method, then performs step 2.2；
In step 2.2, the memory cell in identification circuit domain, non-memory element circuit N traps and memory cell are calculated
Between distance, if the distance of N traps and memory cell is less than the most short license distance that determines in step 1, returns to step 2.1 and adjust
Justifying G- Design, increase the distance between N traps and memory cell, be allowed to be more than or equal in step 1 the most short license distance determined,
If the distance of N traps and memory cell is more than or equal in step 1 the most short license distance determined, step 2.3 is performed；
In step 2.3, nmos pass transistor is inserted in region between non-memory element circuit N traps and memory cell, makes NMOS
Transistor is occupied more than or equal to the minimum area determined in step 1, then performs step 2.4；
In step 2.4, the area of non-memory element circuit N traps is calculated, if N traps area is more than what is determined in step 1
Maximum license area, then step 2.1 adjustment layout design is returned to, reduce N traps area (such as reducing N traps width), be less than
Or equal to the maximum license area determined in step 1, if N traps area is less than or equal in step 1 the maximum license face determined
Product, then perform step 2.5；
In step 2.5, layout design rules inspection is traditionally performed, if there is conflict, then returns to step 2.1
Layout design is adjusted, if do not conflicted, radioresistance layout design is completed.
The present invention has carried out experiment test, as a result shows, layout design method of the invention can avoid storage unit circuit
A large amount of electronics of middle nmos pass transistor source electrode are flowed to through substrate P and drained, so that circuit has radioresistance characteristic.
The present invention has advantages below：
(1) the radiation-hardened ic layout design method proposed by the present invention based on isolation N traps and memory cell, passes through increase
Nmos pass transistor area between distance and N traps and memory cell between N traps and memory cell, N trap areas are reduced, make circuit that there is anti-spoke
Penetrate characteristic；
(2) present invention does not change memory cell structure and combinational circuit structure, does not increase number of memory cells or adds it
His redundant circuit, so area overhead very little；
(3) test experiments result shows, this method can not only strengthen the capability of resistance to radiation of unguyed circuit, can also enter
One step improves the capability of resistance to radiation for having reinforced circuit.
In order to make it easy to understand, the present invention will be described in detail by specific drawings and examples below.Need
It is emphasized that instantiation and accompanying drawing are merely to explanation, it is clear that one of ordinary skill in the art can be according to herein
Illustrate, make various modifications and variations to the present invention within the scope of the invention, these modifications and variations also include this
In the range of invention.In addition, the present invention refer to open source literature, these documents be in order to more clearly describe the present invention, they
Entire contents include and referred to herein, just look like that repeated description herein has been excessively for their full text.
Brief description of the drawings：
Fig. 1 is the radioresistance layout design schematic diagram of the present invention.
Embodiment
Embodiment 1
By two steps of the inventive method：
It is right under specified process conditions and radiation intensity using traditional circuit simulation or method of testing in step 1)
The N traps of non-memory element circuit are radiated, it is determined that radiation will not cause memory cell stored data the non-memory of mistake occur
Between most short license distance, the N traps of non-memory element circuit and memory cell between element circuit N traps and memory cell in isolated area
The maximum license area of minimum area that nmos pass transistor should occupy, non-memory element circuit N traps；
In step 2), step 2.1, step 2.2, step 2.3, step 2.4, step 2.5 are performed by below scheme；
In step 2.1, circuit layout is designed by traditional layout design method, then performs step 2.2；
In step 2.2, the memory cell in identification circuit domain, non-memory element circuit N traps and memory cell are calculated
Between distance, if the distance of N traps and memory cell is less than the most short license distance that determines in step 1, returns to step 2.1 and adjust
Justifying G- Design, increase the distance between N traps and memory cell, be allowed to be more than or equal in step 1 the most short license distance determined,
If the distance of N traps and memory cell is more than or equal in step 1 the most short license distance determined, step 2.3 is performed；
In step 2.3, nmos pass transistor is inserted in region between non-memory element circuit N traps and memory cell, makes NMOS
Transistor is occupied more than or equal to the minimum area determined in step 1, then performs step 2.4；
In step 2.4, the area of non-memory element circuit N traps is calculated, if N traps area is more than what is determined in step 1
Maximum license area, then step 2.1 adjustment layout design is returned to, N trap areas is reduced, such as reduces N trap width, be less than or wait
The maximum license area determined in step 1, if N traps area is less than or equal in step 1 the maximum license area determined,
Perform step 2.5；
In step 2.5, layout design rules inspection is traditionally performed, if there is conflict, then returns to step 2.1
Layout design is adjusted, if do not conflicted, radioresistance layout design is completed；
Following experiment is performed, to test its capability of resistance to radiation and area overhead：
(1) in the first experiment, first using Traditional Man layout design method to reference circuit bigkey, dsip,
S38417, S13207.1, S15850.1, S38584.1 carry out circuit layout design, then again using the present invention to the circuit version
Figure is modified adjustment, strengthens its capability of resistance to radiation.Test result shows, compared with Traditional Man layout design method, this hair
It is bright that radiosensitivity index SEU cross section value 78% is averagely reduced with 5% additional areas expense；
(2) in second of experiment, radiation hardening is carried out using triplication redundancy scheme to said reference circuit first and set
Meter, circuit layout design is then carried out to the reference circuit after reinforcing using Traditional Man layout design method, finally used again
Adjustment of the invention of being modified to the circuit layout, strengthens its capability of resistance to radiation.Test result shows, is set with Traditional Man domain
Meter method is compared, and the present invention averagely reduces SEU cross section value 35% with 2% additional areas expense；
(3) in the third experiment, anti-spoke is carried out using double interlock memory cell scheme to said reference circuit first
Design of Reinforcement is penetrated, circuit layout design is then carried out to the reference circuit after reinforcing using the artificial G- Design method of traditional version, most
Its capability of resistance to radiation is strengthened using adjustment of the invention of being modified to the circuit layout again afterwards.Test result shows, with traditional people
Work layout design method is compared, and the present invention averagely reduces SEU cross section value 33% with 3% additional areas expense.
Above-mentioned three kinds of test experiments results show that the present invention, not only can be with larger enhancing not with the area overhead of very little
The capability of resistance to radiation of circuit is reinforced, further larger raising can also reinforce the capability of resistance to radiation of circuit.
Claims (4)
1. the radioresistance layout design method of a kind of integrated circuit, it is characterised in that this method is single with storage based on isolation N traps
The radiation-hardened ic layout design side of member, it includes：In circuit layout design, make N traps and the storage of non-memory element circuit
Distance between unit is more than or equal to preassigned most short license distance, makes the N traps and memory cell of non-memory element circuit
Between isolated area have more than or equal to preassign minimum area region occupied by nmos pass transistor, make non-memory element circuit
The area of N traps is less than or equal to preassigned maximum license area.
2. the radioresistance layout design method of the integrated circuit as described in claim 1, it is characterised in that it includes step：
Step 1：Using traditional circuit emulation or method of testing, determine between the N traps of non-memory element circuit and memory cell most
The minimal face that nmos pass transistor between short license distance, non-memory element circuit N traps and memory cell in isolated area should occupy
The maximum license area of product, non-memory element circuit N traps；
Step 2：Circuit layout is designed, the distance between the N traps of non-memory element circuit and memory cell is more than or equal to step 1
The most short license distance of middle determination, occupies the nmos pass transistor between non-memory element circuit N traps and memory cell in isolated area
More than or equal to the minimum area determined in step 1, the area of non-memory element circuit N traps is set to be less than or equal in step 1 really
Fixed maximum license area.
3. the method as described in claim 1, it is characterised in that in described step 1), using traditional circuit simulation or survey
Method for testing, the N traps of non-memory element circuit are radiated under specified process conditions and radiation intensity, it is determined that radiation will not
Cause memory cell stored data occur mistake non-memory element circuit N traps and memory cell between it is most short license distance, it is non-
Nmos pass transistor should occupy in isolated area between the N traps and memory cell of storage unit circuit minimum area, non-memory unit
The maximum license area of circuit N traps.
4. the method as described in claim 1, it is characterised in that in described step 2), by below scheme perform step 2.1,
Step 2.2, step 2.3, step 2.4, step 2.5；
In step 2.1, circuit layout is designed by traditional layout design method, then performs step 2.2；
In step 2.2, the memory cell in identification circuit domain, calculate between non-memory element circuit N traps and memory cell
Distance, if the distance of N traps and memory cell is less than the most short license distance determined in step 1, return to step 2.1 adjustment version
G- Design, increase the distance between N traps and memory cell, be allowed to be more than or equal in step 1 the most short license distance determined, if
The distance of N traps and memory cell is more than or equal in step 1 the most short license distance determined, then performs step 2.3；
In step 2.3, nmos pass transistor is inserted in region between non-memory element circuit N traps and memory cell, makes NMOS crystal
Pipe is occupied more than or equal to the minimum area determined in step 1, then performs step 2.4；
In step 2.4, the area of non-memory element circuit N traps is calculated, if N traps area is more than the maximum determined in step 1
Permit area, then return to step 2.1 adjustment layout design, reduce N trap areas, such as reduce N trap width, be less than or equal to step
The maximum license area determined in rapid 1, if N traps area is less than or equal in step 1 the maximum license area determined, perform
Step 2.5；
In step 2.5, layout design rules inspection is traditionally performed, if there is conflict, then step 2.1 is returned to and adjusts
Layout design, if do not conflicted, radioresistance layout design is completed.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110676252A (en) * | 2019-09-12 | 2020-01-10 | 北京时代民芯科技有限公司 | Integrated circuit layout structure with reinforced instantaneous radiation resistance |
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| CN104885220A (en) * | 2012-11-27 | 2015-09-02 | 吉林克斯公司 | An integrated circuit having improved radiation immunity |
| CN105468798A (en) * | 2014-09-02 | 2016-04-06 | 复旦大学 | Anti-radiation placing and routing method for integrated circuits |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110676252A (en) * | 2019-09-12 | 2020-01-10 | 北京时代民芯科技有限公司 | Integrated circuit layout structure with reinforced instantaneous radiation resistance |
| CN110676252B (en) * | 2019-09-12 | 2022-05-13 | 北京时代民芯科技有限公司 | Integrated circuit layout structure with reinforced instantaneous radiation resistance |
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Application publication date: 20171205 |