CN107426076B - Electronic equipment, information processing method and information transmission method - Google Patents
Electronic equipment, information processing method and information transmission method Download PDFInfo
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- CN107426076B CN107426076B CN201710584847.2A CN201710584847A CN107426076B CN 107426076 B CN107426076 B CN 107426076B CN 201710584847 A CN201710584847 A CN 201710584847A CN 107426076 B CN107426076 B CN 107426076B
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Abstract
The invention discloses an electronic device, an information processing method and an information transmission method, wherein a ring topology connection structure is adopted, so that in the process of receiving and transmitting data signals, a digital identifier is correspondingly increased or decreased once when data passes through a processing module in the ring topology structure, the processing module for specifically receiving the data signals can be determined through the digital identifier, and a main control device can determine which processing module in the ring topology structure the received data signals specifically come from through the digital identifier. Moreover, after the plurality of processing modules adopt the connection structure in the embodiment of the application, the signal transmission path is not branched, a large number of signal connection lines are not required to be added, and the number of the added slave devices is not limited, so that the technical effects of reducing the wiring layout difficulty of the antenna signal processing system, improving the signal transmission integrity and being not limited by the number of the slave devices are achieved.
Description
Technical Field
The present invention relates to the field of electronic technologies, and in particular, to an electronic device, an information processing method, and an information transmission method.
Background
Currently, in a beam control system of a phased array antenna, a field programmable logic device FPGA needs to control a plurality of digital-to-analog conversion chips (DACs) simultaneously. Because the working environment of the phased array antenna is generally severe and the application space is very limited, a topological structure which is stable and reliable in data transmission and occupies a small number of pins is needed to realize interconnection between chips.
The following two chip connection topologies exist in the prior art:
one is star topology interconnection, in which an FPGA is used as a central node, and a plurality of digital-to-analog converters (DACs) are used as respective sub-nodes and the central node to be directly connected. The reliability of the star topology structure is high, but each branch node needs a group of communication buses to be connected with a central node, so that the number of signal lines is huge, the complexity and difficulty of PCB layout and wiring are correspondingly increased along with the multiple increase of the number of DACs, and the implementation in the phased array antenna with very limited space is very difficult.
The other is bus type topological structure interconnection, wherein an FPGA and DAC chips are mounted on the same bus, the FPGA serves as a master control device, and the DACs serve as slave devices and are distinguished through chip selection signals. Although the bus type topological structure can save a certain number of signal lines, the number of DAC slave devices mounted on the same bus is limited due to the limitation of bus load driving capability; meanwhile, due to bus bifurcation, signals are reflected for many times during transmission, so that partial signals are easy to lose.
Therefore, in the prior art, in a beam control system of a phased array antenna, a topological connection structure between a main control chip and a plurality of signal conversion chips often causes the technical problems of large number of signal lines, high wiring difficulty, or limited number of slave devices, and easy signal loss.
Disclosure of Invention
The application provides an electronic device, an information processing method and an information transmission method, which are used for solving the technical problems that in a beam control system of a phased array antenna, a topological connection structure between a main control chip and a plurality of signal conversion chips often causes huge signal line quantity, higher wiring difficulty or limited slave device quantity, and signals are easy to miss in the prior art.
One aspect of the present application provides an electronic device, including M processing modules, where data transmission is performed between the M processing modules according to a preset downloading order, M is an integer greater than or equal to 2, a Q-th processing module of the M processing modules is respectively connected to a Q-1-th processing module and a Q + 1-th processing module, and when Q is equal to 1, a 1-th processing module of the M processing modules is respectively connected to the M-th processing module and a 2-th processing module; the preset downloading sequence is sequentially transmitted based on the connection relation among the M processing modules, and Q is an integer which is less than or equal to M-1 and greater than or equal to 2;
the Q-1 processing module is used for acquiring first data, generating a first step size identifier, and sending the first step size identifier and the first data to the Q processing module according to the preset downloading sequence, wherein the first step size identifier is used for representing that the number of other processing modules which need to pass through is N when the first data is transmitted from the current processing module to the target processing module according to the preset downloading sequence, and N is an integer greater than or equal to 1;
the Q processing module is used for processing the first step length identifier to generate a second step length identifier which represents that the number of the other processing modules is N-1; judging whether N-1 is 0; if the N-1 is not 0, continuously transmitting the first data and the second step size identifier to the Q +1 processing module according to the preset downloading sequence; and if the N-1 is 0, determining that the Q-th processing module is the target processing module, and stopping transmitting the first data according to the preset downloading sequence.
Optionally, after the Q-1 th processing module is a preset main processing module and the first data is transmitted according to the preset downloading sequence, the main processing module is configured to determine that the data transmission fails when the first data is transmitted to the main processing module again through another processing module of the M processing modules, and adjust the first step size identifier so that the number of the other processing modules represented by the adjusted first step size identifier is N different from N, and transmit the adjusted first step size identifier and the first data to the Q th processing module according to the preset downloading sequence, where N is an integer greater than or equal to 1 and less than M.
Optionally, the Q +1 th processing module is configured to obtain second data, generate a first step identifier, and send the first step identifier and the second data to the Q th processing module according to a preset uploading order that is opposite to the preset downloading order, where the first step identifier is used to represent that the number of other processing modules, except the Q +1 th processing module, that the second data currently passes through is P, and P is an integer greater than or equal to 0;
when the qth processing module is a preset main processing module, the main processing module is configured to determine, based on the first step identifier, that the source processing module of the second data is the qth +1 processing module; when the qth processing module is not the main processing module, the qth processing module is configured to process the first procedure identifier to generate a second procedure identifier, and send the second procedure identifier and the second data to the qth-1 processing module according to the preset uploading sequence, where the second procedure identifier is used to represent that the number of the other processing modules is P + 1.
Optionally, when the qth processing module is the main processing module, the main processing module is configured to determine that the source processing module of the second data is a pth processing module starting from the main processing module according to the preset downloading order.
Optionally, when each processing module of the M processing modules includes a clock signal input terminal, a clock signal output terminal, a data input terminal, and a data output terminal, the clock signal output terminal of the qth processing module is connected to the clock signal input terminal of the Q +1 th processing module, and the data output terminal of the qth processing module is connected to the data input terminal of the Q +1 th processing module.
On the other hand, an embodiment of the present application further provides an information processing method, which is applied to the electronic device as described above, and the method includes:
acquiring first data through a Q-1 th processing module;
generating a first step size identifier through the Q-1 processing module, wherein the first step size identifier is used for representing that the number of other processing modules which need to pass through when the first data is transmitted from the current processing module to the target processing module according to the preset downloading sequence is N, and N is an integer greater than or equal to 1;
sending the first step size identifier and the first data to a Q-th processing module through the Q-1-th processing module according to the preset downloading sequence;
processing the first step size identifier by the Q processing module to generate a second step size identifier, wherein the second step size identifier is used for representing that the number of the other processing modules is N-1;
judging whether the N-1 is 0 or not through the Q processing module, wherein the judgment comprises the following steps: if the N-1 is not 0, continuously transmitting the first data and the second step size identifier to a Q +1 th processing module according to the preset downloading sequence; and if the N-1 is 0, determining that the Q-th processing module is the target processing module, and stopping transmitting the first data according to the preset downloading sequence.
Optionally, the method further comprises:
after the Q-1 processing module is a preset main processing module and transmits the first data according to the preset downloading sequence, if the first data is sent to the main processing module again through another processing module in the M processing modules, determining that the data transmission fails through the main processing module, and adjusting the first step size identifier so that the number of the other processing modules represented by the adjusted first step size identifier is N different from N, wherein N is an integer greater than or equal to 1 and less than M;
and sending the adjusted first step size identifier and the first data to the Q-th processing module according to the preset downloading sequence.
In another aspect, an embodiment of the present application further provides an information transmission method, which is applied to the electronic device described above, where the method includes:
acquiring second data through the Q +1 th processing module;
generating a first step identifier through the Q +1 th processing module, wherein the first step identifier is used for representing that the number of other processing modules, except the Q +1 th processing module, which are currently passed by the second data is P, and P is an integer greater than or equal to 0;
the Q +1 th processing module sends the first step identifier and the second data to the Q th processing module according to a preset uploading sequence opposite to the preset downloading sequence, where the method includes: when the Q processing module is a preset main processing module, the main processing module confirms that a source processing module of the second data is the Q +1 processing module based on the first step identification; and when the Q processing module is not the main processing module, the Q processing module processes the first procedure identifier to generate a second procedure identifier, and sends the second procedure identifier and the second data to the Q-1 processing module according to the preset uploading sequence, wherein the second procedure identifier is used for representing that the number of the other processing modules is P + 1.
Optionally, the main processing module confirms that the source processing module of the second data is the Q +1 th processing module based on the first step identifier, and includes:
and when the qth processing module is the main processing module, the main processing module is configured to determine that the source processing module of the second data is the pth processing module starting from the main processing module according to the preset downloading order.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
in the technical scheme of the embodiment of the application, as the ring topology connection structure is adopted, in the process of receiving and sending the data signals, the digital identifier is correspondingly increased or decreased once when the data passes through one processing module in the ring topology structure, so that the processing module specifically receiving the data signals can be determined through the digital identifier, and the main control device can also determine which processing module specifically receiving the data signals from the ring topology structure through the digital identifier. Moreover, after the plurality of processing modules adopt the connection structure in the embodiment of the application, the signal transmission path is not branched, a large number of signal connection lines are not required to be added, and the number of the added slave devices is not limited, so that the technical effects of reducing the wiring layout difficulty of the antenna signal processing system, improving the signal transmission integrity and being not limited by the number of the slave devices are achieved.
Drawings
Fig. 1 is a schematic diagram of a topology structure among M processing modules of an electronic device according to an embodiment of the present invention;
fig. 2 is a flowchart of an information processing method according to an embodiment of the present invention;
fig. 3 is a flowchart of an information transmission method according to an embodiment of the present invention.
Detailed Description
The application provides an electronic device, an information processing method and an information transmission method, which are used for solving the technical problems that in a beam control system of a phased array antenna, a topological connection structure between a main control chip and a plurality of signal conversion chips often causes huge signal line quantity, higher wiring difficulty or limited slave device quantity, and signals are easy to miss in the prior art.
In order to solve the technical problems, the general idea of the embodiment of the application is as follows:
in the technical scheme of the embodiment of the application, as the ring topology connection structure is adopted, in the process of receiving and sending the data signals, the digital identifier is correspondingly increased or decreased once when the data passes through one processing module in the ring topology structure, so that the processing module specifically receiving the data signals can be determined through the digital identifier, and the main control device can also determine which processing module specifically receiving the data signals from the ring topology structure through the digital identifier. Moreover, after the plurality of processing modules adopt the connection structure in the embodiment of the application, the signal transmission path is not branched, a large number of signal connection lines are not required to be added, and the number of the added slave devices is not limited, so that the technical effects of reducing the wiring layout difficulty of the antenna signal processing system, improving the signal transmission integrity and being not limited by the number of the slave devices are achieved.
The technical solutions of the present application are described in detail below with reference to the drawings and specific embodiments, and it should be understood that the specific features in the embodiments and examples of the present application are detailed descriptions of the technical solutions of the present application, and are not limitations of the technical solutions of the present application, and the technical features in the embodiments and examples of the present application may be combined with each other without conflict.
The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
Example one
Referring to fig. 1, an embodiment of the present application provides an electronic device, including M processing modules, where the M processing modules perform data transmission according to a preset downloading order, M is an integer greater than or equal to 2, a Q-th processing module of the M processing modules is respectively connected to a Q-1-th processing module and a Q + 1-th processing module, and when Q is equal to 1, a 1-th processing module of the M processing modules is respectively connected to the M-th processing module and a 2-th processing module;
the preset downloading sequence is sequentially transmitted based on the connection relation among the M processing modules, and Q is an integer which is less than or equal to M-1 and greater than or equal to 2.
In the actual operation process, the processing modules may be processing chips that are physically independent from each other, or a general-purpose Central Processing Unit (CPU), or an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits that are used to control program execution, or different virtual processing modules in the same processing system. As the processing module, any physical device or virtual module as long as it can realize an independent processing function may be used.
Further, the electronic device may further include a memory, and the number of the memories may be one or more. The Memory may include a Read Only Memory (ROM), a Random Access Memory (RAM), and a disk Memory.
It should be noted that, in this embodiment of the application, the processing module may specifically be a digital-to-analog conversion chip, and/or an analog-to-digital conversion chip, and/or an FPGA main processing chip in the antenna signal transceiving system. And the connection mode of the M processing modules is a ring topology structure which is connected one by one and end to end.
Optionally, the Q-1 processing module is configured to obtain first data, generate a first step size identifier, and send the first step size identifier and the first data to the Q-th processing module according to the preset downloading order, where the first step size identifier is used to indicate that the number of additional processing modules that need to pass through when the first data is transmitted from the current processing module to the target processing module according to the preset downloading order is N, and N is an integer greater than or equal to 1;
the Q processing module is used for processing the first step length identifier to generate a second step length identifier which represents that the number of the other processing modules is N-1; judging whether N-1 is 0; if the N-1 is not 0, continuously transmitting the first data and the second step size identifier to the Q +1 processing module according to the preset downloading sequence; and if the N-1 is 0, determining that the Q-th processing module is the target processing module, and stopping transmitting the first data according to the preset downloading sequence.
The obtained first data can be received by the Q-1 processing module and sent by other devices, or can be processed and generated by the Q-1 processing module, and the like.
In actual operation, when the first step size identifier and the first data are sent to another processing module by one processing module, the first step size identifier and the first data can be packaged and processed into a file by the processing module to be sent; the first step length identifier and the first data can also be encrypted through a processing module, and then the encrypted first step length identifier and the encrypted first data are sent; the first step size identifier and the first data may be inserted with a special identifier, such as a time identifier, a feature identifier, and the like, by which it may be confirmed that a certain first step size identifier matches a certain first data, and the matching may mean that the first step size identifier may be used to characterize the number of processing modules through which the first data passes.
It should be noted that, in an actual operation process, the number N of the additional processing modules characterized by the first step size identifier is processed to be N-1, which may mean that the number N of the additional processing modules characterized by the second step size identifier is N-1. Based on the content disclosed in the technical solution of the present application, a person skilled in the art will readily understand that in the implementation process of the technical solution in this application, the N cycle represented by the step size identifier may be decremented until the first data is transmitted to the processing module where the first data is located when N is equal to 0.
For example, 5 processing modules, namely a processing module 1, a processing module 2, a processing module 3, a processing module 4, and a processing module 5, are connected by using a ring topology structure in the embodiment of the present application, and a preset downloading order among the 5 processing modules is transmission according to a numerical ascending order, when the processing module 1 acquires first data, the processing module 1 determines that the first data needs to be sent to the processing module 5, and according to the preset downloading order, the number of additional processing modules that the processing module 1 needs to pass through to transmit the data to the processing module 5 is 3, so that the processing module 1 generates a first step size identifier matching the first data, and the number N of the first step size identifier identifiers is 3; after the processing module 1 transmits the first data and the first step size identifier to the processing module 2, the processing module 2 may process the first step size identifier into a second step size identifier, that is, N is 3-1 is 2, and determines whether N is 0, and if the determination result is no, the processing module 2 further transmits the second step size identifier to the processing module 3, and the processing module 3 continues to loop the above technical solution to process the second step size identifier, that is, N is 2-1 is 1, and loops the above determination process until the first data and the corresponding step size identifier are transmitted to the processing module 5, and then the corresponding step size identifier N is decremented and then also becomes 0, so based on the technical solution in the embodiment of the present application, the processing module 5 stops transmitting the first data after determining that N is 0, the first data is stored in the processing module 5, and the processing module 5 performs corresponding subsequent processing.
Optionally, after the Q-1 th processing module is a preset main processing module and the first data is transmitted according to the preset downloading sequence, the main processing module is configured to determine that the data transmission fails when the first data is transmitted to the main processing module again through another processing module of the M processing modules, and adjust the first step size identifier so that the number of the other processing modules represented by the adjusted first step size identifier is N different from N, and transmit the adjusted first step size identifier and the first data to the Q th processing module according to the preset downloading sequence, where N is an integer greater than or equal to 1 and less than M.
That is to say, in the technical solution of the embodiment of the present application, all externally input data are first obtained by a main processing module, then the main processing module is used as an initial processing module, the data and a first step size identifier assigned by the main processing module are sequentially transmitted according to the preset downloading sequence, and the data are finally sent to the target processing module based on a step number N represented by the first step size identifier. Preferably, in the technical solution of the embodiment of the present application, if a certain data is transmitted to another processing module from the main processing module according to the preset downloading sequence, and then is transmitted to the main processing module again by another processing module of the M processing modules through a round of cyclic transmission, the main processing module determines that the data transmission of the current round is failed, and automatically readjusts the assignment of the first step size identifier, so that the data can be transmitted to the target processing module in a round of cyclic transmission in the next round of transmission.
Optionally, the Q +1 th processing module is configured to obtain second data, generate a first step identifier, and send the first step identifier and the second data to the Q th processing module according to a preset uploading order that is opposite to the preset downloading order, where the first step identifier is used to represent that the number of other processing modules, except the Q +1 th processing module, that the second data currently passes through is P, and P is an integer greater than or equal to 0;
when the qth processing module is a preset main processing module, the main processing module is configured to determine, based on the first step identifier, that the source processing module of the second data is the qth +1 processing module; when the qth processing module is not the main processing module, the qth processing module is configured to process the first procedure identifier to generate a second procedure identifier, and send the second procedure identifier and the second data to the qth-1 processing module according to the preset uploading sequence, where the second procedure identifier is used to represent that the number of the other processing modules is P + 1.
Similarly, the first step identifier is similar to the first step identifier, and the second data is also similar to the first data, and when the first step identifier and the second data are sent from one processing module to another processing module, the first step identifier and the second data may also be subjected to packing processing, and/or encryption processing, and/or insertion of a special identifier by the processing module.
Similarly, the number P of the other processing modules represented by the first step identifier is processed to be P +1, which means that the number P of the other processing modules represented by the second step identifier is P + 1. Also, based on the disclosure in the technical solution of the present application, it can be easily known by those skilled in the art that the technical solution in the embodiment of the present application may increment the P cycle represented by the step identifier during the execution process until after the second data is transmitted to the preset main processing device, the main processing device may determine which processing module the second data originates from based on the value of N represented by the received step identifier.
For example, 5 processing modules, namely the processing module 1, the processing module 2, the processing module 3, the processing module 4, and the processing module 5, are connected by using the ring topology structure in the embodiment of the present application, the processing module 5 is a preset main processing module, and a preset uploading sequence between the 5 processing modules is opposite to a preset downloading sequence in the previous example, that is, transmission is performed according to a descending order of numbers. After the processing module 4 acquires second data, the processing module 4 generates a first step identifier, and the number of other processing modules except the processing module 4, which the second data represented by the first step identifier currently passes through, is P ═ 0. Then, the processing module 4 sends the second data and the first step identifier to the processing module 3 according to the preset downloading order, the processing module 3 processes the first step identifier into a second step identifier, that is, P is 0+1 or 1, because the processing module 3 is not a preset main processing module, the processing module 3 continues to circulate the above technical scheme to transmit the second data and the second step identifier to the processing module 2, the processing module 2 repeats the above processing procedure, processes the second step identifier to generate a new step identifier, that is, P is 1+1 or 2, because the processing module 2 is not the main processing module yet, the processing module 2 still transmits the second data and the corresponding step identifier according to the preset downloading order until the second data and the corresponding step identifier are transmitted to the processing module 5, the corresponding step identifier is characterized as P ═ 4, and since the processing module 5 is the main processing module, the main processing module may determine that the second data is in the preset uploading order based on the value P characterized by the step identifier at this time, and start from the main processing module with the P ═ 4 processing modules in the preset downloading order, that is, the processing module 4, that is, the main processing module may determine that the source of the second data is the processing module 4 based on the value 4 of P characterized by the step identifier. Of course, in the actual operation process, the main processing module may also determine the source processing module of the second data based on the value P represented by the step identifier through other calculation formulas. Are not described herein for brevity of description.
That is to say, in a further optional manner of the technical solution in this embodiment of the application, when the qth processing module is the main processing module, the main processing module is configured to determine that a source processing module of the second data is a pth processing module starting from the main processing module according to the preset downloading order.
Optionally, when each processing module of the M processing modules includes a clock signal input terminal, a clock signal output terminal, a data input terminal, and a data output terminal, the clock signal output terminal of the qth processing module is connected to the clock signal input terminal of the Q +1 th processing module, and the data output terminal of the qth processing module is connected to the data input terminal of the Q +1 th processing module.
In summary, according to the technical solution in the embodiment of the present application, because the ring topology connection structure is adopted, in the process of receiving and sending the data signal, the digital identifier is correspondingly increased or decreased once when the data passes through one processing module in the ring topology structure, so that the processing module specifically receiving the data signal can be determined by the digital identifier, and the main control device can also determine which processing module in the ring topology structure the received data signal specifically comes from through the digital identifier. Moreover, after the plurality of processing modules adopt the connection structure in the embodiment of the application, the signal transmission path is not branched, a large number of signal connection lines are not required to be added, and the number of the added slave devices is not limited, so that the technical effects of reducing the wiring layout difficulty of the antenna signal processing system, improving the signal transmission integrity and being not limited by the number of the slave devices are achieved.
Example two
Referring to fig. 2, a second embodiment of the present application provides an information processing method applied to the electronic device, where the method includes:
step 201: acquiring first data through a Q-1 th processing module;
step 202: generating a first step size identifier through the Q-1 processing module, wherein the first step size identifier is used for representing that the number of other processing modules which need to pass through when the first data is transmitted from the current processing module to the target processing module according to the preset downloading sequence is N, and N is an integer greater than or equal to 1;
step 203: sending the first step size identifier and the first data to a Q-th processing module through the Q-1-th processing module according to the preset downloading sequence;
step 204: processing the first step size identifier by the Q processing module to generate a second step size identifier, wherein the second step size identifier is used for representing that the number of the other processing modules is N-1;
step 205: judging whether the N-1 is 0 or not through the Q processing module, wherein the judgment comprises the following steps: if the N-1 is not 0, continuously transmitting the first data and the second step size identifier to a Q +1 th processing module according to the preset downloading sequence; and if the N-1 is 0, determining that the Q-th processing module is the target processing module, and stopping transmitting the first data according to the preset downloading sequence.
Optionally, the method further comprises:
after the Q-1 processing module is a preset main processing module and transmits the first data according to the preset downloading sequence, if the first data is sent to the main processing module again through another processing module in the M processing modules, determining that the data transmission fails through the main processing module, and adjusting the first step size identifier so that the number of the other processing modules represented by the adjusted first step size identifier is N different from N, wherein N is an integer greater than or equal to 1 and less than M;
and sending the adjusted first step size identifier and the first data to the Q-th processing module according to the preset downloading sequence.
Various changes and specific examples in the electronic device in the foregoing embodiment in fig. 1 are also applicable to the information processing method in this embodiment, and a person skilled in the art can clearly know the implementation method of the information processing method in this embodiment through the foregoing detailed description of the electronic device, so for the brevity of the description, detailed descriptions are omitted here.
EXAMPLE III
Referring to fig. 3, a third embodiment of the present application provides an information transmission method applied to the electronic device, where the method includes:
step 301: acquiring second data through the Q +1 th processing module;
step 302: generating a first step identifier through the Q +1 th processing module, wherein the first step identifier is used for representing that the number of other processing modules, except the Q +1 th processing module, which are currently passed by the second data is P, and P is an integer greater than or equal to 0;
step 303: the Q +1 th processing module sends the first step identifier and the second data to the Q th processing module according to a preset uploading sequence opposite to the preset downloading sequence, where the method includes: when the Q processing module is a preset main processing module, the main processing module confirms that a source processing module of the second data is the Q +1 processing module based on the first step identification; and when the Q processing module is not the main processing module, the Q processing module processes the first procedure identifier to generate a second procedure identifier, and sends the second procedure identifier and the second data to the Q-1 processing module according to the preset uploading sequence, wherein the second procedure identifier is used for representing that the number of the other processing modules is P + 1.
Optionally, the main processing module confirms that the source processing module of the second data is the Q +1 th processing module based on the first step identifier, and includes:
and when the qth processing module is the main processing module, the main processing module is configured to determine that the source processing module of the second data is the pth processing module starting from the main processing module according to the preset downloading order.
Various changes and specific examples in the electronic device in the embodiment of fig. 1 are also applicable to the information transmission method in the embodiment, and those skilled in the art can clearly know the implementation method of the information transmission method in the embodiment through the foregoing detailed description of the electronic device, so that details are not described here for the sake of brevity of the description.
Therefore, in the technical scheme of the embodiment of the application, as the ring topology connection structure is adopted, in the process of receiving and sending the data signals, the digital identifier is correspondingly increased or decreased once when the data passes through one processing module in the ring topology structure, so that the processing module specifically receiving the data signals can be determined through the digital identifier, and the main control device can also determine which processing module in the ring topology structure the received data signals specifically come from through the digital identifier. Moreover, after the plurality of processing modules adopt the connection structure in the embodiment of the application, the signal transmission path is not branched, a large number of signal connection lines are not required to be added, and the number of the added slave devices is not limited, so that the technical effects of reducing the wiring layout difficulty of the antenna signal processing system, improving the signal transmission integrity and being not limited by the number of the slave devices are achieved.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Specifically, the computer program instructions corresponding to an information processing method in the embodiments of the present application may be stored on a storage medium such as an optical disc, a hard disc, or a usb disk, and when the computer program instructions corresponding to an information processing method in the storage medium are read or executed by an electronic device, the method includes the following steps:
acquiring first data through a Q-1 th processing module;
generating a first step size identifier through the Q-1 processing module, wherein the first step size identifier is used for representing that the number of other processing modules which need to pass through when the first data is transmitted from the current processing module to the target processing module according to the preset downloading sequence is N, and N is an integer greater than or equal to 1;
sending the first step size identifier and the first data to a Q-th processing module through the Q-1-th processing module according to the preset downloading sequence;
processing the first step size identifier by the Q processing module to generate a second step size identifier, wherein the second step size identifier is used for representing that the number of the other processing modules is N-1;
judging whether the N-1 is 0 or not through the Q processing module, wherein the judgment comprises the following steps: if the N-1 is not 0, continuously transmitting the first data and the second step size identifier to a Q +1 th processing module according to the preset downloading sequence; and if the N-1 is 0, determining that the Q-th processing module is the target processing module, and stopping transmitting the first data according to the preset downloading sequence.
Specifically, the computer program instructions corresponding to an information transmission method in the embodiments of the present application may be stored on a storage medium such as an optical disc, a hard disc, or a usb disk, and when the computer program instructions corresponding to an information transmission method in the storage medium are read or executed by an electronic device, the method includes the following steps:
acquiring second data through the Q +1 th processing module;
generating a first step identifier through the Q +1 th processing module, wherein the first step identifier is used for representing that the number of other processing modules, except the Q +1 th processing module, which are currently passed by the second data is P, and P is an integer greater than or equal to 0;
the Q +1 th processing module sends the first step identifier and the second data to the Q th processing module according to a preset uploading sequence opposite to the preset downloading sequence, where the method includes: when the Q processing module is a preset main processing module, the main processing module confirms that a source processing module of the second data is the Q +1 processing module based on the first step identification; and when the Q processing module is not the main processing module, the Q processing module processes the first procedure identifier to generate a second procedure identifier, and sends the second procedure identifier and the second data to the Q-1 processing module according to the preset uploading sequence, wherein the second procedure identifier is used for representing that the number of the other processing modules is P + 1.
Optionally, the step of storing in the storage medium: the main processing module, based on the first step identifier, determines that the source processing module of the second data is the computer program instruction corresponding to the Q +1 th processing module, and when the computer program instruction is executed, the method specifically includes the following steps:
and the main processing module confirms that the source processing module of the second data is the M-P processing module starting from the main processing module according to the preset uploading sequence and the preset downloading sequence.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Further, the steps of the methods in the technical solutions of the present application may be reversed, and the sequence may be changed while still falling within the scope of the invention covered by the present application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (9)
1. An electronic device comprises M processing modules, wherein data transmission is performed among the M processing modules according to a preset downloading sequence, and M is an integer greater than or equal to 3, wherein the Q-th processing module of the M processing modules is respectively connected with the Q-1-th processing module and the Q + 1-th processing module, and when Q is equal to 1, the 1-st processing module of the M processing modules is respectively connected with the M-th processing module and the 2-nd processing module; the preset downloading sequence is sequentially transmitted based on the connection relation among the M processing modules, and Q is an integer which is less than or equal to M-1 and greater than or equal to 2;
the Q-1 processing module is used for acquiring first data, generating a first step size identifier, and sending the first step size identifier and the first data to the Q processing module according to the preset downloading sequence, wherein the first step size identifier is used for representing that the number of other processing modules which need to pass through is N when the first data is transmitted from the current processing module to the target processing module according to the preset downloading sequence, and N is an integer greater than or equal to 1;
the Q processing module is used for processing the first step length identifier to generate a second step length identifier which represents that the number of the other processing modules is N-1; judging whether N-1 is 0; if the N-1 is not 0, continuously transmitting the first data and the second step size identifier to the Q +1 processing module according to the preset downloading sequence; and if the N-1 is 0, determining that the Q-th processing module is the target processing module, and stopping transmitting the first data according to the preset downloading sequence.
2. The electronic device according to claim 1, wherein after the Q-1 th processing module is a preset main processing module and the first data is transmitted according to the preset downloading order, the main processing module is configured to determine that the data transmission fails this time when the first data is transmitted to the main processing module again through another processing module of the M processing modules, and adjust the first step size identifier so that the number of the other processing modules represented by the adjusted first step size identifier is N different from N, and transmit the adjusted first step size identifier and the first data to the Q-th processing module according to the preset downloading order, where N is an integer greater than or equal to 1 and less than M.
3. The electronic device according to claim 1, wherein the Q +1 th processing module is configured to obtain second data and generate a first procedure identifier, and send the first procedure identifier and the second data to the Q-th processing module according to a preset uploading sequence opposite to the preset downloading sequence, where the first procedure identifier is used to represent that the number of other processing modules, except the Q + 1-th processing module, that the second data currently passes through is P, and P is an integer greater than or equal to 0;
when the qth processing module is a preset main processing module, the main processing module is configured to determine, based on the first step identifier, that the source processing module of the second data is the qth +1 processing module; when the qth processing module is not the main processing module, the qth processing module is configured to process the first procedure identifier to generate a second procedure identifier, and send the second procedure identifier and the second data to the qth-1 processing module according to the preset uploading sequence, where the second procedure identifier is used to represent that the number of the other processing modules is P + 1.
4. The electronic device as claimed in claim 3, wherein when the qth processing module is the main processing module, the main processing module is configured to determine that the source processing module of the second data is the pth processing module according to the predetermined downloading order from the main processing module.
5. The electronic device of claim 4, wherein when each of the M processing modules includes a clock signal input, a clock signal output, a data input, and a data output, respectively, the clock signal output of the Q processing module is connected to the clock signal input of the Q +1 processing module and the data output of the Q processing module is connected to the data input of the Q +1 processing module.
6. An information processing method applied to the electronic device according to any one of claims 1 to 5, the method comprising:
acquiring first data through a Q-1 th processing module;
generating a first step size identifier through the Q-1 processing module, wherein the first step size identifier is used for representing that the number of other processing modules which need to pass through when the first data is transmitted from the current processing module to the target processing module according to the preset downloading sequence is N, and N is an integer greater than or equal to 1;
sending the first step size identifier and the first data to a Q-th processing module through the Q-1-th processing module according to the preset downloading sequence;
processing the first step size identifier by the Q processing module to generate a second step size identifier, wherein the second step size identifier is used for representing that the number of the other processing modules is N-1;
judging whether the N-1 is 0 or not through the Q processing module, wherein the judgment comprises the following steps: if the N-1 is not 0, continuously transmitting the first data and the second step size identifier to a Q +1 th processing module according to the preset downloading sequence; and if the N-1 is 0, determining that the Q-th processing module is the target processing module, and stopping transmitting the first data according to the preset downloading sequence.
7. The information processing method of claim 6, wherein the method further comprises:
after the Q-1 processing module is a preset main processing module and transmits the first data according to the preset downloading sequence, if the first data is sent to the main processing module again through another processing module in the M processing modules, determining that the data transmission fails through the main processing module, and adjusting the first step size identifier so that the number of the other processing modules represented by the adjusted first step size identifier is N different from N, wherein N is an integer greater than or equal to 1 and less than M;
and sending the adjusted first step size identifier and the first data to the Q-th processing module according to the preset downloading sequence.
8. An information transmission method applied to the electronic device according to any one of claims 1 to 5, the method comprising:
acquiring second data through the Q +1 th processing module;
generating a first step identifier through the Q +1 th processing module, wherein the first step identifier is used for representing that the number of other processing modules, except the Q +1 th processing module, which are currently passed by the second data is P, and P is an integer greater than or equal to 0;
the Q +1 th processing module sends the first step identifier and the second data to the Q th processing module according to a preset uploading sequence opposite to the preset downloading sequence, where the method includes: when the Q processing module is a preset main processing module, the main processing module confirms that a source processing module of the second data is the Q +1 processing module based on the first step identification; and when the Q processing module is not the main processing module, the Q processing module processes the first procedure identifier to generate a second procedure identifier, and sends the second procedure identifier and the second data to the Q-1 processing module according to the preset uploading sequence, wherein the second procedure identifier is used for representing that the number of the other processing modules is P + 1.
9. The information transmission method according to claim 8, wherein the main processing module confirms that the source processing module of the second data is the Q +1 th processing module based on the first process identification, and includes:
and when the qth processing module is the main processing module, the main processing module is configured to determine that the source processing module of the second data is the pth processing module starting from the main processing module according to the preset downloading order.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1771506A (en) * | 2003-05-28 | 2006-05-10 | 株式会社日立制作所 | Radio recognition semiconductor device and its manufacturing method |
| CN104316908A (en) * | 2014-10-08 | 2015-01-28 | 上海航天电子通讯设备研究所 | Optically controlled phased array radar front end transmitting and receiving method and device |
| ES2467465B1 (en) * | 2012-12-11 | 2015-04-06 | Incide, S.A. | RFID LABEL, SYSTEMA AND PROCEDURE FOR THE IDENTIFICATION OF SAMPLES TO CRIOGENIC TEMPERATURES |
| CN104991883A (en) * | 2015-06-04 | 2015-10-21 | 青岛海信信芯科技有限公司 | Sending and receiving apparatuses with chip interconnection and sending and receiving method and system |
| CN105356051A (en) * | 2015-11-16 | 2016-02-24 | 中国电子科技集团公司第十研究所 | High-power seeker tile type active phased array antenna |
| CN205945749U (en) * | 2016-08-29 | 2017-02-08 | 陕西佳之易网络科技有限公司 | High -speed multichannel broadband DBF board |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015035158A (en) * | 2013-08-09 | 2015-02-19 | ルネサスエレクトロニクス株式会社 | Data processing system |
-
2017
- 2017-07-18 CN CN201710584847.2A patent/CN107426076B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1771506A (en) * | 2003-05-28 | 2006-05-10 | 株式会社日立制作所 | Radio recognition semiconductor device and its manufacturing method |
| ES2467465B1 (en) * | 2012-12-11 | 2015-04-06 | Incide, S.A. | RFID LABEL, SYSTEMA AND PROCEDURE FOR THE IDENTIFICATION OF SAMPLES TO CRIOGENIC TEMPERATURES |
| CN104316908A (en) * | 2014-10-08 | 2015-01-28 | 上海航天电子通讯设备研究所 | Optically controlled phased array radar front end transmitting and receiving method and device |
| CN104991883A (en) * | 2015-06-04 | 2015-10-21 | 青岛海信信芯科技有限公司 | Sending and receiving apparatuses with chip interconnection and sending and receiving method and system |
| CN105356051A (en) * | 2015-11-16 | 2016-02-24 | 中国电子科技集团公司第十研究所 | High-power seeker tile type active phased array antenna |
| CN205945749U (en) * | 2016-08-29 | 2017-02-08 | 陕西佳之易网络科技有限公司 | High -speed multichannel broadband DBF board |
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