CN107425073A - A kind of thin film transistor (TFT) and preparation method, array base palte - Google Patents

Abstract

The present application provides a thin film transistor, a preparation method, and an array substrate, which are used to reduce active layer damage in the preparation of metal oxide thin film transistors without increasing the photolithography process. The thin film transistor provided by the present application includes: Gate, gate insulation layer, active layer, source and drain, the active layer is provided with two grooves spaced apart from each other, the source and drain are respectively arranged in the two grooves .

Description

A kind of thin film transistor and its preparation method, array substrate

technical field

The present application relates to the field of display technology, in particular to a thin film transistor, a manufacturing method, and an array substrate.

Background technique

A thin film transistor (Thin-film transistor, TFT) is a kind of field effect transistor, which is widely used in the field of display and plays a very important role in the working performance of the display device. Thin film transistors can be classified into amorphous silicon thin film transistors, polysilicon thin film transistors and metal oxide thin film transistors according to the semiconductor layer materials used. Among them, metal oxide thin film transistor (Metal Oxide Thin Film Transistor, MOTFT) has the characteristics of high mobility, simple manufacturing process, low cost, and excellent large-area uniformity. Therefore, since the birth of MOTFT technology It has attracted the attention of the industry.

At present, the main structures used in MOTFT are back channel etching structure and etching barrier layer structure. For the MOTFT with back channel etching structure, after the active layer is formed, a metal layer is deposited on the active layer, and then the source and drain electrodes are formed by etching, but when the source and drain electrodes are etched on the active layer, no matter Whether dry etching or wet etching is used, damage to the active layer is likely to occur, thereby affecting the performance of the MOTFT. The structure of the etch barrier layer is to make an etch barrier layer after the active layer is formed, then deposit a metal layer on it and form the source and drain electrodes by etching. The etch barrier layer can be used to form the source and drain electrodes While protecting the active layer from being damaged, an additional photolithography process is required to form an etching barrier layer, which will undoubtedly increase the MOTFT manufacturing process flow.

Based on this, how to reduce the damage of the active layer in the fabrication of the metal oxide thin film transistor without increasing the photolithography process is a technical problem to be solved urgently by those skilled in the art.

Contents of the invention

Embodiments of the present application provide a thin film transistor, a preparation method, and an array substrate, so as to reduce damage to an active layer in the preparation of a metal oxide thin film transistor without increasing the photolithography process.

A thin film transistor provided in an embodiment of the present application includes: a gate, a gate insulating layer, an active layer, a source and a drain, and two grooves spaced apart from each other are arranged in the active layer, and the source and the drain are respectively arranged in the two grooves.

The thin film transistor provided in the embodiment of the present application includes: a gate, a gate insulating layer, an active layer, a source and a drain, and two grooves spaced apart from each other are arranged in the active layer, and the source and drain The poles are respectively arranged in the two grooves. Since there is no etching barrier layer between the active layer and the source and drain, the photolithography process will not be increased when making the thin film transistor, and the source and drain are respectively arranged In the two grooves spaced apart from each other in the active layer, on the one hand, etching is not used to form the source and drain electrodes when making the thin film transistor, so that there will be no problems caused by etching the metal film layer of the source and drain electrodes. Active layer damage, on the other hand, the thin film transistor is relatively flat, and the level difference is small, so that the yield rate of the thin film transistor is high.

Preferably, the source and drain are flush with the upper surface of the active layer.

Since the source electrode and the drain electrode are flush with the upper surface of the active layer, the contact resistance can be reduced, the on-state current of the thin film transistor can be increased, and the performance of the thin film transistor can be improved.

Preferably, the groove penetrates through the active layer in the thickness direction.

Preferably, the material of the active layer is metal oxide, and the metal oxide is InGaZnO.

An embodiment of the present application also provides an array substrate, including: the thin film transistor provided in any embodiment of the present application, a passivation layer disposed above the thin film transistor, and a pixel electrode electrically connected to the drain of the thin film transistor .

Since the array substrate provided by the embodiment of the present application adopts the above-mentioned thin film transistor, and the above-mentioned thin film transistor includes: a gate, a gate insulating layer, an active layer, a source and a drain, and two Grooves spaced apart from each other, the source and the drain are respectively arranged in the two grooves, since there is no etching stopper layer between the active layer and the source and drain, it will not increase when making the thin film transistor photolithography process, and the source and drain are respectively arranged in two grooves spaced apart from each other in the active layer. The active layer is damaged due to the etching of the metal film layer of the source and the drain. On the other hand, the thin film transistor is relatively flat and has few steps, so that the yield rate of the thin film transistor is high.

The embodiment of the present application also provides a method for preparing a thin film transistor, including:

Forming a semiconductor film layer on the substrate;

forming two mutually spaced grooves in the semiconductor film layer through a patterning process;

forming a metal film layer on the semiconductor film layer formed with grooves;

removing all the metal film layers except the metal film layers in the two grooves by a chemical mechanical planarization process, and using the metal film layers in the two grooves as source and drain electrodes respectively;

An active layer is formed through a patterning process for the semiconductor film layer on which the source electrode and the drain electrode are formed.

Using this method to prepare thin-film transistors, since there is no need to make an etching stopper layer between the active layer and the source and drain, it does not increase the photolithography process, and when forming the source and drain, it is first formed in the semiconductor film layer. Two grooves spaced apart from each other, and then a metal film layer is formed on the semiconductor film layer formed with the groove, and then all the metal film layers except the metal film layer in the two grooves are removed by a chemical mechanical planarization process, The metal film layers in the two grooves are used as the source and drain respectively. On the one hand, the source and drain are not formed by etching when making the thin film transistor, so that there will be no damage caused by etching the metal film of the source and drain. On the other hand, the prepared thin film transistor is relatively flat with less step difference, so that the yield rate of the prepared thin film transistor is high.

Preferably, the forming a metal film layer on the semiconductor film layer formed with grooves specifically includes:

A metal film layer having a thickness not smaller than the maximum depth of the groove is formed on the semiconductor film layer on which the groove is formed.

Since the thickness of the metal film layer is not less than the maximum depth of the groove, the formed source and drain can fill the two spaced grooves in the active layer, which can reduce the contact resistance and improve the opening of the thin film transistor. State current, thereby improving the performance of thin film transistors.

Preferably, the polishing liquid used in the chemical mechanical planarization process in the step of removing the metal film layer is an alkaline non-abrasive polishing liquid.

Since the polishing liquid used in the chemical mechanical planarization process in the step of removing the metal film layer is an alkaline non-abrasive polishing liquid, there is almost no damage to the active source electrode and the drain electrode when the chemical mechanical planarization process is used to make the source electrode and the drain electrode. layer damage.

Preferably, the formation of two mutually spaced grooves in the semiconductor film layer through a patterning process specifically includes:

Two grooves spaced apart from each other and penetrating through the semiconductor film layer are formed in the semiconductor film layer through a patterning process.

Preferably, before forming the semiconductor film layer, or after forming the active layer, the method further includes:

forming a gate insulating film layer on the substrate;

The gate insulating film layer is planarized by a chemical mechanical planarization process to form a gate insulating layer.

Since the gate insulating layer is also produced through a chemical mechanical planarization process, the step difference of the thin film transistor can be further reduced, thereby improving the yield rate of the thin film transistor.

Description of drawings

FIG. 1 is a schematic structural diagram of a thin film transistor provided in an embodiment of the present application;

FIG. 2 is a schematic structural diagram of another thin film transistor provided in an embodiment of the present application;

FIG. 3 is a schematic flow diagram of forming an active layer, a source electrode, and a drain electrode in the thin film transistor manufacturing method provided in the embodiment of the present application;

4(a) to 4(h) are schematic diagrams of the manufacturing process flow of the thin film transistor provided in the embodiment of the present application;

FIG. 5 is a schematic structural diagram of an array substrate provided in an embodiment of the present application;

FIG. 6 is a schematic structural diagram of another array substrate provided by an embodiment of the present application.

detailed description

Embodiments of the present application provide a thin film transistor, a preparation method, and an array substrate, so as to reduce damage to an active layer in the preparation of a metal oxide thin film transistor without increasing the photolithography process.

The following will clearly and completely describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

It should be noted that the thickness and shape of each layer in the drawings of the present application do not reflect the real scale, and the purpose is only to schematically illustrate the content of the present application.

The technical solutions provided in the embodiments of the present application are applicable to both bottom-gate thin film transistors and top-gate thin film transistors. The technical solutions provided in the embodiments of the present application will be described below by taking the bottom-gate thin film transistors as an example.

Referring to Fig. 1, a kind of thin film transistor provided by the embodiment of the present application includes: a gate 11, a gate insulating layer 12, an active layer 13, a source 14 and a drain 15, and the active layer 13 is provided with two mutually spaced The grooves 16, the source electrode 14 and the drain electrode 15 are arranged in the two grooves 16 respectively.

Wherein, the material of the gate 11 may be, for example, metals such as Cr, Al, Cu, Ti, Ta, Mo, or alloys thereof.

The material of the gate insulating layer 12 can be, for example, one or a combination of silicon oxide (SiO _x ) and silicon nitride (SiN _x ).

The material of the source electrode 14 and the drain electrode 15 can be, for example, metals such as Cr, W, Cu, Ti, Ta, Mo, or alloys thereof, and the source electrode 14 and the drain electrode 15 can be a layer structure composed of one layer of metal, or can be multi-layered. Layer structure composed of layer metal.

Since there is no etching stopper layer between the active layer 13 and the source and drain electrodes, the photolithography process will not be increased when making the thin film transistor, and the source electrode 14 and the drain electrode 15 are respectively arranged on two sides of the active layer 13. In the grooves 16 spaced apart from each other, on the one hand, the source and drain are not formed by etching when making the thin film transistor, so that the active layer 13 will not be damaged due to the etching of the metal film layer of the source and drain. On the one hand, the thin film transistor is relatively flat and has few steps, so that the yield rate of the thin film transistor is high.

In a preferred embodiment, as shown in FIG. 1 , the source electrode 14 and the drain electrode 15 are flush with the upper surface of the active layer 13, that is, the source electrode 14 and the drain electrode 15 fill up two of the active layer 13. The grooves 16 spaced apart from each other can reduce the contact resistance and increase the on-state current of the thin film transistor, thereby improving the performance of the thin film transistor. Certainly, the source electrode 14 and the drain electrode 15 may not fill the two grooves 16 spaced apart from each other in the active layer 13, but it will only have a certain impact on the performance of the thin film transistor, and this embodiment of the present application does not discuss this. limited.

The above-mentioned groove 16 may not penetrate the active layer 13 in the thickness direction, as shown in FIG. The thickness direction runs through the active layer 13 , as shown in FIG. 2 .

In a preferred embodiment, the material of the active layer 13 is metal oxide, wherein the metal oxide can be, for example, indium gallium zinc oxide (IGZO).

Based on the same inventive concept, as shown in Figure 3, the embodiment of the present application also provides a method for manufacturing a thin film transistor, including the following steps:

S101, forming a semiconductor film layer on the substrate;

S102, forming two mutually spaced grooves in the semiconductor film layer through a patterning process;

S103, forming a metal film layer on the semiconductor film layer formed with grooves;

S104. Remove all the metal film layers except the metal film layers in the two grooves by chemical mechanical planarization process (CMP), and use the metal film layers in the two grooves as source and drain respectively pole;

S105 , for the semiconductor film layer formed with the source electrode and the drain electrode, an active layer is formed through a patterning process.

Using this method to prepare thin-film transistors, since there is no need to make an etching stopper layer between the active layer and the source and drain, it does not increase the photolithography process, and when forming the source and drain, it is first formed in the semiconductor film layer. Two grooves spaced apart from each other, and then a metal film layer is formed on the semiconductor film layer formed with the groove, and then all the metal film layers except the metal film layer in the two grooves are removed by a chemical mechanical planarization process, The metal film layers in the two grooves are used as the source and drain respectively. On the one hand, the source and drain are not formed by etching when making the thin film transistor, so that there will be no damage caused by etching the metal film of the source and drain. On the other hand, the prepared thin film transistor is relatively flat with less step difference, so that the yield rate of the prepared thin film transistor is high.

The etching of the semiconductor film layer in the above method can be performed by wet etching, for example.

In a preferred implementation manner, in step S102, two grooves spaced apart from each other are formed in the semiconductor film layer through a patterning process, which may specifically include:

Two grooves spaced apart from each other and penetrating through the semiconductor film layer are formed in the semiconductor film layer through a patterning process.

In a preferred embodiment, in order to reduce the contact resistance and increase the on-state current of the thin film transistor, thereby improving the performance of the thin film transistor, in step S103, a metal film layer is formed on the semiconductor film layer formed with grooves, specifically Can include:

A metal film layer having a thickness not smaller than the maximum depth of the groove is formed on the semiconductor film layer on which the groove is formed.

In a preferred embodiment, the polishing liquid used in the chemical mechanical planarization process in the step of removing the metal film layer in step S104 is an alkaline non-abrasive polishing liquid, so that the source electrode and the When draining, there is almost no damage to the active layer.

In a preferred embodiment, before forming the semiconductor film layer, the method may also include:

forming a gate insulating film layer on the substrate;

The gate insulating film layer is planarized by a chemical mechanical planarization process to form a gate insulating layer.

In a preferred embodiment, after forming the active layer, the method may further include:

forming a gate insulating film layer on the substrate;

The gate insulating film layer is planarized by a chemical mechanical planarization process to form a gate insulating layer.

Since the gate insulating layer is also produced through a chemical mechanical planarization process, the step difference of the thin film transistor can be further reduced, thereby improving the yield rate of the thin film transistor.

Taking the bottom-gate thin film transistor as an example below, the manufacturing process flow of the thin film transistor provided in the embodiment of the present application will be described in detail with reference to FIGS. 4( a ) to 4 ( h ). Its preparation process comprises the following steps:

Step 1, referring to FIG. 4(a), forming a gate 02 on the substrate 01;

Wherein, the thickness of the gate 02 is about 300nm, and the process flow for forming the gate 02 is completely the same as that of the prior art, and will not be repeated here.

Step 2, referring to FIG. 4(b), forming a gate insulating film layer 03 on the gate 02;

For example, a gate insulating film layer 03 with a thickness of about 500-600 nm can be deposited and grown on the gate 02 by plasma enhanced chemical vapor deposition (PECVD).

Step 3, referring to FIG. 4(c), the gate insulating film layer 03 is planarized by a chemical mechanical planarization process to form a gate insulating layer 04;

Step 4, referring to FIG. 4(d), forming an IGZO film layer 05 on the gate insulating layer 04;

For example, an IGZO film layer 05 with a thickness of about 400-500 nm can be deposited on the gate insulating layer 04 by means of magnetron sputtering.

Step 5, referring to Fig. 4 (e), form two mutually spaced grooves 06 in the IGZO film layer 05 by a patterning process;

Wherein, the depth of the groove 06 is about 200-300 nm.

Step 6, referring to FIG. 4(f), forming a metal film layer 07 on the IGZO film layer 05 formed with the groove 06;

For example, a metal film layer 07 with a thickness of about 400-600 nm can be deposited on the IGZO film layer 05 formed with the groove 06 by means of magnetron sputtering or the like.

Step 7, referring to FIG. 4(g), remove all the metal film layers 07 except the metal film layers 07 in the two grooves 06 through chemical mechanical planarization process, and remove the metal film layers 07 in the two grooves 06 Respectively as source 08 and drain 09;

Wherein, the polishing liquid used in the chemical mechanical planarization process in the step of removing the metal film layer 07 is an alkaline non-abrasive polishing liquid.

Step 8, referring to FIG. 4( h ), for the IGZO film layer 05 formed with the source electrode 08 and the drain electrode 09 , an active layer 010 is formed through a patterning process.

Based on the same inventive concept, an embodiment of the present application also provides an array substrate, see Fig. 5-Fig. Schematic diagram of the structure of the array substrate when the type thin film transistor is used, the array substrate includes: the thin film transistor 51 provided by any embodiment of the present application (as shown in the dotted line box in Fig. 5 and Fig. 6 ), the passivation layer 52 disposed above the thin film transistor 51 , and the pixel electrode 53 electrically connected to the drain 511 of the thin film transistor 51 .

Wherein, the material of the passivation layer 52 may be, for example, one or a combination of silicon oxide (SiO _x ) and silicon nitride (SiN _x ).

In a preferred implementation manner, as shown in FIG. 5 and FIG. 6 , the pixel electrode 53 may be disposed above the passivation layer 52 , and electrically connected to the drain 511 of the thin film transistor 51 through the via hole 54 .

In summary, in the technical solution provided by the embodiment of the present application, the thin film transistor includes: a gate, a gate insulating layer, an active layer, a source and a drain, and two recesses spaced apart from each other are arranged in the active layer. Groove, the source and the drain are respectively arranged in the two grooves, since there is no etching stopper layer between the active layer and the source and drain, so the photolithography process will not be increased when making the thin film transistor, Moreover, the source and the drain are respectively arranged in two grooves spaced apart from each other in the active layer. On the one hand, the source and the drain are not formed by etching when making the thin film transistor, so that there will be no corrosion due to etching. On the other hand, the thin film transistor is relatively flat and has few steps, so that the yield rate of the thin film transistor is high.

Obviously, those skilled in the art can make various changes and modifications to the application without departing from the spirit and scope of the application. In this way, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims (10)

1. A kind of thin-film transistor, comprises: gate, gate insulating layer, active layer, source electrode and drain electrode, it is characterized in that, two mutually spaced grooves are arranged in the described active layer, described source electrode and the drain are respectively arranged in the two grooves. 2. The thin film transistor according to claim 1, wherein the source electrode and the drain electrode are flush with the upper surface of the active layer. 3. The thin film transistor according to claim 1 or 2, wherein the groove penetrates through the active layer in a thickness direction. 4 . The thin film transistor according to claim 3 , wherein the material of the active layer is metal oxide, and the metal oxide is InGaZnO. 5. An array substrate, characterized by comprising: the thin film transistor according to any one of claims 1 to 4, a passivation layer disposed above the thin film transistor, and a drain electrode connected to the thin film transistor. connected to the pixel electrode. 6. A method for preparing a thin film transistor, comprising: Forming a semiconductor film layer on the substrate; forming two mutually spaced grooves in the semiconductor film layer through a patterning process; forming a metal film layer on the semiconductor film layer formed with grooves; removing all the metal film layers except the metal film layers in the two grooves by a chemical mechanical planarization process, and using the metal film layers in the two grooves as source and drain electrodes respectively; An active layer is formed through a patterning process for the semiconductor film layer on which the source electrode and the drain electrode are formed. 7. The method for preparing a thin film transistor according to claim 6, wherein the formation of a metal film layer on the semiconductor film layer formed with grooves specifically comprises: A metal film layer having a thickness not smaller than the maximum depth of the groove is formed on the semiconductor film layer on which the groove is formed. 8. The method for preparing a thin film transistor according to claim 6 or 7, characterized in that the polishing solution used in the chemical mechanical planarization process in the step of removing the metal film layer is an alkaline non-abrasive polishing solution. 9. The method for preparing a thin film transistor according to claim 8, wherein the patterning process forms two mutually spaced grooves in the semiconductor film layer, specifically comprising: Two grooves spaced apart from each other and penetrating through the semiconductor film layer are formed in the semiconductor film layer through a patterning process. 10. The preparation method of the thin film transistor according to claim 6 or 7, characterized in that, before forming the semiconductor film layer, or after forming the active layer, the method further comprises: forming a gate insulating film layer on the substrate; The gate insulating film layer is planarized by a chemical mechanical planarization process to form a gate insulating layer.