CN107424996B

CN107424996B - Bonded SADP fins for semiconductor devices and methods of making the same

Info

Publication number: CN107424996B
Application number: CN201710291608.8A
Authority: CN
Inventors: 尼古拉斯·文森特·利考西; E·S·科扎尔斯基; 古拉密·波奇
Original assignee: GlobalFoundries Inc
Current assignee: GlobalFoundries US Inc
Priority date: 2016-04-28
Filing date: 2017-04-28
Publication date: 2020-12-18
Anticipated expiration: 2037-04-28
Also published as: TWI667771B; US9691775B1; TW201806131A; CN107424996A

Abstract

The present invention relates to bonded SADP fins for semiconductor devices and methods of fabricating the same, the semiconductor cells including a substrate, and an array of at least five substantially parallel fins disposed on the substrate with substantially equal fin widths. At least one pair of adjacent fins in the array includes a predetermined minimum separation distance therebetween. The array has first n-type fins for n-type semiconductor devices and first p-type fins for p-type semiconductor devices. The first p-type fin is disposed adjacent to the first n-type fin and is spaced apart from the first n-type fin by a predetermined first n-to-p distance. The first n-to-p distance is greater than the minimum separation distance and less than the sum of the fin width plus twice the minimum separation distance.

Description

Bonded SADP fins for semiconductor devices and methods of making the same

Technical Field

The invention relates to a semiconductor device and a manufacturing method thereof. More particularly, the present invention relates to combinatorial self-aligned double patterning for semiconductor devices and methods of fabricating the same.

Background

Fabrication techniques for semiconductor devices, such as transistors, capacitors, and the like, have been developed for ultra-high density integrated circuits with patterning resolution that exceeds existing lithography (which is typically limited to about 80nm pitch). Self-aligned multiple patterning is one such high resolution patterning technique. Current multiple patterning technology, in terms of commercial production considerations, is a method known as self-aligned four patterning (SAQP), which is an extrapolation of the commercially common self-aligned double patterning (SADP) technique.

The theoretical minimum regular pitch of SAQP is about 20 nanometers (nm) using existing lithography techniques, which can cause problems. In addition, the variable spacing or interval between fins in a fin field effect transistor (FinFET) is very difficult to achieve with the requirements of sapp. This is particularly the case when the pitch (i.e., the distance between repeating features in a semiconductor device structure) is less than or equal to 32 nm. More specifically, when the spacing between fins is equal to or less than 24nm, it is more difficult to achieve variable spacing between fins in an array of five or more fins using existing SAQPs.

The lack of variability in the fabrication of various semiconductor devices utilizing fin arrays having both n-type and p-type fins poses a significant problem. This is because the minimum separation distance (n-to-p separation distance) between n-type fins and p-type fins is necessarily greater than the distance between a pair of n-type fins, and therefore, the fin array needs to be somewhat variable or unnecessarily large in size. Such devices requiring both n-type and p-type finfets are Static Random Access Memory (SRAM) cells and other similar logic cells.

Therefore, there is a need for a method of fabricating a semiconductor device that can make the pitch more variable using standard photolithography. It is desirable to be able to apply this technique to semiconductor devices having fin pitches equal to or less than 32nm, and to semiconductor devices having fin pitches equal to or less than 24 nm. There is a particular need to be able to apply this technique to the fabrication of SRAM cells. In addition, there is a need for a method of fabricating semiconductor devices with pitches of 20nm or less.

Furthermore, there is a substantial need for the ability to cut a single fin among a large number of fins without damaging adjacent fins. This is particularly challenging with pitch approximately equal to or less than 32nm as the fin pitch scales.

Disclosure of Invention

The present invention provides advantages and alternatives over the prior art by providing a semiconductor cell or similar structure and method of implementing the same. The semiconductor cell can be fabricated using standard photolithography to achieve more variable spacing between fins in an array, even when the fin spacing is equal to or less than 24nm, or the fin array is large. In addition, the present invention enables fins to be cut in an array of fins containing three or more fins. This can be achieved by a continuous fin formation and cutting process, which can be used for both SRAM-like cells and random logic cells.

Semiconductor cells according to one or more aspects of the invention include a substrate, and an array including at least five substantially parallel fins disposed on the substrate with substantially equal fin widths. At least one pair of adjacent fins in the array includes a predetermined minimum separation distance therebetween. The array also includes first n-type fins for n-type semiconductor devices and first p-type fins for p-type semiconductor devices. The first p-type fin is disposed adjacent to the first n-type fin and is spaced apart from the first n-type fin by a predetermined first n-to-p distance. The first n-to-p distance is greater than the minimum separation distance and less than the sum of the fin width plus twice the minimum separation distance.

A method according to one or more aspects of the present invention includes providing a structure including a hardmask layer disposed over a substrate, and a first mandrel layer disposed over the hardmask layer. A first mandrel array is patterned into the first mandrel layer. A first array of spacers is formed on sidewalls of the first mandrels. A pattern layer disposed over the first array of spacers, an etch stop layer disposed over the pattern layer, and a second mandrel layer disposed over the etch stop layer. A second mandrel array is patterned into the second mandrel layer. A second array of spacers is formed on sidewalls of the second mandrels. The second array of spacers is etched into the pattern layer such that the second spacers combine with the first spacers and the first and second spacers form a pattern for the array of fins disposed on the hardmask layer. The pattern is etched into the substrate to form the array of fins.

Drawings

The present invention will become more fully understood from the detailed description given herein below, taken in conjunction with the accompanying drawings, wherein:

FIG. 1A is a side view of an exemplary embodiment of a prior art SAQP fabrication method for a semiconductor structure in an intermediate stage of fabrication with a first spacer layer conformally disposed over an array of lithographically patterned mandrels;

FIG. 1B is a side view of the prior art FIG. 1A with first spacers formed on the sidewalls of the mandrels;

FIG. 1C is a side view of the prior art FIG. 1B with the mandrel removed;

FIG. 1D is a side view of the prior art FIG. 1C conformally coating the first spacers with a second spacer layer;

FIG. 1E is a side view of the prior art FIG. 1D with second spacers formed on sidewalls of the first spacers;

FIG. 1F is a side view of the prior art FIG. 1E with the first spacer removed;

figure 2 is a top view of a prior art SRAM cell;

figure 3 is a block flow diagram of a method for forming variably spaced semiconductor cells or similar structures in accordance with the present invention;

FIG. 4A is a side view of an initial stack of layers for a structure including a substrate, a hardmask layer, a first mandrel layer, and a first etch stop layer, in accordance with the present invention;

FIG. 4B is a perspective view of FIG. 4A, according to the present invention;

FIG. 5 is a side view of FIG. 4B patterning a first mandrel into a first photoresist layer, in accordance with the present invention;

FIG. 6 is a side view of FIG. 5 with the first mandrel etched into the first mandrel layer, in accordance with the present invention;

FIG. 7 is a side view of FIG. 6 conformally coating a first mandrel with a first spacer layer, according to the present invention;

FIG. 8 is a side view of FIG. 7 with first spacers formed on sidewalls of the first mandrels, in accordance with the present invention;

FIG. 9 is a side view of FIG. 8 with the first mandrel removed, in accordance with the present invention;

FIG. 10A is a side view of FIG. 9 having a first planarizing layer, a second etch stop layer, and a second photoresist layer disposed thereon, wherein a scale region of the second etch stop layer is exposed in accordance with the present invention;

FIG. 10B is a perspective view of FIG. 10A, according to the present invention;

FIG. 11 is a side view of FIG. 10A with selected sections of the first spacer exposed and removed, in accordance with the present invention;

FIG. 12 is a side view of FIG. 11 with the first planarizing layer removed, the pattern layer disposed over the first spacers, and the second mandrel layer disposed thereon, in accordance with the present invention;

FIG. 13 is a side view of FIG. 12 having a second mandrel patterned thereon, in accordance with the present invention;

FIG. 14 is a side view of FIG. 13 with a second mandrel etched into a second mandrel layer, in accordance with the present invention;

FIG. 15 is a side view of FIG. 14 conformally coating a second mandrel with a second spacer layer, according to the present invention;

FIG. 16 is a side view of FIG. 15 with second spacers formed on sidewalls of the second mandrels, in accordance with the present invention;

FIG. 17 is a side view of FIG. 16 with the second mandrel removed, in accordance with the present invention;

FIG. 18A is the side view of FIG. 17 with the second planarization layer, the fourth etch stop layer, and the second layer of photoresist disposed thereon, wherein a scaled section of the fourth etch stop layer is exposed in accordance with the present invention;

FIG. 18B is a perspective view of FIG. 18A, in accordance with the present invention;

FIG. 19 is a side view of FIG. 18A with selected segments of the second spacers exposed and removed, in accordance with the present invention;

FIG. 20 is a side view of FIG. 19 with the second planarizing layer removed, in accordance with the present invention;

fig. 21 is a side view of fig. 20 with second spacers etched into the pattern layer to form a fin pattern in accordance with the present invention;

FIG. 22 is a side view of FIG. 21 etching a first pattern into the hardmask in accordance with the invention; and

figure 23 is a side view of figure 22 etching a pattern into a substrate to form an SRAM cell, in accordance with the present invention.

Description of the main component symbols:

10. 100 structure

12. 22, 129, 162 spacer layer

14. 118, 154 mandrel

16. 104 hard cover layer

18. 102 substrate

20. 24, 26, 28, 30, 130, 164 spacers

32. 36 space apart

34 space

40. 202 SRAM cell

42. 44, 56, 58 n type fin

46. 48, 50, 52, 54 fins

60. 62, 64 transverse incision

Block 80 flow diagram

82. 84, 86, 88, 90, 92, 94, 96, 98 modules

106. 148 mandrel layer

108. 134, 146, 170 etch stop layer

110 hard mask layer

112 second hard mask layer

120. 138, 150, 174 photoresist layer

122. 136, 152, 172 BARC layer

124. 156 spindle width

126. 158 mandrel spacing

127. 131, 166 average distance

132. 168 planarization layer

139. 176 scaling section

142. 178 selected section

143. 179 notch

144 patterned layer

160 spindle pitch

180 fin pattern

190. 192, 194, 196, 198, 200 fins

194A, 194B, 194C, 196A, 196B fin portions

204 minimum separation distance

Distance 206

208 p to p.

Detailed Description

Certain exemplary embodiments will now be described to provide an overall understanding of the principles of the structure, function, manufacture, and use of the methods, systems, and devices disclosed herein. One or more examples of these embodiments are illustrated in the accompanying drawings. Those skilled in the art will understand that the methods, systems, and apparatus specifically described herein and illustrated in the accompanying drawings are non-limiting exemplary embodiments and that the scope of the present invention is defined solely by the claims. Features illustrated or described in connection with one exemplary embodiment may be combined with features of other embodiments. Such modifications and variations are intended to be included within the scope of the present invention.

Fig. 1A-1F illustrate a typical prior art SAQP method for semiconductor fabrication. Figure 2 illustrates a typical prior art SRAM cell including n-type, p-type fins, and dummy fins.

Referring to fig. 1A-1F, an exemplary embodiment of a prior art sequential method of SAQP fabrication is shown. Starting with fig. 1A, in an intermediate manufacturing stage, the structure 10 is conformally (conformamally) disposed with a first spacer layer 12 over an array of lithographically patterned mandrels 14 having a predetermined line density and pitch. In this exemplary embodiment, the mandrel is disposed over the hardmask layer 16, and the hardmask layer 16 is disposed over the substrate 18.

Referring to fig. 1B, the first spacer layer 12 is then anisotropically etched to form a first array of first spacers 20 on the sidewalls of the mandrels 14. Referring to fig. 1C, the mandrels 14 are then removed, and the first array of spacers 20 is then anisotropically etched into the hardmask 16. To date, this procedure is no different than the typical SADP procedure. Since there are two spacers 20 for each mandrel 14, the line density is doubled and the pitch is halved.

Starting with fig. 1D, the first part of the SAQP program flow is repeated over the first array of spacers 20. That is, the second spacer layer 22 is arranged over the first array of spacers 20. Next, referring to fig. 1E, the second spacer layer 22 is anisotropically etched to form a second array of

spacers

24, 26, 28, and 30. Finally, referring to fig. 1F, the first array of spacers 20 is then removed, leaving only the second array of spacers 20-30, which will be patterned to etch the fins into the substrate 18. Since there are four spacers 24-30 for each mandrel 14, the linear density is quadrupled and the pitch has become one-fourth of the original mandrel 14.

It is important to note that the width of the mandrel 14 and the spacing between mandrels are the only variable parameters in the SAQP procedure. The thickness of the first and second spacer layers 12 and 22 cannot be locally adjusted during the deposition process and is not considered a variable parameter across the wafer. As such, the spacing 32 on either side of the group of four spacers 24-30 is referred to herein as the ajar space (α) because it is variable as controlled by the spacing between the mandrels 14. In addition, the spacing 36 between the

spacers

26 and 28 is referred to herein as the gamma space (γ) because it is likewise variable as controlled by the width of the mandrel 14. However, the pair of spaces 34 between

spacers

24 and 26, and between

spacers

28 and 30, referred to herein as beta-spaces (β), are rigidly fixed.

Thus, every other space in any fin array created by the SAQP procedure is a fixed beta space 34. This rigidity is more problematic due to the larger number of fin arrays (e.g., thousands or more) and smaller dimensions (e.g., spacing between fins below 24 nm). As a result, prior art cells for semiconductor devices have arrays of fins that are typically spaced at equal distances. If variability is required between fins (e.g., when n-type fins are adjacent to p-type fins), sacrificial dummy fins are typically inserted and then removed during fabrication. However, the use of such sacrificial dummy fins causes the prior art cells to be unnecessarily large in size.

Referring to fig. 2, an exemplary embodiment of a typical prior art SRAM cell 40 fabricated using a conventional sapp process is shown. SRAM cells are typically random access memories that retain data bits in the memory as long as power is supplied. SRAM is typically used in personal computers, workstations, routers, peripherals, and the like.

The SRAM cell 40 includes four n-

type fins

42, 44, 56, and 58 for four n-type finfets (referred to herein as nfets). The SRAM cell 40 also includes two p-

type fins

48 and 52 for two p-type finfets (referred to herein as pfets).

Fins

46, 50, and 54 are sacrificial dummy fins that will be removed prior to forming the FinFET, as explained in more detail herein.

Each bit in the SRAM cell 40 is stored in two adjacent nFET/pFET pairs associated with two n-type/p-type

adjacent fins

44, 48 and 52, 56, respectively, with the finfets interconnected together to form a pair of cross-coupled inverters. The remaining two nfets associated with the remaining two n-

type fins

42, 58 function to control access to the inverters during read and write operations.

Those skilled in the art recognize that there are several other possible configurations of SRAM cells with various interconnected combinations of nfets and pfets. However, each SRAM cell must have at least one nFET adjacent to one pFET, both separated by a predetermined n to p distance.

In this exemplary embodiment, the fins 42-58 (within a tolerance of equal to or less than plus or minus 4nm) have a fixed fin width of 8nm and are spaced at equal distances of 24nm to provide an average pitch of 32 nm. Because fins 42-58 are separated by this small distance, they are fabricated using a SAQP process. As a result, every other space separating the fins 42 to 58 is the fixed beta space 34. In addition, the alpha 32 and gamma 36 spaces alternate between the fixed beta spaces 32. Thus, for any array of at least five substantially parallel fins (e.g., fins 42-50, fins 46-54, or fins 50-58), there will be at least two fixed beta spaces 34 connected to one alpha space 32 and one gamma space 36.

Because of the rigidity introduced by the fixed beta space 34, coupled with the difficulty of adjusting the ajar 32 and gamma 36 spaces at such small scales, and the added complexity of integrating a large number of such SRAM cells with many other devices throughout the ultra-high density integrated circuit logic, it is not cost effective at all, nor technically feasible to fabricate variable-spacing SRAM cells using the existing SAQP methods. Furthermore, even though the rigidity introduced by the fixed beta space 34 becomes significant for an array of at least five parallel fins, where there are still a variety of different types of alpha 32, beta 34, and gamma 36 spaces, this rigidity rapidly becomes greater as the number of fins in the array increases above 5. As a result, fins 42-58 are fabricated with uniform widths and are spaced equidistantly throughout SRAM cell 40.

However, due to the structural differences between the dopant types and the relationship of the epitaxial source/drain regions associated with n-type and p-type finfets, the minimum distance between an n-type fin and an adjacent p-type fin required for function will always be greater than the minimum distance required between a pair of n-type fins. Thus, in order to introduce some variable spacing between fins within the SRAM cell 40,

dummy fins

46 and 54 are disposed between each n-type/p-type fin combination (44, 48 and 52, 56) at an intermediate processing stage. Thus, the n-to-p distance between each n-type/p-type fin pair may be made greater than the minimum separation distance associated with a pair of n-type fins by simply removing the dummy fins. More specifically, once the

dummy fins

46 and 54 are removed, the n-to-p spacing distance in the SRAM cell 40 will be equal to or greater than the sum of the fin width (8 nm in this example) plus twice the minimum spacing distance (24 nm in this example).

In addition to the need for fin spacing variability due to structural differences between n-type and p-type fins, the need for fin spacing variability is also important because it is generally necessary to make

lateral cuts

60, 62, and 64 in the p-type fins of the SRAM cell 40. However, the lithographic tolerances are such that not clipping adjacent fins does not reliably pattern the cuts in the fins at such small dimensions. As such, a dummy fin (fin 50 in this example) is also interposed between any p-type fin pair (

fins

48 and 52 in this example).

Thus, in the example of an SRAM cell 40, for the six

active fins

42, 44, 48, 52, 56, and 58 of the cell, three

dummy fins

46, 50, and 54 are required to allow for n-type to p-type fin structure differences and to allow for the cutting of p-type fins without cutting adjacent fins. Problematically, the use of

dummy fins

46, 50, and 54 increases the number of fins and increases the overall size of the SRAM cell 40 by as much as 50 percent. That is, it is therefore desirable to provide a method of achieving variability between n-type to p-type fin pairs, and n-type fin pairs without using dummy fins. Such requirements are particularly important in SRAM cells or the like.

Fig. 3-23 illustrate various exemplary embodiments of methods and apparatus for implementing variable spacing semiconductor cells or similar structures in accordance with the present invention. The present invention provides more variable parameters than the existing SAQP procedure, thus achieving the goal of spacing variability within the fin array in a cost-effective and technically feasible manner. More specifically, the present invention achieves variability without the use of dummy fins. Also, it is applicable to arrays of five or more fins, with a minimum fin spacing equal to or less than 24nm, and/or a minimum pitch equal to or less than 32 nm.

Referring to fig. 3, a block flow diagram 80 illustrates an exemplary embodiment of a high level overview of a method and apparatus for forming variably spaced semiconductor cells in accordance with the present invention. The module flow diagram 80 includes nine

separate modules

82, 84, 86, 88, 90, 92, 94, 96 and 98, each of which includes several method steps that will be described in detail herein. Briefly, these modules may be described as follows:

the module 82: the initial stack accumulates. (including the steps shown in FIGS. 4A and 4B): in this module, a structure 100 is provided. The structure 100 includes at least one hardmask layer 104 disposed over a substrate 102, and a first mandrel layer 106 disposed over the hardmask layer 104.

The module 84: the first mandrel is patterned. (including the steps shown in fig. 5 to 6): in this module, an array of first mandrels 108 is patterned into the first mandrel layer 106.

The module 86: a first spacer is formed. (including the steps shown in fig. 7 to 9): in this module, a first array of spacers is formed on sidewalls of the first mandrels.

Module 88 (as required): a first incision is formed. (including the steps shown in FIGS. 10A to 11): the module includes disposing a first planarization layer over the first array of spacers. The first planarization layer is then patterned to expose at least one selected first spacer of the first array of spacers. Next, a first cut is etched into the exposed first spacer.

And a module 90: and (5) rebuilding a stack. (including the steps shown in FIG. 12): the module includes depositing a pattern layer over the first array of spacers. An etch stop layer is disposed over the pattern layer. A second mandrel layer is disposed over the etch stop layer.

The module 92: the second mandrel is patterned. (including the steps shown in fig. 13 to 14): this module includes patterning a second mandrel array into the second mandrel layer.

The module 94 is: a second spacer is formed. (including the steps shown in fig. 15 to 17): the module includes forming a second array of spacers on sidewalls of the second mandrel.

Module 96 (optional): a second incision is formed. (including the steps shown in fig. 18A to 19): the module includes a second planarization layer disposed over the second array of spacers. The second planarization layer is then patterned to expose at least one selected second spacer of the first array of spacers. Then, a second cut is etched into the exposed second spacers.

Module 98: the fins are patterned into the substrate. (including the steps shown in fig. 20 to 23): this module includes etching the second array of spacers into the pattern layer such that the second spacers are combined with the first spacers, wherein the first and second spacers are patterned for an array of fins disposed on the hardmask layer 104. The pattern is then etched into the substrate 102 to form the array of fins.

The module 82: the initial stack accumulates. (FIGS. 4A and 4B)

This module details the accumulation of the initial stack of layers in the structure 100, including the mandrel layer 106.

Referring to fig. 4A and 4B, simplified diagrams of an exemplary embodiment of an integrated circuit device according to the present invention having a semiconductor cell structure 100 at an intermediate stage of fabrication are illustrated. The semiconductor cell structure 100 includes a substrate 102 having a hardmask layer 104 disposed thereon. A first mandrel layer 106 is disposed over the hardmask layer 104, and a first etch stop layer 108 may be disposed over the first mandrel layer 106.

The substrate 102 may be comprised of any suitable semiconductor material, such as silicon, silicon germanium, or the like. The hardmask layer 104 is required to etch the fin array (not shown) into the substrate 102. Although at least one hard mask layer 104 is required, the hard mask layer 104 may be composed of several layers. In the exemplary embodiment, the hard mask layer 104 is comprised of a first hard mask layer 110 and a second hard mask layer 112. The first hard mask layer 110 may be silicon dioxide (SiO2) or the like. The second hard mask layer 112 may be silicon nitride (SiN) or the like, which is deposited by a Low Pressure Chemical Vapor Deposition (LPCVD) procedure.

The first mandrel layer 106 may be a spin-on hard mask (SOH) material, such as amorphous carbon (aC) or amorphous silicon (aSi). The first etch stop layer 108 may be silicon oxynitride (SiON) or the like.

The module 84: the first mandrel is patterned. (FIGS. 5 to 6)

This module details the steps required to pattern the array of first mandrels 118 into the mandrel layer 106.

Referring to fig. 5, at least a first photoresist layer 120 is disposed over the first etch stop layer 108. However, it is more likely that a first bottom anti-reflective coating (BARC) layer 122 is disposed over the first etch stop layer 108 and a first photoresist layer 120 is disposed over the first BARC layer 122. The first mandrel 118 is then patterned into the first photoresist layer 120 by well-known photolithography techniques.

In this embodiment, the first mandrels have an average pitch 127 of 128nm, a first mandrel width 124 of 64nm, and a first mandrel spacing 126 of 64 nm. It is important to note, however, that the first mandrel width 124 and spacing 126 are variable parameters that may be used to control variable spacing within the fin array of a semiconductor cell. As such, the mandrels 118 need not be equally spaced or equally wide.

Referring to FIG. 6, the first mandrel 118 is then anisotropically etched from the first photoresist layer 120 into the first mandrel layer 106. The anisotropic etching process may be a reactive ion etching process. For clarity, any feature etched down from an original feature, such as a spacer, mandrel, etc., will be referred to herein as such original feature if it has the same form and function as the original feature. However, it is well known that the down-etched features will be a transfer of the original features and will be composed of residues of the layers involved in the etching process. More specifically, in the case of the first mandrel 118, the original first mandrel 118 is etched into and composed of the resist layer 120 and the BARC layer 122. However, the first mandrel 118 etched down may be composed of the first etch stop layer 108 and the first mandrel layer 106.

The module 86: a first spacer is formed. (FIGS. 7 to 9)

This module details the steps required to form the first spacers on the sidewalls of the mandrels 118.

Referring to fig. 7, a first spacer layer 128 is conformally coated over the first mandrel 118. The first spacer layer may be an oxide layer, such as SiO2, and may be coated over the first mandrel 118 by an Atomic Layer Deposition (ALD) procedure.

Referring to fig. 8, the first spacer layer 128 is anisotropically etched to form first spacers 130 on sidewalls of the first mandrels 118. Since there are two spacers 130 per mandrel 118, the average spacing 131 between the first spacers 130 is half the spacing 127 (best seen in FIG. 5) between the first mandrels 118.

Referring to FIG. 9, the first mandrels 118 are then removed, leaving only the first spacers 130 over the hard mask layer 104. The mandrels 118 may be removed by any of several well-known procedures, such as a wet etch procedure, a RIE procedure, or the like.

Additionally, although fig. 8 and 9 are shown as two separate steps, both can generally be accomplished with the same procedure. For example, a RIE etch process may be employed to first etch the first spacers 130 with a first type of gas, and then a second type of gas may be introduced during the same process to remove the first mandrels 118.

Module 88 (as required): a first incision is formed. (FIGS. 10A to 11)

This optional module details a method of etching at least a first cut into the first spacer 130.

Referring to fig. 10A and 10B, a first planarization layer 132 is disposed over the array of first spacers 130, and a second etch stop layer 134 is disposed over the first planarization layer 132.

The first planarizing layer 132 may be composed of a SOH material (e.g., amorphous carbon or amorphous silicon) as the first mandrel layer 106. In this manner, the first mandrel 118 need not be removed prior to disposing the first planarizing layer 132. However, the mandrels 118 may harden or break to some extent during processing, and it is therefore desirable to completely remove the first mandrel 118, and begin with the recently deposited planarization layer 132.

Next, a second BARC layer 136 and a second photoresist layer 138 are disposed over the second etch stop layer 134. Photoresist layer 138 and BARC layer 136 are then patterned to expose at least one scale region 139 of second etch stop layer 134. As can be seen most clearly in FIG. 10B, in this particular embodiment, photoresist layer 138 and BARC layer 136 have been patterned to expose two scale segments 139.

Referring to fig. 11, the second etch stop layer 134 and the first planarization layer 132 are then patterned to expose at least one selected segment 142 (two selected segments 142 in this particular embodiment) of the first spacers 130 of the array of first spacers 130. At least one first cut 143 (in this case a pair of first cuts 143, best seen in fin pattern 180 of fig. 23) is then etched into the exposed selected segments 142 of the first spacers 130 to remove the exposed selected segments 142.

In this particular embodiment, the pair of first cutouts 143 (subject to the removed selected section 142) divide the scaled first spacer 130 into three spacer portions. The scaling spacers may be used later to form p-type fins for p-type finfets or similar p-type semiconductor devices. In addition, the first cutout 143 may be a plurality of cutouts on a plurality of spacers having various different lengths. It is important to note that the pitch dimension of this dimension (64 nm in this example) is large enough to allow photolithographic patterning of a single exposed spacer 130 without clipping of adjacent spacers.

And a module 90: and (5) rebuilding a stack. (FIG. 12)

This module reconstructs the stack of layers in detail to include the second mandrel layer 148.

Referring to fig. 12, the first planarization layer 132 and the second etch stop layer 134 are removed by well-known procedures to expose the array of first spacers 130. Next, a recently planarized pattern layer 144 is disposed over the array of first spacers 130. A third etch stop layer 146 is disposed over the patterning layer 144 and a second mandrel layer 148 is disposed over the third etch stop layer 146. The patterning layer 144 and the second mandrel layer 148 may be amorphous silicon, amorphous carbon, or the like. The third etch stop layer 146 may be SiON or the like.

The module 92: the second mandrel is patterned. (FIGS. 13 to 14)

This module details the patterning of an array of second mandrels 154 into the second mandrel layer 148.

Referring to FIG. 13, a third photoresist layer 150 and optionally a third BARC layer 152 are disposed over the second mandrel layer 148. Second mandrels 154 are then patterned into third photoresist layer 150 by well-known photolithography techniques.

In this embodiment, the second mandrels have an average second mandrel spacing 160 of 128nm, a second mandrel width 156 of 64nm, and a second mandrel spacing 158 of 64 nm. It is important to note, however, that the second mandrel width 156 and spacing 158 are variable parameters that may be used to control variable spacing within the fin array of a semiconductor cell. As such, the second mandrels 154 need not be equally spaced or equally wide. It is important to note that the position of the second mandrel 154 relative to the position of the original first mandrel 118 is also a variable parameter that may be used to control the spacing between the fins of the semiconductor cell.

It is helpful to compare the present invention with the prior art SAQP process as described with reference to prior art FIGS. 1A-1F, that only two variable parameters for controlling fin spacing can be seen in the present SAQP process, and as many as five variable parameters for doing the same. That is, in the conventional SAQP procedure, the two variable parameters are the width of the single mandrel array and the spacing between the single mandrel arrays.

In contrast, in the present invention, the first mandrel width 124 and first mandrel spacing 126 of the first mandrel 118, the second mandrel width 156 and second mandrel spacing 158 of the second mandrel 154, and the relative position between the first 118 and second 154 mandrels contain a set of five variable parameters. This set of five variable parameters may be used to provide variable fin spacing between fins of a fin array for a semiconductor cell.

As a result, the process according to the present invention provides more continuous and cost-effective variability in the spacing between fins of a semiconductor cell. The present invention maintains this variability even at small scales, such as: the spacing between the fins is equal to or less than 24nm, the fins have a width equal to or less than 8nm (where the fin width has a tolerance of equal to or less than plus or minus 4nm), and the array of fins have a pitch equal to or less than 32 nm. In addition, the need for dummy fins is avoided.

Furthermore, the present invention maintains variability in an array of five or more fins. This is because, unlike prior art SAQP methods (like the beta space 34 shown in FIG. 2) where every other space in the array is a non-variable beta space, the five variable parameters of the present invention provide continuous variability for almost every space in the array.

Referring to fig. 14, a second mandrel 154 is then anisotropically etched into the second mandrel layer 148. The anisotropic etching process may be a reactive ion etching process.

The module 94 is: a second spacer is formed. (FIGS. 15 to 17)

This module details the formation of a second array of spacers in the sidewalls of the second mandrel 154.

Referring to fig. 15, a second spacer layer 162 is conformally coated over the second mandrel 154. The second spacer layer 162 may be an oxide layer, such as SiO2, and may be coated over the second mandrels 154 by an Atomic Layer Deposition (ALD) procedure.

Referring to fig. 16, the second spacer layer 162 is anisotropically etched to form second spacers 164 on sidewalls of the second mandrels 154. Since there are two second spacers 164 per second mandrel 154, the average spacing 166 between the second spacers 164 is half the spacing 160 (best seen in FIG. 13) between the second mandrels 154.

Referring to fig. 17, the second mandrels 154 are then removed, leaving only the second spacers 164 on the third etch stop layer 146. The mandrels 154 may be removed by any of several well-known procedures, such as a wet etch procedure, a RIE procedure, or the like.

Additionally, although fig. 16 and 17 are shown as two separate steps, both may generally be accomplished with the same procedure. For example, a RIE etch process may be employed to first etch the second spacers 164 with a first type of gas, and then a second type of gas may be introduced during the same process to remove the second mandrel 154.

Module 96 (optional): a second incision is formed. (FIGS. 18A to 19)

This optional module details a method of etching at least a second cut into the second spacers 164.

Referring to fig. 18A and 18B, a second planarization layer 168 is disposed over the array of second spacers 164, and a fourth etch stop layer 170 is disposed over the second planarization layer 168.

The second planarizing layer 168 may be composed of the same SOH material (e.g., amorphous carbon or amorphous silicon) as the second mandrel layer 148. As such, the second mandrels 154 can be removed without first disposing the second planarizing layer 168. However, because the second mandrels 154 may be hardened or damaged to some extent during processing, it is desirable to completely remove the mandrels 154 and begin with the recently deposited second planarizing layer 168.

Next, a fourth BARC layer 172 and a fourth photoresist layer 174 are disposed over the fourth etch stop layer 170. Fourth photoresist layer 174 and fourth BARC layer 172 are then patterned to expose at least one scale region 176 of fourth etch stop layer 170.

Referring to fig. 19, the fourth etch stop layer 170 and the second planarization layer 168 are then patterned to expose at least a selected segment 178 of the second spacers 164 of the array of second spacers 164. At least one second cut 179 (best seen in fin pattern 180 of fig. 23) is then etched into the exposed selected segments 178 of the second spacers 164 to remove the exposed selected segments 178.

In this particular embodiment, the second cutout 179 (subject to the removed segment 178) distinguishes the scaled second spacer 164 into two spacer portions. The scaling spacers 164 may be used later to form p-type fins for p-type finfets or similar p-type semiconductor devices. Additionally, the second cut may be a plurality of cuts on a plurality of spacers having various lengths.

It is important to note that the pitch dimension of this dimension (64 nm in this example) is large enough to allow photolithographic patterning of a single exposed spacer 164 without clipping of adjacent spacers. It is important to note that the first cut 143 (the selected section 142 of the first spacer 130 that was subject to removal) and the first array of spacers 130 are retained by the third etch stop layer 146. Furthermore, the methods described in modules 88 and 96, which form first cutout 143 and second cutout 179, respectively, enable a single fin to be cut out of a large number of fins without damaging adjacent fins, even for fin pitches equal to or less than 32 nm.

Module 98: the fins are patterned into the substrate. (FIGS. 20 to 23)

This module details interleaving the first 130 and second 164 spacers to form a pattern in the patterning layer 144, and subsequently using the pattern to etch the fins into the substrate 102.

Referring to fig. 20, the second planarization layer 168 and the fourth etch stop layer 170 are then removed, leaving only the second spacers 164 on the third etch stop layer 146. The second planarizing layer 168 and the fourth etch stop layer 170 can be removed by any of several well-known procedures, such as a wet etch procedure, a RIE procedure, or the like.

Referring to fig. 21, next, the array of second spacers 164 is anisotropically etched into the pattern layer 144 such that the second spacers 164 are combined with the first spacers 130. The first 130 and second 164 spacers now form a fin pattern 180 over the fin array on the hardmask layer 104. The anisotropic etching process may be a reactive ion etching process. For clarity, the second spacers 164, which are now etched onto the pattern layer 144 and disposed over the hard cap layer 104, are so referred to because they have the same form and function as the original second spacers 164, which are disposed over the third etch stop layer 146. However, it is well known that the second spacers 164, now on the hardmask layer 104, are transferred from the original second spacers 164 by an anisotropic etching process and will be composed of residues of the layers involved in the etching process. More specifically, the second spacer 164 now on the hardmask layer 104 may be composed of the original second spacer 164, the third etch stop layer 146, and the residue of the patterning layer 144.

It is important to note that the first 130 and second 164 spacers may be combined in a number of different ways to form the fin pattern 180. For example, but not limiting of, the first 130 and second 164 spacers may be staggered, alternated, arranged in specific groups or any combination thereof. Further, the first 130 and second 164 spacers may be combined to form a fin pattern 180 ranging in size from as little as two fins to hundreds of fins and more.

Referring to fig. 22, the fin pattern 180 is then anisotropically etched down through the two

sub-layers

110, 112 of the hardmask layer 104. This pattern is now disposed on the substrate 102 and is ready to be used to form fins within the substrate 102.

Referring to fig. 23, fin pattern 180 is etched into substrate 102 to form an array of

fins

190, 192, 194, 196, 198, and 200 (i.e., 190-200). In the present embodiment, the array of fins 190-200 forms a semiconductor SRAM cell 202.

SRAM cell 202 is similar to prior art SRAM cell 40 in that there are alternating pairs of n-type fins and p-type fins. Specifically,

fins

190, 192, 198, and 200 are n-type fins, and

fins

194 and 196 are p-type fins. In addition, the cutouts are arranged in the p-type fin 194, which divides the fin 194 into three

fin portions

194A, 194B, and 194C. Also, the cutout 179 is disposed in the p-type fin 196, which divides the fin 196 into two

fin portions

196A and 196B. All fins 190-200 have equal fin widths. In this particular embodiment, the fin width is set to 8nm with a tolerance equal to or less than plus or minus 4 nm.

As with the prior art SRAM cell 40, the minimum separation distance 204 is the distance between n between pairs of n-type fins, which is set to 24nm for this particular embodiment. That is, there is a minimum separation distance of 24nm between the pair of n-type fins 190/192 and 198/200. The n-to-p spacing distance is the distance between adjacent pairs of n-type and p-type fins 192/194 and 196/198, which must be greater than the minimum spacing distance 204.

Unlike the prior art SRAM cell 40, however, the spacing between the fins 190-200 of the SRAM cell 202 is not fixed. This is due to the set of five variable parameters for the variable fin spacing between any of the fins 190-200 of the SRAM cell 202. As described in particular reference to block 92, these five variable parameters are:

a. a first mandrel width 124 of the first mandrel 118;

b. a first spindle spacing 126 of the first spindle 118;

c. a second spindle width 156 of the second spindle 154;

d. a second spindle spacing 158 of the second spindle 154; and

e. the relative position between the first 118 and second 154 mandrels.

Thus, the n-to-p distance in the SRAM cell 202 may be set smaller than in the prior art SRAM cell 40. More specifically, because the SRAM cell 40 must achieve its fin spacing variability through the formation and removal of sacrificial dummy fins, the n-to-p spacing in the SRAM cell 40 must be equal to or greater than the sum of the fin width plus twice the minimum spacing distance (which, in this embodiment, amounts to 56nm plus or minus 4 nm). In contrast, the n-to-p distance 206 of the SRAM cell 202 is not limited and can be set small, such as 1.5 times the minimum separation distance (which, in this embodiment, amounts to 36 nm).

In addition, the p-to-p distance 208 between p-type fins 194/196 is also substantially greater than the minimum separation distance 204 between n-type fins. In the prior art SRAM cell 40, since the prior art SRAM cell 40 can only achieve spacing variability through dummy fin removal, this p-to-p distance also must be equal to or greater than the sum of the fin width plus twice the minimum spacing distance. Again, in contrast, the p-to-p distance in the SRAM cell 202 can be set smaller.

While the invention has been described with reference to specific embodiments, it should be understood that numerous changes could be made within the spirit and scope of the inventive concepts described. Accordingly, it is intended that the invention not be limited to the particular embodiment disclosed, but that it have the full scope defined by the contents of the following claims.

Claims

1. A semiconductor cell, comprising:

a substrate; and

an array of at least five substantially parallel fins disposed on the substrate with substantially equal fin widths, at least one pair of adjacent fins in the array including a predetermined minimum separation distance therebetween, wherein the minimum separation distance is a distance between opposing sides of the adjacent fins, the array comprising:

a first n-type fin for an n-type semiconductor device, and

a first p-type fin for a p-type semiconductor device, the first p-type fin positioned adjacent to the first n-type fin and spaced apart from the first n-type fin by a predetermined first n-to-p distance,

wherein the first n-to-p distance is a distance between two opposite sides of the first n-type fin and the first p-type fin, the first n-to-p distance being greater than the minimum separation distance and less than a sum of the fin width plus twice the minimum separation distance.

2. The semiconductor cell of claim 1, wherein the first p-type fin comprises a lateral cut through the first p-type fin.

3. The semiconductor cell of claim 1, wherein the array comprises:

a first pair of n-type fins including the first n-type fin; and

a first pair of p-type fins including the first p-type fin;

wherein a distance between fins of the first pair of n-type fins is substantially the minimum separation distance, an

Wherein a distance between the first pair of n-type fins and the first pair of p-type fins is the first n-to-p distance.

4. The semiconductor cell of claim 3, wherein the array has at least six substantially parallel fins disposed on the substrate at the substantially equal fin width, the array comprising:

a second pair of n-type fins disposed adjacent to the first pair of p-type fins and spaced apart from the first pair of p-type fins by a predetermined second n-to-p distance;

wherein a distance between fins of the second pair of n-type fins is substantially the minimum separation distance, and

wherein the second n-to-p distance is less than the sum of the fin width plus twice the minimum separation distance.

5. The semiconductor cell of claim 1, wherein the semiconductor cell is a Static Random Access Memory (SRAM) cell.

6. The semiconductor cell of claim 1, wherein the minimum separation distance is equal to or less than 24 nm.

7. The semiconductor cell of claim 1, wherein the fin width is equal to or less than 8nm, the fin width having a tolerance of no greater than plus or minus 4 nm.

8. The semiconductor cell of claim 1, wherein the first n-to-p distance is less than 56 nm.

9. A method of fabricating a semiconductor device, comprising:

providing a structure comprising a hardmask layer disposed over a substrate, and a first mandrel layer disposed over the hardmask layer;

patterning a first mandrel array into the first mandrel layer;

forming a first array of spacers on sidewalls of the first mandrels;

disposing a pattern layer over the first spacer array, an etch stop layer over the pattern layer, and a second mandrel layer over the etch stop layer;

patterning a second mandrel array into the second mandrel layer;

forming a second array of spacers on sidewalls of the second mandrel;

etching the second spacer array into the pattern layer such that the second spacers combine with the first spacers, the first and second spacers forming a pattern for the array of fins disposed on the hardmask layer; and

the pattern is etched into the substrate to form the array of fins.

10. The method of claim 9, wherein the first mandrel width and first mandrel spacing of the first mandrel, the second mandrel width and second mandrel spacing of the second mandrel, and the relative position between the first and second mandrels are a set of five variable parameters, the method comprising:

variable fin spacing is provided between fins of the array of fins using the set of five variable parameters.

11. The method of claim 9, comprising:

disposing a first planarizing layer over the first spacer array prior to the step of disposing the pattern layer over the first spacer array;

patterning the first planarization layer to expose selected sections of first spacers of the first array of spacers; and

a first cut is etched into the selected section where the first spacer has been exposed.

12. The method of claim 11, comprising removing the first mandrel prior to the step of disposing the first planarizing layer.

13. The method of claim 11, comprising forming a p-type fin for a p-type semiconductor device from the first spacer.

14. The method of claim 9, comprising:

before the step of etching the second array of spacers into the pattern layer, first disposing a second planarization layer over the second spacers;

patterning the second planarization layer to expose selected second spacers of the second array of spacers; and

a second cut is etched into the exposed second spacers.

15. The method of claim 14, comprising removing the second mandrel prior to the step of disposing a second planarizing layer.

16. The method of claim 14, comprising forming p-type fins for p-type semiconductor devices from the second spacers.

17. The method of claim 9, wherein the fin array formed by the etching step comprises:

an array of at least five substantially parallel fins disposed on the substrate with substantially equal fin widths, at least one pair of adjacent fins within the array of fins comprising a predetermined minimum separation distance therebetween, the array of fins comprising:

a first n-type fin for an n-type semiconductor device, and

wherein the first n-to-p distance is greater than the minimum separation distance and less than the sum of the fin width plus twice the minimum separation distance.

18. The method of claim 17, wherein the fin array formed by the etching step comprises:

a first pair of n-type fins including the first n-type fin; and

a first pair of p-type fins including the first p-type fin;

19. The method of claim 17, wherein:

the minimum separation distance is equal to or less than 24 nm; and

the fin width is equal to or less than 8nm, the fin width having a tolerance of no greater than plus or minus 4 nm.

20. The method of claim 16, wherein the array of fins formed by the etching step comprises an array of fins for Static Random Access Memory (SRAM) cells.