CN107424955B - Manganese barrier and adhesion layers for cobalt - Google Patents

Manganese barrier and adhesion layers for cobalt Download PDF

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Publication number
CN107424955B
CN107424955B CN201710337590.0A CN201710337590A CN107424955B CN 107424955 B CN107424955 B CN 107424955B CN 201710337590 A CN201710337590 A CN 201710337590A CN 107424955 B CN107424955 B CN 107424955B
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cobalt
substrate
feature
manganese
layer
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CN107424955A (en
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黎照健
罗郑硕
拉什纳·胡马雍
迈克尔·达内克
凯寒·阿比迪·阿施蒂尼
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Lam Research Corp
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    • H01L2924/01027Cobalt [Co]

Abstract

The invention relates to manganese barrier and adhesion layers for cobalt. The present invention provides methods of forming conductive cobalt (Co) interconnects and Co features. The method includes depositing a manganese (Mn) containing film on a dielectric, followed by depositing cobalt on the Mn containing film. The Mn-containing film can be deposited on a silicon-containing dielectric such as silicon dioxide and annealed to form manganese silicate.

Description

Manganese barrier and adhesion layers for cobalt
Technical Field
The present invention relates generally to the field of semiconductor manufacturing, and more particularly to manganese barrier and adhesion layers for cobalt.
Background
Semiconductor device fabrication typically involves the deposition of conductive materials for front-end-of-line (FEOL), middle-of-line (MOL), and back-end-of-line (BEOL) applications, such as source and drain contacts and logic interconnects. For example, tungsten-containing materials may be used for horizontal interconnects between adjacent metal layers, vias, and contacts between a first metal layer on a silicon substrate and a device. Copper is another commonly used conductive material. However, as devices shrink, features become narrower and aspect ratios increase, leading to challenges in using these conductive materials.
For example, copper interconnects are challenging to fabricate technology nodes beyond 7 nm. The deposition of copper interconnects typically involves first depositing a barrier layer. Copper barrier materials that maintain their integrity below 2.5nm in thickness have not been identified. As the line width reaches 10nm (at the 5nm technology node), the barrier layer will consume 5nm line width and over 50% of the line cross section, so that the resistance increases exponentially for each technology node over 10 nm. As a result, alternative materials are sought to fill the features.
An alternative to copper and tungsten is cobalt. However, for applications such as cobalt interconnects, various process integration challenges exist.
Disclosure of Invention
One aspect of the present disclosure relates to a method, comprising: (a) providing a substrate having a feature comprising a feature opening; (b) forming a manganese-containing liner layer in the feature; and (c) after (b), exposing the substrate to a cobalt-containing precursor to at least partially fill the features with cobalt. In some embodiments, (c) comprises completely filling the feature with cobalt.
In some embodiments, the method further comprises heating the substrate to a temperature of at least 400 ℃ to anneal the cobalt. In some such embodiments, the method further comprises reacting at least some of the manganese with cobalt during heating of the substrate.
In some embodiments, (b) includes Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD) of an elemental manganese film in the feature. In some such embodiments, (b) further comprises heating the substrate to at least 350 ℃ to enable the elemental manganese film to react with a silicon-containing underlayer to form a manganese silicate layer. In some such embodiments, the exposed portion of the elemental manganese film is not converted to manganese silicate.
In some embodiments, (b) includes Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD) of a manganese nitride film in the feature. In some such embodiments, the method further comprises heating the substrate to at least 350 ℃ to enable the manganese to react with the silicon-containing underlayer to form a manganese silicate layer and desorb nitrogen from the substrate.
In some embodiments, the method further comprises, after (b) and before (c), exposing the substrate to a nitrogen species to form a differential inhibition curve. In some such embodiments, the method further comprises preferentially depositing cobalt in the one or more features according to the differential suppression curve.
In some embodiments, (c) comprises depositing a cobalt seed layer for a subsequent Co plating process.
Another aspect of the present disclosure relates to a method, comprising: (a) providing a substrate having a feature comprising a feature opening and having sidewalls comprising dielectric silicon; (b) forming an elemental manganese layer in the feature, wherein the elemental manganese layer is conformal to the feature; (c) after (b), converting a portion of the elemental manganese layer to a manganese silicate layer such that the exposed portion of the elemental manganese layer can remain unconverted; (d) filling the features with cobalt; and (e) forming a cobalt-manganese alloy at an interface of the cobalt and the manganese silicate layer.
In particular, some aspects of the invention may be set forth as follows:
1. a method, comprising:
(a) providing a substrate having a feature comprising a feature opening;
(b) forming a manganese-containing liner layer in the feature; and
(c) after (b), exposing the substrate to a cobalt-containing precursor to at least partially fill the features with cobalt.
2. The method of clause 1, wherein (c) comprises completely filling the feature with cobalt.
3. The method of clause 2, further comprising heating the substrate to a temperature of at least 400 ℃ to anneal the cobalt.
4. The method of clause 3, further comprising reacting at least some manganese with cobalt during heating of the substrate.
5. The method of clause 3, further comprising alloying at least some of the manganese with cobalt during heating of the substrate.
6. The method of clause 1, wherein (b) includes Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD) of the elemental manganese film in the feature.
7. The method of clause 6, wherein (b) further comprises heating the substrate to at least 350 ℃ so that the elemental manganese film can react with a silicon-containing underlayer to form a manganese silicate layer.
8. The method of clause 7, wherein the exposed portion of the elemental manganese film is not converted to manganese silicate.
9. The method of clause 1, wherein (b) includes Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD) of the manganese nitride film in the feature.
10. The method of clause 9, further comprising heating the substrate to at least 350 ℃ to enable manganese to react with the silicon-containing underlayer to form a manganese silicate layer and desorb nitrogen from the substrate.
11. The method of clause 1, further comprising, after (b) and before (c), exposing the substrate to a nitrogen species to form a differential suppression curve.
12. The method of clause 11, further comprising preferentially depositing cobalt in the one or more features according to the differential suppression curve.
13. The method of clause 1, wherein (c) comprises depositing a cobalt seed layer for a subsequent Co plating process.
14. A method, comprising:
(a) providing a substrate having a feature comprising a feature opening and having sidewalls comprising dielectric silicon;
(b) forming an elemental manganese layer in the feature, wherein the elemental manganese layer is conformal to the feature;
(c) after (b), converting a portion of the elemental manganese layer to a manganese silicate layer such that the exposed portion of the elemental manganese layer can remain unconverted;
(d) filling the features with cobalt; and
(e) a cobalt-manganese alloy is formed at the interface of the cobalt and the manganese silicate layer.
These and other aspects are further discussed below with reference to the figures.
Drawings
FIG. 1 is a process flow diagram of operations for performing a method in accordance with a disclosed embodiment.
Fig. 2A-2C are schematic cross-sectional views illustrating certain operations in an example of the method described with reference to fig. 1.
FIGS. 3-5 show the formation of SiO2XPS profiling of the Mn/Co metal stack above: FIG. 3 uses annealing, FIG. 4 does not anneal, FIG. 5 does not degas, H2Plasma, norThere is annealing.
Fig. 6 shows an image of Co on a Mn-containing layer prior to Co annealing.
Fig. 7 shows an image of Co on a Mn-containing layer after Co annealing.
FIG. 8A provides a simple block diagram depicting various reactor components arranged to implement certain methods described herein.
Fig. 8B shows a schematic diagram of an apparatus for processing a semiconductor substrate, according to some embodiments.
FIG. 9 illustrates a schematic diagram of an embodiment of a multi-station processing tool that can be used in accordance with certain embodiments.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with the specific embodiments, it will be understood that they are not intended to limit the disclosed embodiments.
In semiconductor fabrication, the features may be filled with a conductive material. For example, tungsten is often filled in features to form contacts (such as in front end of line (FEOL) applications). However, as devices shrink, aspect ratios increase and smaller features are used to form contacts. In many applications, alternative conductive materials (such as cobalt) may be used to form the contacts or fill features.
Cobalt deposition in conventional semiconductor manufacturing includes wet deposition processes such as electroplating and electroless plating. In cobalt electroplating, some thickness of metal is first deposited in the feature, making the metal sufficiently conductive that the current flow allows the metal to grow in the feature in an electroplating or electroless plating process. Such a seed layer may have a certain maximum resistance. Wet-based cobalt feature fill processes, such as electroplating, typically involve feature filling in a different tool than the deposition tool of the seed layer, which increases the complexity of the process and the manufacturing cost.
One aspect of the subject matter described herein relates to methods of forming conductive cobalt (Co) interconnects and other features. The method includes depositing a thin manganese (Mn) -containing film on a dielectric, followed by depositing cobalt on the Mn-containing film. FIG. 1 is a process flow diagram of operations for performing a method in accordance with a disclosed embodiment. Fig. 2A-2C are schematic cross-sectional views illustrating certain operations in an example of the method described with reference to fig. 1. In operation 102, a substrate having features to be filled is provided. The substrate may be a silicon substrate or another suitable semiconductor substrate. The features may be in a semiconductor layer, an insulator layer, or a conductive layer. The substrate may include more than one feature and may include a pattern of features having various sizes of features or features having one size of features. For purposes of this description, FIG. 1 is discussed in the context of filling a single feature, but it should be understood that features of various sizes may be similarly filled.
Fig. 2A is a schematic illustration of an example of such a feature 200 in a substrate 202. The substrate may be a silicon wafer (e.g., a 200-mm wafer, a 300-mm wafer, a 450-mm wafer), comprising a wafer having one or more layers of material (such as a dielectric material, a conductive material, or a semiconductive material) deposited thereon. The features may be characterized by one or more of narrow and/or concave openings, constrictions within the features, and high aspect ratios. In some embodiments, the features 200 may have an aspect ratio of at least about 2: 1, at least about 10: 1, at least about 15: 1, at least about 20: 1 or higher. Feature holes 205 represent open spaces to be filled and may also have dimensions near the opening of less than about 19nm (e.g., opening diameter or line width, or opening width, or critical dimension), otherwise known as feature widths of less than 1 × nm. The features 200 can be referred to as unfilled features or simply features. This and any features are characterized in part by an axis extending through the length of the feature, with vertically oriented features having a vertical axis and horizontally oriented features having a horizontal axis. The feature may be characterized by a bottom and dielectric sidewalls, the bottom being silicon, metal, or other material.
As shown, the substrate 202 includes a feature 200 having a feature opening 210 that is narrower than the width of the bottom of the feature. Thus, the feature 200 in FIG. 2A comprises a concave profile. The concave profile is as follows: narrowing from the bottom, closed end, or interior of the feature to the feature opening. According to various embodiments, the profile may be gradually narrowed and/or include a protrusion at the feature opening. The pattern of recesses shown in fig. 2A can result from asymmetric etching kinetic energy during patterning and/or protrusions due to non-conformal film step coverage in previous film depositions. In various examples, the feature may have a width at the opening at the top of the feature that is less than the width at the bottom of the feature.
Returning to fig. 1, in operation 104, a Mn-containing film is formed in the feature. According to various embodiments, the Mn-containing film may be a thin layer conformal (conform) to the feature. Fig. 2B is a schematic illustration of a Mn-containing layer 204 conformally deposited into the feature 200. The Mn metal-organic precursor can be formed by ALD or CVD processes by reacting the Mn metal-organic precursor with a reducing agent such as H2Or NH3Reaction, Mn deposition. Examples of Mn precursors include bis (N, N ' -di-tert-butylacetamidinate) manganese (II) (mangannese (II) bis (N, N ' -di-tert-butylacetamidate)), bis [1- (tert-butylamide) -2-dimethylaminoethane-N, N ']Manganese (II) and bis (N, N' -diisopropylpentamidine) manganese (II).
In the CVD process, the substrate is exposed to a suitable Mn-containing precursor and a reducing agent to form a Mn layer on the substrate. In an ALD process, the substrate may be cycled through exposure such that the substrate is first exposed to a pulse of a suitable Mn-containing precursor, then purged of the precursor, then exposed to a pulse of a reducing agent, and then purged of the reducing agent, and such cycling may be repeated until a desired Mn thickness is formed on the substrate. ALD methods can be used for high aspect ratio and/or narrow features to promote conformal deposition. In some embodiments, the deposition temperature may be 250 ℃ or below 250 ℃.
In some embodiments, after ALD or CVD deposition of elemental Mn, an annealing process is performed to form a manganese silicate layer, and in some cases, manganese oxide. For example, an annealing treatment of about 350 ℃ to 500 ℃ may be performed. This Mn anneal may be performed after the Mn layer is deposited or during a later Co anneal. In some embodiments, the deposition temperature may be sufficiently high such that manganese silicate is formed during deposition and no additional anneal is performed.
Can be formed with a dielectric (e.g., SiO)2) A Mn-containing film is formed in the sidewall features. In some embodiments, the coating is formed by SiO2Reduction of Mn to SiO2Formation of MnO on top of surfacexAnd/or MnSiyOz(x, y, and z are any integer or non-integer greater than zero that can be formed). In some embodiments, the Mn-containing film can be deposited to a thickness of less than 20 angstroms, less than 10 angstroms. As described below, even a thin Mn layer can provide good adhesion and barrier properties to Co due to its unique properties. The Mn-containing film may include the element Mn and a binary or ternary compound, such as MnOxAnd MnSiyOz。MnOxUsed to denote a mixture of manganese oxides or manganese oxide. Mn (II) forms MnO; mn (III) formation can be expressed as MnO1.5Mn of (2)2O3Mn (IV) forming MnO3And the like. The manganese oxide layer refers to a layer containing manganese oxide or a mixture of a plurality of oxides. MnSiyOzUsed to denote manganese silicate or a mixture of manganese silicates. Mn (II) formation of MnSiO3. The manganese silicate layer refers to a layer including manganese silicate or a mixture of manganese silicates.
In some embodiments, the deposition and/or subsequent annealing is controlled such that small amounts of pure Mn (e.g., 2 to 3 monolayers) remain unconverted in the MnSixOyOf the bottom plate. This unconverted Mn can alloy with Co and act as an adhesion layer.
In operation 105, the Mn-containing film is optionally treated with nitrogen. This operation is discussed further below and may be performed to suppress Co nucleation at the top of the feature. Thus, the process can be preferentially applied to the top of the feature.
In operation 106, the feature is filled with Co by one or more PVD, ALD, CVD, or plating processes. For example, in some embodiments, a thin Co seed layer may be deposited by ALD. The seed layer may then be filled with bulk Co by CVD. Alternatively, Co may be plated on the Co seed layer. Fig. 2C shows an example of a feature comprising a Mn liner layer 204 filled with Co 206.
In a CVD process, the substrate is exposed to a suitable cobalt-containing precursor and a reducing agent to form a cobalt layer on the substrate. In some embodiments, the temperature may be between about 70 ℃ and about 400 ℃, or between about 80 ℃ and about 200 ℃. In some embodiments, the temperature may be between about 70 ℃ and about 200 ℃, or between about 100 ℃ and about 120 ℃. The chamber pressure can be about 0.1 Torr (Torr) to about 10Torr, or between about 1Torr and about 30 Torr. In some embodiments, the chamber pressure can be between about 0.5Torr and about 10Torr, or between about 1Torr and about 3 Torr. In various embodiments, a suitable cobalt-containing precursor and/or reducing agent is introduced into the chamber using a carrier gas, such as argon (Ar), nitrogen (N)2) Or carbon monoxide (CO). In some embodiments, the cobalt-containing precursor is introduced into the chamber using argon as a carrier gas. The flow rate of the carrier gas can be between about 10sccm and about 300sccm, or between about 10sccm and about 50 sccm. In some embodiments, the flow rate of the carrier gas can be between about 10sccm and about 100sccm, or between about 10sccm and about 30 sccm. The reducing agent may be any suitable reactant that reduces the selected cobalt-containing precursor. In various embodiments, the reducing agent is hydrogen (H)2). The reducing agent may be introduced at a flow rate of between about 100sccm and about 5000sccm, or between about 2000sccm and about 5000 sccm. It should be understood that flow rates outside of the ranges provided throughout this disclosure may be used depending on the particular deposition chamber.
In an ALD process, the substrate may be cycled through exposures such that the substrate is first exposed to a pulse of an appropriate cobalt-containing precursor, then the precursor is purged, then the substrate is exposed to a pulse of a reducing agent, and the reducing agent is purged, and such a cycle may be repeated until a desired thickness of cobalt is formed on the substrate. For deposition processes by ALD, the temperature may be between about 70 ℃ and about 400 ℃, or between about 100 ℃ and about 200 ℃. In some embodiments, the temperature may be between about 70 ℃ and about 200 ℃, or between about 100 ℃ and about 120 ℃. The pressure may be between about 1Torr and about 30Torr, or at aboutBetween 8Torr and about 15 Torr. In various embodiments, a cobalt-containing precursor and/or a reducing agent is introduced into a chamber using a carrier gas, such as Ar, N2Or CO. In some embodiments, the cobalt-containing precursor is introduced into the chamber using Ar as a carrier gas. The flow rate of the carrier gas can be between about 10sccm and about 300sccm, or between about 10sccm and about 100 sccm. In some embodiments, the flow rate of the carrier gas can be between about 50sccm and about 100 sccm. The reducing agent may be any suitable reactant for reducing the selected cobalt-containing precursor. In various embodiments, the reducing agent is H2. The reducing agent may be introduced at a flow rate of between about 100sccm and about 5000sccm, or between about 2000sccm and about 5000 sccm. The time at which operation 206 terminates depends on the size of the feature.
Exemplary cobalt-containing precursors include cyclopentadienyl cobalt (I) dicarbonyl, cobalt carbonyl, various cobalt amidinate precursors, diazadiene cobalt complexes, cobalt amidinate/guanidinate precursors, and combinations thereof. Suitable cobalt-containing precursors may comprise a cobalt center having an organic group comprising alkyl groups such as methyl, ethyl, propyl, butyl, pentyl, hexyl, heptyl, and octyl groups, which may be linear or branched hydrocarbon chains, and/or carbonyl groups. In some embodiments, the organometallic compound has a substituted or unsubstituted allyl ligand. In some embodiments, the allyl ligand is unsubstituted.
In some embodiments, organometallic cobalt compounds having the following structure are used:
Figure BDA0001294260690000091
wherein R is1Is C1-C8-alkyl, R2Is C1-C8Alkyl, x is 0, 1 or 2; and y is 0
Or 1.
In some embodiments R1Is C2-C8Alkyl radical, R2Independently is C2-C8An alkyl group.
The term "alkyl" as used herein refers to a saturated hydrocarbon chain of 1to 8 atoms in length, such as methyl, ethyl, propyl, butyl, pentyl, hexyl, heptyl and octyl. The term "alkyl" encompasses both straight and branched hydrocarbon chains. Thus, the term propyl encompasses both n-propyl and isopropyl. The term butyl comprises n-butyl, sec-butyl, isobutyl and tert-butyl.
In some embodiments, x is 0 and y is 1. Examples of the organometallic compounds according to this embodiment are shown below:
Figure BDA0001294260690000092
some of the illustrated compounds can be from SAFC-Hitech, Haverhill, massachusetts, in combination with a corresponding deposition apparatus from Lam Research inc.
In some embodiments, the cobalt-containing precursor comprises a metallorganic precursor having a high vapor pressure at low temperatures (such as temperatures below about 100 ℃). An exemplary vapor pressure may be about 0.5Torr in an environment of about 30 c.
According to various embodiments, the Co deposition process may be performed according to U.S. patent publication No.20160056077, which is incorporated herein by reference. The Co filling can also be done by sputtering from a Co target or by electroplating.
In some embodiments, the substrate may be annealed after the formation of a thin Co seed layer, after the Co fill, or both. Annealing the substrate can reduce the resistivity of Co and help form an alloy (or other compound formation) of Co and Mn at high temperatures. In some embodiments, the annealing may be performed at a temperature between about 250 ℃ and about 500 ℃. To form an alloy of Co and Mn, higher temperatures, such as about 600 ℃, may be used. In some embodiments, a temperature below the alloying temperature may be used to react Mn and Co. The duration of the anneal may depend on the type of heating method used to heat the substrate. Exemplary techniques include radiant heating, laser heating, thermal heating, and electromagnetic radiation heating. In some embodiments, the annealing may be performed such that the annealing time is performed as quickly as possible. In some embodiments, the heating may be performed for a duration of between 1 second and 30 minutes.
In some embodiments, manganese nitride (MnN, which may include any suitable stoichiometric ratio including Mn, may be formed in operation 104 of fig. 13N2). For example, if the subsequent operation involves exposure to air, manganese nitride may be used. Exposure to air can result in rapid oxidation of the as-deposited pure Mn film, thereby preventing the formation of manganese silicate. By forming the MnN layer, oxidation can be prevented. The anneal used to form the manganese silicate will denitrify the surface. MnN may use a Mn-containing precursor and a nitrogen-containing reactant (e.g., ammonia (NH) in an ALD or CVD process)3) Formed as part of operation 104. Alternatively, ALD or CVD deposits elemental Mn followed by annealing to form a manganese silicate layer, which can be performed under vacuum without air exposure. The substrate may then be transferred under vacuum for cobalt filling. In SiO2MnN is deposited on and then a silicate barrier layer is formed by annealing as described in Au, Yeung, Youbo Lin, and Roy G.Gordon.2011.filling narrow trenches by iodine-catalyzed CVD of coater and silane on silane nitride barrier/adhesives layer journal of the Electrochemical Society 158(5) D248-D253, which is incorporated herein by reference.
According to various embodiments, the method may be used for logic interconnects (MOL and BEOL), metal gate applications, and other applications involving Co metallization. The method of incorporating Mn into a Co metallization scheme (e.g., source/drain contact fill or local interconnect) described above with respect to fig. 1 addresses various integration challenges presented by using Co to enhance device performance.
The challenges include the following: 1) co can be easily oxidized due to its unique redox properties; 2) co does not adhere well to dielectric surfaces (e.g., SiO)2And Si3N4) And onto the oxidized metal substrate; 3) co can diffuse into certain dielectrics and cause time-dependent dielectrics on semiconductor devicesBreakdown (TDDB) problems; 4) for resistivity reduction, the Co film may be annealed to about 400 ℃ after deposition. Co undergoes a phase change during annealing, resulting in the formation of a large stress-lag within the film. The latter can lead to film delamination if the adhesion to the substrate is insufficient; and 5) during device fabrication, high temperature cycling similar to that of post-deposition annealing is repeated in subsequent metallization/isolation sequences and may lead to reliability issues for Co films.
The use of a thin Mn layer (less than 20 angstroms, and in some cases less than 10 angstroms) as a barrier layer and adhesion layer overcomes these integration barriers. First, because Co and Mn form different alloys, in some embodiments Co adheres better to Mn than to other possible lining metals. In addition, Mn has a unique self-forming barrier due to its reactivity with different types of silica. Thus, it is SiO2Co on the substrate provides a thin barrier and adhesion layer. Thus, most electron conduction occurs through the lower resistance Co metal.
In some embodiments, the Mn-containing film is treated by exposure to an N species, which may be provided in the form of a plasma. Mn reacts with active N species (N radicals or N ions) to form MnN, which behaves differently from Mn for nucleation and growth of Co. In using direct or remote N2In the case of plasma, for example, the surface of the Mn-containing layer may be treated differently (e.g., the top of the features may be treated preferentially over the bottom of the features) to selectively inhibit Co growth. This may facilitate a bottom-up growth method for void-free filling of high aspect ratio structures typically encountered in advanced logic (e.g., source/drain contacts and metal gates) or memory (3D NAND word line) applications. Reactive N treatment may be with N2The plasma is performed. An alternative to N incorporation into Mn films after Mn film formation is to use NH with or without plasma3
In some embodiments, Mn surfaces at and near the top of the features are treated by exposure to a plasma generated from a nitrogen-containing gas. This treatment may be referred to as "inhibitor control of the stormDew "(ICE) or" plasma-based surface nitridation ". In some embodiments, a remote plasma is used to generate the plasma. In various embodiments, the plasma is a directional plasma such that active species from the plasma directly contact the surface of the feature in a direction perpendicular to the plane of the substrate. In some embodiments, the treated surface may form MnNxWhich triggers a long nucleation delay on the subsequent Co seed layer deposition or Co bulk deposition on the Mn-containing film. Some MnNxAre unstable, thereby enabling the nitrided Mn-containing films to act as temporary inhibitors of Co nucleation.
Since various features may have openings that are narrower than the width of the bottom of the feature, the plasma, in some embodiments, primarily treats the top surface of the feature, from about 10% to about 50% of the top of the feature sidewalls. In some embodiments, the plasma treats the top of the feature sidewalls from about 10% to about 30%. In various embodiments involving small features, the bottom of the sidewall is left untreated by about 50% to 90% due to the narrow opening. In some embodiments, the bottom of the sidewall is about 70% to 90% untreated. In some embodiments, when the active species impact the feature openings, the nitrogen ions collide around the openings, leaving a small gradient of treated Mn surface near the top of the feature. Since the treated surface exhibits a longer nucleation delay, cobalt nucleation is selectively inhibited on the treated surface, resulting in a differential inhibition curve along the characteristic axis formed by the treatment. Selective inhibition, which may also be referred to as selective passivation, differential inhibition, or differential passivation, involves inhibiting subsequent cobalt nucleation on a portion of the feature, while not inhibiting nucleation (or inhibiting nucleation to a lesser degree) on the remainder of the feature. For example, in some embodiments, features at or near the feature opening (e.g., about 10% to about 50% of the top of the feature sidewalls, or about 10% to about 30% and the top surface of the feature) are selectively inhibited, while nucleation in about 70% to 90%, or about 50% to 90% of the bottom of the sidewalls within the feature is not inhibited.
The directional plasma can generate ions, neutral species, and radicals, among other species, that form a differential suppression curve. For directional plasmas, the ions generated may be the dominant species in the suppression process.
In some embodiments, a remote plasma may be used. In addition to neutral species and radicals, among other species, remote plasmas may also generate ions. However, remote plasmas may generate little to no ions compared to directional in situ plasmas, and the dominant species in the suppression process may be radicals rather than ions. In various embodiments, the remote plasma may be gentler such that damage to components of the substrate is reduced (e.g., there is little bombardment of plasma species on the substrate). This may be used in particular when manufacturing logic devices, which may be more susceptible to performance problems when damaged by in-situ or directional plasmas. The damage caused by the plasma may degrade the functionality of the device. For example, plasma damage to components such as transistors in metal gate regions may result in voltage shifts or electrical inefficiencies in order to fabricate the transistors.
In the case of using a remote plasma, the substrate temperature may be set at a temperature between about 30 ℃ and about 450 ℃. In various embodiments, the chamber pressure can be set at a pressure between about 0.001 torr and about 10 torr. The RF power may be between about 50W and 10000W. In various embodiments, a nitrogen-containing gas is flowed to a remote plasma generator to generate a nitrogen-based plasma. The nitrogen-containing gas may be any of those described above. In some embodiments, the nitrogen-containing gas is nitrogen (N)2). The nitrogen flow rate can be between about 5sccm to about 10000 sccm. The substrate may be exposed to a nitrogen-based plasma generated from a remote plasma generator for a duration of between about 1 second and about 200 seconds.
Test of
Depositing about 30 angstroms of MnN to thermal SiO using a CVD process at a temperature greater than 250 deg.C2On a substrate. The silicate is formed by annealing. Degassing was carried out at 300 ℃. Transferring the sample to an external plasma processing chamber, wherein the sample is in airAny MnO formed during exposurexIs remotely located H2And (4) plasma reduction. The sample was then transferred in vacuum to a Co deposition chamber where approximately 90 angstroms of Co was deposited by PVD onto the Mn surface. The final sample was then transferred in vacuo to an annealing chamber where it was placed in H2Annealing at 400 ℃ for 10 minutes in a/He environment. A second sample was prepared without a subsequent Co deposition anneal as a reference. In the absence of degassing, in the absence of H2The third sample was prepared with the plasma reduced and without annealing.
XPS profiling analysis to examine Co/Mn/SiO2The interface of (2).
FIGS. 3-5 show SiO2XPS profile of Mn/Co metal stack above: FIG. 3 with annealing, FIG. 4 without annealing, FIG. 5 without degassing and without H2Plasma, nor annealing. The results show that Mn and SiO2React to form stabilized MnSiyOzAnd (3) a layer. Mn hardly diffuses into the Co layer even after annealing at 400 deg.C, as MnSi in FIG. 3yOzAs evidenced by the overlap of the Si and Mn signals at the top surface of the layer. The curves are also similar to those of the as-deposited samples in fig. 4 and 5, which did not see any annealing. The layer is degassed and H2The plasma is also stable as shown by fig. 3 and a comparison of fig. 4 with fig. 5.
For all samples, Co rarely or never crossed the bottom MnSiyOzPenetration of the barrier layer into SiO2In (1). The results show that Mn is in SiO2Which forms a good barrier to Co diffusion. In addition, Mn does not infiltrate and diffuse into the Co layer, indicating that MnSiyOzThe layer is stable at 400 ℃. This is important because Co annealing allows grain growth, densification of the film and reduction of resistivity. Fig. 6 shows an image of Co on the Mn-containing layer before annealing, and fig. 7 shows an image of Co on the Mn-containing layer after annealing. As can be seen by comparing the images, annealing densifies the film.
Device for measuring the position of a moving object
Any suitable chamber may be used to implement the disclosed embodiments. In some embodiments, no plasma may be used during the deposition of cobalt. Examples of deposition apparatus include any of a variety of systems, such as ALTUS and ALTUS Max available from Lam Research Corporation of fremont, california, or any of a variety of other commercially available processing systems.
The deposition techniques provided herein may also be implemented in a Plasma Enhanced Chemical Vapor Deposition (PECVD) chamber, or a Conformal Film Deposition (CFD) chamber, or in some embodiments, an ALD chamber. Suitable chambers may take many forms and may be part of an apparatus that includes one or more chambers or reactors (sometimes including multiple stations), each of which may house one or more substrates or wafers and may be configured to perform various substrate processing operations. The one or more chambers may maintain the substrate in a defined one or more positions (whether or not there is motion within the position, such as rotation, vibration, or other agitation). In one embodiment, substrates undergoing film deposition may be transported from one station within the chamber to another during processing. In other embodiments, the substrate may be transferred from chamber to chamber within the apparatus to perform different operations, such as etching operations or photolithography operations. For any deposition step, the full film deposition may be performed entirely at a single station or for any portion of the total film thickness. Each substrate may be held in place during processing by a pedestal, substrate chuck, and/or other substrate holding device. For certain operations in which the substrate is to be heated, the apparatus may include a heater (such as a hot plate).
FIG. 8A provides a simple block diagram depicting various reactor components for implementing some of the process arrangements described herein. As shown, the reactor 500 includes a process chamber 524 enclosing the other components of the reactor and used to contain a plasma generated by a capacitive discharge type system including a showerhead 514 operating in conjunction with a grounded heater block 520. A High Frequency (HF) Radio Frequency (RF) generator 504 and a Low Frequency (LF) RF generator 502 may be connected to the matching network 506 and the showerhead 514. The power and frequency supplied by the matching network 506 may be sufficient to generate a plasma from the process gas supplied to the process chamber 524. For example, the matching network 506 may provide 100W to 1000W of power. In some examples, a matching network 506 may be provided. In a typical process, the HFRF assembly may typically be between 1MHz and 100MHz, for example 13.56 MHz. In operation, when there are LF components, the LF components may be less than about 1MHz, such as 100 kHz.
Within the reactor, a pedestal 518 may support a substrate 516. The pedestal 518 may contain chucks, forks, or lift pins (not shown) to hold and transport substrates during and between deposition and/or plasma processing reactions. The chuck may be an electrostatic chuck, a mechanical chuck, or various other types of chucks that may be used in industry and/or research.
Various process gases may be introduced via inlet 512. A plurality of source gas lines 510 are connected to the manifold 508. The gases may be premixed or not. Appropriate valves and mass flow control mechanisms may be employed to ensure that the appropriate process gases are delivered during the deposition and plasma processing stages of the process. Where the chemical precursors are delivered in liquid form, a liquid flow control mechanism may be employed. Such liquid may then evaporate and mix with the process gas during delivery in a manifold that is heated above the vaporization point of the chemical precursors supplied in liquid form before reaching the deposition chamber.
A process gas, such as a Mn-containing precursor, a cobalt-containing precursor, or an N-containing gas, can be output from the chamber 524 via an outlet 522. A vacuum pump (e.g., a primary or secondary mechanical dry pump and/or a turbomolecular pump 540) may be used to draw process gases from the process chamber 524 and maintain a suitably low pressure within the process chamber 524 by using a closed-loop controlled flow restriction device, such as a throttle valve or a pendulum valve.
As noted above, the techniques for deposition described herein may be implemented in a multi-station or single-station tool. Fig. 6 is a schematic diagram of an example of such a tool. In particular embodiments, a 300mm Lam Vector with a 4-station deposition scheme may be usedTMTool, or 200mm sequence with 6 station deposition protocolTMA tool. In some embodiments, a tool for processing 450mm substrates may be used. In various embodiments, if the etching chamber is a vacuum chamber orWhere the stations are also part of the same tool, the substrate may be indexed after each deposition and/or post-deposition plasma treatment, or may be indexed after the etching step, or multiple depositions and treatments may be performed at a single station before the substrate is indexed.
In some implementations, an apparatus may be provided that is configured to perform the techniques described herein. Suitable apparatus may include hardware for performing various processing operations in accordance with the disclosed embodiments, and a system controller 530 having instructions for controlling the processing operations. The system controller 530 will typically comprise one or more memory devices, and one or more processors communicatively coupled to various process control devices (e.g., valves, RF generators, substrate processing systems, etc.), and configured to execute instructions such that the devices will perform techniques in accordance with the disclosed embodiments, e.g., such as those provided in the deposition step of fig. 1. A machine-readable medium containing instructions for controlling processing operations in accordance with the present disclosure may be coupled to system controller 530. The controller 530 may be communicatively coupled to various hardware devices (e.g., mass flow controllers, valves, RF generators, vacuum pumps, etc.) to facilitate control of various process parameters associated with deposition operations as described herein.
In some embodiments, the system controller 530 may control all activities of the reactor 500. The system controller 530 may execute system control software that is stored in a mass storage device, loaded into a memory device, and executed on a processor. The system control software may contain instructions for controlling the timing of gas flows, substrate movement, RF generator activation, etc., as well as instructions for controlling the mixing of gases, chamber and/or station pressures, chamber and/or station temperatures, substrate temperatures, target power levels, RF power levels, substrate pedestal, chuck, and/or pedestal positions, and other parameters of the particular process being performed by the reactor apparatus 500. For example, the software may contain instructions or code for controlling the flow rate of the Mn-containing precursor, the flow rate of the cobalt-containing precursor, the flow rate of the reducing agent, the flow rate of the nitrogen-containing gas, and the number of exposures to each of the flowing chemicals described above. The system control software may be configured in any suitable manner. For example, various process tool component subroutines or control objects may write the operations of the control process tool components needed to perform various process tool processes. The system control software may be encoded in any suitable computer readable programming language.
The system controller 530 may typically include one or more memory devices, and one or more processors configured to execute instructions such that the apparatus will perform techniques in accordance with this disclosure. A machine-readable medium containing instructions for controlling processing operations in accordance with the disclosed embodiments may be coupled to system controller 530.
Fig. 8B shows a schematic diagram of an apparatus 500B for processing a semiconductor substrate, according to some embodiments. The apparatus 500B includes a chamber 518B having a pedestal 520B, a showerhead 514B, and an optional in-situ plasma generator 516B. The device 500B also includes a system controller 522B for receiving inputs and/or providing control signals to the various devices. The apparatus also includes other gases that may be delivered to the chamber 512B through the showerhead 514B.
The nitrogen-containing gas, and in some embodiments, an inert gas such as argon, helium, etc., is provided to the remote plasma generator 506B from a source 502B, which may be a tank. Any suitable remote plasma generator may be used to energize the nitrogen-containing gas prior to introducing the nitrogen-containing gas into chamber 518B. For example, it is possible to use a Remote Plasma Cleaning (RPC) unit, e.g.
Figure BDA0001294260690000171
i Type AX7670、
Figure BDA0001294260690000172
e Type AX7680、
Figure BDA0001294260690000173
ex Type AX7685、
Figure BDA0001294260690000174
hf-s Type AX7645, both available from MKS Instruments of Andorff, Mass. RPC units are commonly usedA separate apparatus is provided for generating a weakly ionized plasma from a nitrogen-containing gas. A high power RF generator embedded in the RPC cell energizes the electrons in the plasma. This energy is then transferred to neutral etchant molecules, resulting in a temperature of about 2000K, causing thermal dissociation of these molecules. RPC cells, due to their high RF energy and special channel geometry, cause these molecules to absorb most of the energy, thereby dissociating more than 60% of the incoming molecules. In various embodiments, the remote plasma generator may generate the plasma using a Radio Frequency (RF) plasma power of between about 50W to about 10000W.
In some embodiments, a nitrogen-based plasma is flowed from the remote plasma generator 506B into the chamber 518B through the connection 508B, where the mixture is dispensed through the showerhead 514B. In other embodiments, the nitrogen-based plasma flows directly into chamber 518B completely bypassing remote plasma generator 506 (e.g., system 500B does not include such a generator). Alternatively, the remote plasma generator 506B may be turned off while flowing the nitrogen-based plasma to the chamber 518B, for example, because the etchant does not need to be activated.
In some embodiments, the showerhead 514B or susceptor 520B may generally have an internal plasma generator 516B coupled thereto. In one example, generator 516B is a High Frequency (HF) generator capable of providing between about 0W and 10,000W at a frequency between about 1MHz and 100 MHz. In a more specific embodiment, the HF generator can be delivered at about 13.56MHz between about 0W to 5,000W. The RF generator 516B may generate an in-situ plasma to enhance the removal of the initial tungsten layer. In some embodiments, the RF generator 516B is not used during the removal operation of the process.
The chamber 518B may include sensors 524B for sensing various process parameters, such as the degree of deposition and etching, concentration, pressure, temperature, etc. The sensor 524B may provide information regarding the chamber conditions to the system controller 522B during processing. Examples of sensors 524B include mass flow controllers, pressure sensors, thermocouples, and the like. The sensor 524B may also include an infrared detector or optical detector to monitor the presence of gases in the chamber and control measures.
The deposition and selective removal operations produce various volatile species that are exhausted from chamber 518B. In addition, processing occurs in chamber 518B at some predetermined pressure level. For example, in some embodiments, the chamber pressure can be set at a pressure between about 0.001 Torr and about 10 Torr. These functions may be accomplished using the vacuum outlet 526B, which may be a vacuum pump 526B.
A Mn-containing precursor or a cobalt-containing precursor and a processing chemistry may be passed from the showerhead 514B into the chamber such that the substrate on the pedestal 520B is exposed to the precursor or processing chemistry in various embodiments.
In certain embodiments, system controller 522B may include any of the features or functions of system controller 530 described above with respect to fig. 8A, or any of the features and functions of control 650 described below with respect to fig. 9.
As described above, one or more processing stations may be included in a multi-station processing tool. Fig. 9 shows a schematic view of an embodiment of a multi-station processing tool 600 having an inbound load lock 602 and an outbound load lock 604, one or both of which may include a remote plasma source. The robot 606 at atmospheric pressure is configured to move substrates from the cassettes loaded through the pod 608 into the inbound load lock 602 via the atmospheric port 610. The substrate is placed on a pedestal 612 in the inbound load lock 602 by the robot 606, the atmospheric port 610 is closed and the load lock is evacuated. When the inbound load lock 602 includes a remote plasma source, the substrate may be exposed to remote plasma processing in the load lock prior to introduction into the process chamber 614. In addition, the substrate may also be heated in the inbound load lock 602, for example, to remove moisture and adsorbed gases. Next, the chamber transfer port 616 to the process chamber 614 is opened and another robot (not shown) places the substrate in the reactor on the base of the first station shown in the reactor for processing. The embodiment depicted in fig. 9 includes a load lock, but it should be understood that in some embodiments, the substrate may be directed into the processing station.
The depicted processing chamber 614 includes 4 processing stations, numbered from 1to 4 in the embodiment shown in FIG. 9. Each station has a heated base (shown as 618 for station 1) and a gas line inlet. Some stations may contain similar components as described with respect to fig. 8A. It should be understood that in some embodiments, each processing station may have a different or multiple purpose. For example, in some embodiments, the processing stations may be switchable between ALD and CVD processing modes. Additionally or alternatively, in some embodiments, the process chamber 614 may contain one or more matched pairs of ALD and CVD processing stations. In some embodiments, the Mn-containing film may be thermally (without plasma) deposited within the feature at one station (such as station 1) using ALD or CVD. The substrate may then be transferred to a second station within the same chamber 614, such as station 2, or a station in a different chamber where the substrate is exposed to a nitrogen-containing gas and plasma, followed by exposure to a cobalt-containing precursor and a reducing agent to deposit a Co seed layer by ALD and to deposit bulk cobalt by CVD. In some embodiments, the plasma exposure is alternated with the reducing agent while flowing the nitrogen-containing gas into the chamber. The nitrogen-containing gas and/or the reducing agent may be introduced only to the station (such as station 2) where the associated substrate is located, or may be introduced throughout chamber 614.
In various embodiments, the substrate is not transferred to the second station. Instead, the substrate remains at the same station (e.g., station 1) as during thermal deposition, but the station is equipped to also introduce a reducing agent, a nitrogen-containing gas, and a plasma to the station after thermal deposition.
In some embodiments, after the substrate has undergone thermal deposition of Mn, the substrate is transferred to a different chamber that may also contain various stations. Although the depicted processing chamber 614 includes 4 stations, it is understood that processing chambers according to the present disclosure may have any suitable number of stations. For example, in some embodiments, the process chamber may have 5 or more stations, while in other embodiments, the process chamber may have 3 or fewer stations.
Fig. 9 depicts an embodiment of a wafer processing system 609 for transporting wafers within a processing chamber 614. In some embodiments, wafer handling system 609 may transport wafers between various processing stations and/or between a processing station and a load lock. It should be understood that any suitable wafer processing system may be employed. Non-limiting examples include wafer turntables, and wafer handling robots. FIG. 9 also depicts an embodiment of a system controller 650 employed to control the process conditions and hardware states of the processing tool 600. The system controller 650 may include one or more memory devices 656, one or more mass storage devices 654, and one or more processors 652. Processor 652 may comprise a CPU or computer, analog and/or digital input/output connections, stepper motor controller board, etc.
In some embodiments, the system controller 650 controls all activities of the processing tool 600. The system controller 650 executes system control software 658 that is stored on the mass storage device 654, loaded into the memory device 656, and executed on the processor 652. Alternatively, the control logic may be hard coded in the controller 650. Application specific integrated circuits, programmable logic devices (e.g., field programmable gate arrays, or FPGAs), etc. may be used for these purposes. Wherever "software" or "code" is used in the following discussion, it may be replaced with functionally equivalent hard-coded logic. The system control software 658 may contain instructions for controlling timing, mixing of gases, amount of sub-saturated gas flow, chamber and/or station pressures, chamber and/or station temperatures, wafer temperatures, target power levels, RF power levels, substrate pedestal, chuck and/or pedestal positions, and other parameters of the particular process being performed by the process tool 600. The system control software 658 may be configured in any suitable manner. For example, various process tool component subroutines or control objects may write the operations of the control process tool components needed to perform various process tool processes. The system control software 658 may be encoded in any suitable computer-readable programming language.
In some embodiments, the system control software 658 may include input/output control (IOC) sequencing instructions for controlling the various parameters described above. Other computer software and/or programs stored on the mass storage device 654 and/or the memory device 656 associated with the controller 650 may be employed in some embodiments. Examples of programs or program segments for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.
The substrate positioning program may contain program code for a processing tool assembly used to load the substrate onto the pedestal 618 and control the spacing between the substrate and the rest of the processing tool 600.
The process gas control program may include code for: the gas components (e.g., cobalt-containing precursor, reducing agent, and nitrogen-containing gas as described herein) and flow rates are controlled and optionally used to flow gases into one or more processing stations prior to deposition to stabilize the pressure at the processing stations. The pressure control program may contain code for: the pressure in the processing station is controlled, for example, by adjusting a throttle valve in the exhaust system of the processing station, the gas flow to the processing station, etc.
In some embodiments, the controller 650 is part of a system, which may be part of the embodiments described above. Such a system may include a semiconductor processing facility that includes one or more process tools, one or more chambers such as chamber 614, one or more platforms for processing, and/or specific processing components (wafer susceptors, gas flow systems, etc.). These systems may be integrated with electronic devices to control the operation of these systems before, during, or after processing of semiconductor wafers or substrates. The electronics may be referred to as a "controller," which may control various components or sub-portions of one or more systems. Depending on the process requirements and/or type of system, the controller 650 can be programmed to control any of the processes disclosed herein, including controlling the delivery of process gases, the setting of temperatures (e.g., heating and/or cooling), the setting of pressures, the setting of vacuums, the setting of powers, the setting of Radio Frequency (RF) generators, the setting of RF matching circuits, the setting of frequencies, the setting of flow rates, the setting of fluid delivery, the setting of locations and operations, the transfer of wafers to and from other delivery tools and/or load locks connected to or interfaced with a particular system.
In a broad sense, the controller 650 may be defined as an electronic device having various integrated circuits, logic, memory, and/or software to receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, and the like. These integrated circuits may include a chip storing program instructions in firmware, a Digital Signal Processor (DSP), a chip defined as an Application Specific Integrated Circuit (ASIC), and/or one or more microprocessors or microcontrollers executing program instructions (e.g., software). The program instructions may be transmitted to the controller 650 or system in the form of various individual settings (or program files) that define the operating parameters for a particular process on or for a semiconductor wafer. In some embodiments, the operating parameters may be part of a recipe defined by a process engineer to complete one or more process steps in the fabrication of one or more layer(s), material, metal, oxide, silicon dioxide, surface, circuit, and/or die of a wafer. For example, the parameters may include a cobalt-containing precursor gas flow, a reductant gas flow, a carrier gas flow, a nitrogen-containing gas flow, a plasma power and frequency, a pedestal temperature, a station or chamber pressure and/or temperature, and other parameters.
In some embodiments, the controller 650 may be part of or coupled to a computer that is integrated with, coupled to, or otherwise connected to the system via a network, or a combination thereof. For example, the controller 650 may be in the "cloud" or be all or part of a factory-fab (fab) host system, which may allow remote access to wafer processing. The computer may enable remote access to the system to monitor a current process of the manufacturing operation, check a history of past manufacturing operations, check trends or performance criteria of a plurality of manufacturing operations to change parameters of the current process, set processing steps to follow the current process or start a new process. In some examples, a remote computer (e.g., a server) may provide the process recipe to the system over a network, which may include a local network or the internet. The remote computer may include a user interface that allows parameters and/or settings to be input or programmed, which are then communicated from the remote computer to the system. In some examples, controller 650 receives instructions in the form of data specifying parameters for each process step to be performed during one or more operations. It should be understood that these parameters may be specific to the type of process to be performed and the type of tool that the controller 650 is configured to interface with or control. Thus, as described above, the controller 650 may be distributed, for example, by including one or more discrete controllers that are networked together and operate toward a common goal (e.g., the processes and controls described herein). An example of a distributed controller 650 for these purposes may be one or more integrated circuits within a chamber that communicate with one or more remote integrated circuits (e.g., at the platform level or as part of a remote computer) that combine to control the in-chamber processes.
Exemplary systems may include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etch chambers or modules, Physical Vapor Deposition (PVD) chambers or modules, Chemical Vapor Deposition (CVD) chambers or modules, Atomic Layer Deposition (ALD) chambers or modules, Atomic Layer Etch (ALE) chambers or modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system that may be associated with or used in the preparation and/or fabrication of semiconductor wafers.
As described above, the controller 650 may communicate with one or more other tool circuits or modules, other tool components, cluster tools such as tool 600, other tool interfaces, adjacent tools, tools located throughout the factory, a mainframe, another controller 650, or tools used in material handling to handle containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing facility, depending on the process step or steps to be performed by the tool.
The heater control program may contain code for: controlling a current to a heating unit used to heat the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas (such as helium) to the substrate.
The plasma control program may include code for: the RF power level applied to the treatment electrodes in one or more treatment stations is set in accordance with embodiments herein.
The pressure control program may contain code for: the pressure in the reaction chamber is maintained according to embodiments herein.
In some embodiments, there may be a user interface associated with the system controller 650. The user interface may include a display screen, a graphical software display of the apparatus and/or process conditions, and a user input device (such as a pointing device, keyboard, touch screen, microphone, etc.).
In some embodiments, the parameters adjusted by the controller 650 may relate to process conditions. Non-limiting examples include process gas composition and flow rate, temperature, pressure, plasma conditions (such as RF bias power level), pressure, temperature, and the like. These parameters may be provided to the user in the form of a recipe, which may be entered using a user interface.
Signals for monitoring the process can be provided from various process tool sensors via analog and/or digital input connections of the controller 650. Signals for controlling the process can be output to analog and digital output connections of the process tool 600. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as pressure gauges), thermocouples, and the like. Suitably programmed feedback and control algorithms can use data from these sensors to maintain process conditions.
The controller 650 may provide program instructions for implementing the deposition process described above. The program instructions may control various process parameters such as dc power level, RF bias power level, pressure, temperature, etc. The instructions may control parameters to operate in-situ deposition of the thin film stack according to various embodiments described herein.
The controller will typically include one or more memory devices and one or more processors configured to execute instructions such that the apparatus will perform the methods in accordance with embodiments of the present invention. The machine-readable medium contains instructions for controlling the operation of the process according to the present invention and may be coupled to a system controller.
The apparatus/processes described above may be used in conjunction with lithographic patterning tools or processes, for example, for the manufacture or production of semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Typically, but not necessarily, such tools/processes will be used or performed together in a common manufacturing facility. Photolithographic patterning of films typically involves some or all of the following operations, each enabling multiple possible tools: (1) applying photoresist to a workpiece (i.e., substrate) using a spin-on or spray-on tool; (2) curing the photoresist using a hot plate or oven or a UV curing tool; (3) exposing the photoresist to visible or UV or X-ray light with a tool such as a wafer stepper; (4) developing the resist to selectively remove the resist, thus patterning it using a tool such as a wet station; (5) transferring the resist pattern to the underlying film or workpiece by using a dry or plasma assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper.
Conclusion
Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatuses of this embodiment. Thus, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims (9)

1. A method of forming a conductive cobalt interconnect, comprising:
(a) providing a substrate having a feature, the feature comprising a feature opening;
(b) forming a manganese nitride liner layer in the feature and heating the substrate to at least 350 ℃ to react manganese with a silicon-containing underlayer to form a manganese silicate layer and desorb nitrogen from the substrate to form MnSiyOzWherein y and z are greater than zero; and
(c) after (b), exposing the substrate to a cobalt-containing precursor to at least partially fill the features with cobalt.
2. The method of forming a conductive cobalt interconnect of claim 1, wherein (c) comprises completely filling said feature with cobalt.
3. The method of forming a conductive cobalt interconnect of claim 2, further comprising heating the substrate to a temperature of at least 400 ℃ to anneal the cobalt.
4. The method of forming a conductive cobalt interconnect of claim 3, further comprising reacting at least some manganese with cobalt during heating of the substrate.
5. The method of forming a conductive cobalt interconnect of claim 3, further comprising alloying at least some of the manganese with cobalt during heating of the substrate.
6. The method of forming a conductive cobalt interconnect of claim 1, wherein forming a manganese nitride liner layer in the feature is performed by atomic layer deposition or chemical vapor deposition.
7. The method of forming a conductive cobalt interconnect of claim 1, further comprising, after (b) and before (c), exposing the substrate to a nitrogen species to form a differential inhibition curve.
8. The method of forming a conductive cobalt interconnect of claim 7, further comprising preferentially depositing cobalt in one or more of said features according to said differential suppression curve.
9. The method of claim 1, wherein (c) comprises depositing a cobalt seed layer for a subsequent cobalt plating process.
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108315717A (en) * 2018-01-24 2018-07-24 复旦大学 A kind of preparation method of manganese nitride film
KR20200124351A (en) * 2019-04-23 2020-11-03 삼성전자주식회사 Cobalt precursor, method for manufacturing cobalt containing layer using the same, and method for manufacturing semiconductor device using the same
US11004736B2 (en) * 2019-07-19 2021-05-11 International Business Machines Corporation Integrated circuit having a single damascene wiring network
CN110804731B (en) * 2019-11-04 2020-11-06 江南大学 Mn grown by atomic layer deposition technologyxN film method
EP4288999A1 (en) 2021-02-08 2023-12-13 MacDermid Enthone Inc. Method and wet chemical compositions for diffusion barrier formation
KR102522160B1 (en) 2021-06-22 2023-04-14 포항공과대학교 산학협력단 Methods and system for analysis of particle by optical detection

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150179579A1 (en) * 2013-12-20 2015-06-25 Christopher J. Jezewski Cobalt based interconnects and methods of fabrication thereof
CN104934409A (en) * 2014-03-21 2015-09-23 台湾积体电路制造股份有限公司 Via pre-fill on back-end-of-the-line interconnect layer
US20150270133A1 (en) * 2014-03-19 2015-09-24 Applied Materials, Inc. Electrochemical plating methods

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6194315B1 (en) * 1999-04-16 2001-02-27 Micron Technology, Inc. Electrochemical cobalt silicide liner for metal contact fills and damascene processes
US9051641B2 (en) 2001-07-25 2015-06-09 Applied Materials, Inc. Cobalt deposition on barrier surfaces
US7879710B2 (en) 2005-05-18 2011-02-01 Intermolecular, Inc. Substrate processing including a masking layer
US8293647B2 (en) 2008-11-24 2012-10-23 Applied Materials, Inc. Bottom up plating by organic surface passivation and differential plating retardation
KR101558428B1 (en) * 2009-03-03 2015-10-20 삼성전자주식회사 Method of forming semiconductor device
US9330939B2 (en) 2012-03-28 2016-05-03 Applied Materials, Inc. Method of enabling seamless cobalt gap-fill
US8610281B1 (en) * 2012-10-02 2013-12-17 Global Foundries Inc. Double-sided semiconductor structure using through-silicon vias
US8907483B2 (en) * 2012-10-10 2014-12-09 Globalfoundries Inc. Semiconductor device having a self-forming barrier layer at via bottom
US9169556B2 (en) 2012-10-11 2015-10-27 Applied Materials, Inc. Tungsten growth modulation by controlling surface composition
US9514983B2 (en) 2012-12-28 2016-12-06 Intel Corporation Cobalt based interconnects and methods of fabrication thereof
US8673779B1 (en) * 2013-02-27 2014-03-18 Lam Research Corporation Interconnect with self-formed barrier
TW201444021A (en) * 2013-05-10 2014-11-16 Univ Nat Cheng Kung Cu/CuMn barrier layer
US9362228B2 (en) * 2013-10-22 2016-06-07 Globalfoundries Inc. Electro-migration enhancing method for self-forming barrier process in copper metalization
US9159610B2 (en) * 2013-10-23 2015-10-13 Globalfoundires, Inc. Hybrid manganese and manganese nitride barriers for back-end-of-line metallization and methods for fabricating the same
US9373542B2 (en) * 2013-11-15 2016-06-21 GlobalFoundries, Inc. Integrated circuits and methods for fabricating integrated circuits with improved contact structures
US20150228585A1 (en) * 2014-02-10 2015-08-13 Globalfoundries Inc. Self-forming barrier integrated with self-aligned cap
KR102398920B1 (en) * 2014-04-07 2022-05-17 엔테그리스, 아이엔씨. Cobalt cvd
US9869024B2 (en) * 2014-07-17 2018-01-16 Applied Materials, Inc. Methods and apparatus for depositing a cobalt layer using a carousel batch deposition reactor
US9748137B2 (en) 2014-08-21 2017-08-29 Lam Research Corporation Method for void-free cobalt gap fill
US9349637B2 (en) 2014-08-21 2016-05-24 Lam Research Corporation Method for void-free cobalt gap fill
US20170040257A1 (en) * 2015-08-04 2017-02-09 International Business Machines Corporation Hybrid subtractive etch/metal fill process for fabricating interconnects
US9589897B1 (en) * 2015-08-18 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Trench liner for removing impurities in a non-copper trench
US9716065B2 (en) * 2015-09-14 2017-07-25 International Business Machines Corporation Via bottom structure and methods of forming
US9613856B1 (en) * 2015-09-18 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming metal interconnection
US9972529B2 (en) * 2015-09-28 2018-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming metal interconnection
US9905460B2 (en) * 2015-11-05 2018-02-27 Globalfoundries Inc. Methods of self-forming barrier formation in metal interconnection applications
US10446496B2 (en) * 2016-02-17 2019-10-15 International Business Machines Corporation Self-forming barrier for cobalt interconnects
US10128151B2 (en) * 2016-12-16 2018-11-13 Globalfoundries Inc. Devices and methods of cobalt fill metallization

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150179579A1 (en) * 2013-12-20 2015-06-25 Christopher J. Jezewski Cobalt based interconnects and methods of fabrication thereof
US20150270133A1 (en) * 2014-03-19 2015-09-24 Applied Materials, Inc. Electrochemical plating methods
CN104934409A (en) * 2014-03-21 2015-09-23 台湾积体电路制造股份有限公司 Via pre-fill on back-end-of-the-line interconnect layer

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