CN107423023A - A kind of 16 × 16 digit redundancy decimal multipliers - Google Patents
A kind of 16 × 16 digit redundancy decimal multipliers Download PDFInfo
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- CN107423023A CN107423023A CN201710680125.7A CN201710680125A CN107423023A CN 107423023 A CN107423023 A CN 107423023A CN 201710680125 A CN201710680125 A CN 201710680125A CN 107423023 A CN107423023 A CN 107423023A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
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Abstract
The invention provides a kind of 16 × 16 digit redundancy decimal multipliers, the Partial product compression module based on ODDS includes the counter square of binary parts product compressed tree square, ODDS × 6, ODDS Partial product compression error correction squares and special decimal number 3:2 compression squares.Binary parts are overstock caused all decimal carries in compression process and carry out the counting operation of 4 bit ODDS × 6 by the counter square of ODDS × 6, and its result is ODDS erroneous character corrections.The present invention carries out the operation of classified counting × 6 using the counter of 4 bit ODDS × 6 to decimal carry, therefore the principle that binary parts are overstock the ODDS numbers of contracting and first compressed using count results caused by elder generation can be merged to be compressed partial product, the delay of decimal multiplier Partial product compression module can be effectively reduced.
Description
Technical field
The invention belongs to digital integrated electronic circuit field, more particularly to a kind of part applied to high-performance decimal multiplier
Product compression module.
Background technology
Decimal arithmetic is the specification that the mankind calculate, and computer reflects and instead of finance and the manual meter in science
Calculate, these calculating are nearly all metric arithmetical operations.Algorism is that decimal arithmetic system was once used in
In earliest computing machine, the electronic computer of many early stages all employ decimal arithmetic, and some even also uses ten and entered
The addressing system of system.After von Neumann architecture is suggested, due to binary arithmetic operation speed is fast and circuit realiration more
The advantages that simple, binary operation method is employed in a computer, the FPU Float Point Unit in microprocessor is general at present
It is all based on binary system rather than decimal system.Although binary arithmetic operation is widely used in microprocessor, number
Word signal processor, but decimal fraction calculate be prevalent among the various computings of computer user, due to binary system with
Error and rounding-off are inevitably present in metric transfer process (for example, the decimal fraction that value is 0.1 is entered using two
The binary number for being converted into Infinite Cyclic is shown in tabulation), business calculating, financial analysis, tax rate calculating, accounting, guarantor can not be met
The required precisions of the field to decimal arithmetic such as danger.
The IEEE754 standard revisions version (IEEE754-2008) of distribution in 2008 has included decimal floating point
The precision of the decimal system 64 (16-digit) and 128 precision (34-digit) lattice of (Decimal Floating Point, DFP) unit
Formula and specification, it indicates the new breakthrough of decimal arithmetic hardware cell research.At present, succeeded in some processors
Integrated special decimal floating point arithmetical operation hardware cell (Decimal Floating Point Unit, DFPU), IBM faces
Microprocessor and Fujitsu's SparcX microprocessors to Power 6, the Z of work station and server series etc. embedded in symbol
Close the decimal floating point arithmetical operation hardware cell of IEEE754-2008 standards.
With the development of each data-intensive industry, the decimal system processing mode of mass data is in bank finance, image pressure
The industry fields such as contracting, biomedical and medical treatment obtain more and more extensive application.The decimal system pinpoint and floating-point operation finance and
Important effect in business causes it progressively to become the focus studied in Computer Architecture.Decimal multiplication computing master
Including the generation of decimal system partial product, decimal system Partial product compression and the decimal system, finally product produces three modules.Decimal multiplication
Important component of the device as decimal floating point MLA operation unit, its performance will directly affect decimal floating point arithmetic element
Overall performance.Therefore the principle and hardware configuration of decimal multiplier are furtherd investigate, designs high performance parallel decimal multiplication
Device has great importance.
Redundancy decimal coded form be used to design high-performance decimal multiplier.Portion based on ODDS PPA partial product arrays
Point product compression module can be accumulated the counter square of compressed tree square, ODDS × 6, ODDS Partial product compression error correction by binary parts
Square and special decimal number 3:2 compression squares are formed.Because decimal numeral carry rules is " meet 10 to enter 1 ", and 4-bit bis-
The carry rules of system number are " to meet 16 to enter 1 ", it is therefore necessary to overstock contracting and ODDS Partial product compressions error correction side to binary parts
All decimal carries are modified caused by block.The method of amendment is：With counter to binary parts accumulate compressed tree and
All decimal carries caused by ODDS Partial product compression error correction squares carry out counting × 6 operations, obtain error correction row.Conventional meter
Number device includes BCD-8421 counters, 4221 counters and ODDS counters, wherein 9:4BCD-8421 counters include 33:2
Compressor reducer delay stages (1 3:2 compressor reducers include the delay of 2 XOR gates)；15-bit ODDS counters include 43:2 compressions
Device delay stages and 3 carry lookahead adder delay stages；The counter of 4-bit ODDS × 6 that the present invention is invented is to 8
When decimal carry count × 6 operation, the counter of including 2 4-bit ODDS × 6, common property is given birth to 2 ODDS erroneous character corrections, closed
Key path includes the delay of 1 XOR gate and 2 alternative data selectors.
The counter of 4-bit ODDS proposed by the invention × 6 accumulates compressed tree square and ODDS partial products to binary parts
All decimal carries caused by error correction square carry out counting × 6 operations, produce ODDS erroneous character corrections, the erroneous character correction composition of all row
Error correction row, merge binary parts and overstock the ODDS numbers of contracting and use the principle that count results caused by elder generation are first compressed to ODDS portions
Product is divided to be compressed error correction.
The content of the invention
Goal of the invention：The present invention for overloading ten's digit collection (overloaded decimal digit set,
ODDS) Partial product compression module, there is provided a kind of Partial product compression module applied to high-performance decimal multiplier, Ke Yiyou
Effect ground reduces the delay of decimal multiplier Partial product compression module.
Technical scheme：
One kind 16 × 16-digit redundancy decimal multipliers, including partial product produces, Partial product compression and final product produce
Raw three modules；The partial product generation module common property gives birth to 17 row ODDS partial products, wherein the 17th behavior amendment row partial product；Institute
Partial product compression module is stated by 17 row ODDS Partial product compressions caused by the partial product generation module to two row BCD-8421 portions
Divide product：A and B；A is added to obtain 32-digit BCD- by the final product generation module with a BCD decade adder with B
8421 final product P；The Partial product compression module includes 17:3 ODDS Partial product compressions modules and special decimal number 3:2 pressures
Contracting square；Described 17:3 ODDS Partial product compressions modules include 17:2 binary parts product compressed tree square, ODDS × 6 count
Device square and 7:3 ODDS Partial product compression error correction squares；The counter square of the ODDS × 6 by binary parts overstock contracting and
Caused all decimal carries carry out the counting operation of 4-bit ODDS × 6, its result in ODDS Partial product compression error correction procedures
For ODDS number erroneous character corrections；
Described 17:2 binary parts product compressed tree square produces 2 row ODDS numbers and 182 decimal carries, 7:3
ODDS Partial product compression error correction square produces 110 decimal carries, and all decimal carries are sent to the counter side of ODDS × 6
Block carries out classified counting, produces erroneous character correction and forms 5 error correction rows by erroneous character correction；Error correction row and 2 row ODDS numbers compression results totally 7
Row ODDS partial products pass through 7:3 ODDS Partial product compression error correction squares are compressed to 3 row ODDS partial products；The special decimal system
Number 3:3 row ODDS partial products are converted to 2 row BCD-8421 partial products by 2 compression squares.
The counter square of the ODDS × 6 uses the principle that carry caused by elder generation first counts, and will be based on binary parts and accumulate
All decimal carries caused by the decimal multiplier Partial product compression module of compressed tree carry out counting × 6 operations, caused
Input of the ODDS error correction row as ODDS Partial product compression error correction squares.
Shown in the 4-bit ODDS × 6 counter formula are specific as follows：
Wherein, Fi[3],Fi[2],Fi[1] and Fi[0] be the counter of 4-bit ODDS × 6 ODDS numbers output, position power
Respectively 8,4,2,10, wherein, the F that position power is 10i[0] it is passed paramount one；Ci[1]-Ci[15] it is highest row 17:2 two enter
15 decimal carries, C caused by Partial product compression tree square processedi[16]-Ci[19] 7 are listed in for highest:3 ODDS overstock part
4 decimal carries caused by contracting error correction square.
The counter structure of 4-bit ODDS × 6 selects a data selector, first to the 3rd including first to fourth 4
With door, the first to the 3rd OR gate, the first nor gate, the first NAND gate, the first XOR gate and the first same OR gate；Described first to
Four or four select a data selector to be formed by three alternative data selectors, wherein, the one or four selects a data selector by
One to the 3rd alternative data selector is formed, and the two or four selects a data selector by the 4th to the 6th alternative data selector
Form, the three or four selects a data selector to be made up of the 7th to the 9th alternative data selector, and the four or four selects a data to select
Device is made up of the tenth to the 12nd alternative data selector；Described first to the 3rd with door, the first to the 3rd OR gate, first or
NOT gate, the first NAND gate, the first XOR gate and first include two inputs with OR gate, for inputting caused by elder generation two ten
System carry；Described first to the 12nd alternative data selector includes two inputs and a selection control signal is defeated
Enter end；Described the first to the second, the selection of the 4th to the five, the 7th to the eight, the tenth to the 11st alternative data selectors
Control signal input is used for decimal carry caused by after inputting；Described three, the six, the 9th and the 12nd alternative number
It is used to input last caused decimal carry according to the selection control signal input of selector；The first alternative data choosing
Two inputs for selecting device are used to input the first output signal with door and the first OR gate；The second alternative data selector
Two inputs be used for input the first OR gate output signal and 1 signal；The 3rd alternative data selector
Two inputs are used for the output signal for inputting the first to the second alternative data selector；The 4th alternative data selection
Two inputs of device are used for the output signal for inputting the second OR gate and the first NAND gate；The 5th alternative data selector
Two inputs be used for input the first NAND gate and first with OR gate output signal；The 6th alternative data selector
Two inputs be used for input the 4th to the 5th alternative data selector output signal；The 7th alternative data choosing
Two inputs for selecting device are used for the output signal for inputting the first XOR gate and the first nor gate；The 8th alternative data choosing
Select device two inputs be used to inputting the first nor gate and second with the output signal of door；The 9th alternative data selection
Two inputs of device are used for the output signal for inputting the 7th to the 8th alternative data selector；The tenth alternative data
Two inputs of selector be used to inputting 0 signal and the 3rd with the output signal of door；The 11st alternative data
Two inputs of selector are used to input the 3rd output signal with door and the 3rd OR gate；The 12nd alternative data choosing
Two inputs for selecting device are used for the output signal for inputting the tenth to the 11st alternative data selector.
Beneficial effect：The present invention is directed to ODDS Partial product compression modules, there is provided one kind multiplies applied to the high-performance decimal system
The counter structure of 4-bit ODDS of musical instruments used in a Buddhist or Taoist mass Partial product compression module × 6.Partial product compression module based on ODDS is entered including two
The counter square of Partial product compression tree square processed, ODDS × 6, ODDS Partial product compression error correction squares and special decimal number 3:2
Compress square.Binary parts are overstock caused all decimal carries in compression process and carry out 4- by the counter square of ODDS × 6
The counting operation of bit ODDS × 6, its result is ODDS erroneous character corrections.The present invention is entered using the counter of 4-bitODDS × 6 to the decimal system
Position carries out classified counting × 6 and operated, therefore can merge binary parts and overstock the ODDS numbers of contracting and counted using first caused
As a result the principle first compressed is compressed to partial product, can be effectively reduced prolonging for decimal multiplier Partial product compression module
When.
Brief description of the drawings
One kind 16 × 16-digit redundancy decimal multiplier the structure charts of accompanying drawing 1；
The one kind 17 of accompanying drawing 2:3 ODDS Partial product compression function structure charts；
The logic chart of the counter of 4-bit ODDS of accompanying drawing 3 × 6；
The counter square of the highest row ODDS of accompanying drawing 4 × 6 and 7:3 ODDS Partial product compression error correction square construction drawings
In accompanying drawing 1：X and Y be respectively 16 × 16-digit decimal multiplication computings multiplier and multiplicand (d is multiplicand
With the digit of multiplier, for 16 × 16-digit decimal multiplication computings, d=16)；{ 5X, 4X, 3X, 2X, 1X } is redundancy excess-three
The multiplicand multiple of (excess-3, XS-3) coding；There is the coding of symbol base -10 to be re-encoded as 16-digit multipliers Y
{Yb1,...,Yb15,Yb16}；PP [0]-PP [d] is 17 row ODDS partial products caused by partial product generation module, wherein the 17th row
To correct row partial product；S1, S2 and S3 are 17:3 row ODDS partial products caused by 3 ODDS Partial product compression modules；A and B serve as reasons
17:Two row BCD-8421 partial products caused by 2 ODDS Partial product compression modules；A is added production with B by BCD decade adders
The final product P of raw decimal multiplier；In accompanying drawing 2：C [1]-C [182] is 17:Caused by 2 binary parts product compressed tree square
All decimal carries, totally 182；C [183]-C [292] is 7:All ten caused by 3 ODDS Partial product compression error correction squares
System carry, totally 110；P1 and P2 is 17:Two row ODDS partial products caused by 2 binary parts product compressed tree square；Accompanying drawing 3
In：Ci[0]-Ci[3] it is 4 decimal carries to be counted；Fi[3],Fi[2],Fi[1] and Fi[0] it is that 4-bit ODDS × 6 are counted
The output of the ODDS numbers of number device, position power are respectively 8,4,2,10, wherein, the F that position power is 10i[0] it is passed paramount one；Fi-1
[0] carry for being low one；MUX-2 represents alternative data selector；In accompanying drawing 4：Ci[1]-Ci[15] it is highest row 17:2 two
15 decimal carries caused by system Partial product compression tree square, Ci[16]-Ci[19] 7 are listed in for highest:3 ODDS partial products
Compress 4 decimal carries caused by error correction square, JCi1-JCi5 be the counter square of ODDS × 6 to highest row Partial product compression
During caused by 19 decimal carries carry out 5 ODDS erroneous character corrections being obtained behind classified counting × 6.
Embodiment
The present invention is further described below in conjunction with the accompanying drawings.
Reference picture 1,16 × 16-digit redundancy decimal multipliers are divided into partial product generation, Partial product compression and final product
Produce three modules.Partial product generation module includes four parts altogether：(1) using has the coding of symbol base -10 to multiplier YiCarry out
Coding；(2) multiplicand is encoded using redundancy XS-3 codings；(3) data selector and XOR gate obtaining portion are selected with five
Point product array (4) accumulates (decimal numeral+3 of all XS-3 of precomputation codings and in error correction by increasing a line error correcting section
This is subtracted in partial product) the XS-3 PPA partial product arrays encoded are converted directly into ODDS forms.Partial product generation module common property
Raw 17 row ODDS partial products PP [0] to PP [16], wherein the 17th behavior amendment row partial product.17:2 ODDS Partial product compression moulds
Block is by 17 row ODDS Partial product compressions caused by the partial product generation module to two row BCD-8421 partial products (A and B)；With one
The BCD-8421 that A is added to obtain 32-digit by individual BCD decade adders with B finally accumulates P.
Reference picture 2,17:3 ODDS Partial product compressions modules include one 17:2 binary parts product compressed tree square, one
The counter square of individual ODDS × 6 and one 7:3 ODDS Partial product compression error correction squares.ODDS × 6 designed by the present invention count
Binary parts are overstock caused all decimal carries in contracting and ODDS Partial product compression error correction procedures and carry out 4- by device square
The counting operation of bit ODDS × 6, its result is ODDS number erroneous character corrections.17:2 binary parts product compressed tree square produces 2 rows
ODDS numbers (compression result) and 182 decimal carries, 7:3 ODDS Partial product compression error correction squares produce 110 decimal systems
Carry, all decimal carries are sent to the counter square of ODDS × 6 and carry out classified counting, produce erroneous character correction and by erroneous character correction group
Into 5 error correction rows.Totally 7 row ODDS partial products pass through 7 for error correction row and 2 row ODDS numbers compression results:3 ODDS Partial product compressions entangle
Wrong square is compressed to 3 row ODDS partial products.
The counter square of the ODDS × 6 is act as：The principle first counted using carry caused by elder generation, it will enter based on two
All decimal carries caused by the decimal multiplier Partial product compression module of Partial product compression tree processed carry out counting × 6 behaviour
Make, input of the caused ODDS error correction row as ODDS Partial product compression error correction squares；The counter of each 4-bit ODDS × 6 is most
4 decimal carries can be counted more, count results are ODDS erroneous character corrections.
If 4 decimal carries to be counted are { Ci[0],Ci[1],Ci[2],Ci[3] }, the 4-bit ODDS × 6 are counted
The input and output truth table of number device is as follows：
Wherein, Fi[3],Fi[2],Fi[1] and Fi[0] it is i-th row (1≤i as caused by the counter of 4-bit ODDS × 6
≤ 32, highest row i=16,17) decimal carry the output of 4 variables.Fi[3],Fi[2],Fi[1] and Fi[0] position power point
Not Wei 8,4,2,10, wherein, Fi[0] position power is 10, is passed to i+1 row decimal digit erroneous character correction.I-th row decimal digit
Erroneous character correction is by Fi[3],Fi[2],Fi[1] and Fi-1[0] form, Fi-1[0] it is to be handed to the i-th row decimal digit error correction by the i-th -1 biographies
Word；Highest is listed in 17:2 ODDS Partial product compression modules common properties give birth to 19 decimal system partial products, need altogether 4 4-bitODDS ×
The counter of 6 counters and 1 3-bit ODDS × 6 carries out the operation of classified counting × 6 to it；Enter to caused by the i-th row all ten
When carry processed count × 6 operation, it is necessary to j ODDS × 6 counters (0≤j≤5)；
Shown in the 4-bit ODDS × 6 counter formula are specific as follows：
The counter structure of 4-bit ODDS × 6 selects a data selector, first to the 3rd including first to fourth 4
With door, the first to the 3rd OR gate, the first nor gate, the first NAND gate, the first XOR gate and the first same OR gate；Described first to
Four or four select a data selector to be formed by three alternative data selectors, wherein, the one or four selects a data selector by
One to the 3rd alternative data selector is formed, and the two or four selects a data selector by the 4th to the 6th alternative data selector
Form, the three or four selects a data selector to be made up of the 7th to the 9th alternative data selector, and the four or four selects a data to select
Device is made up of the tenth to the 12nd alternative data selector；Described first to the 3rd with door, the first to the 3rd OR gate, first or
NOT gate, the first NAND gate, the first XOR gate and first include two inputs with OR gate, for inputting caused by elder generation two ten
System carry；Described first to the 12nd alternative data selector includes two inputs and a selection control signal is defeated
Enter end；Described the first to the second, the selection of the 4th to the five, the 7th to the eight, the tenth to the 11st alternative data selectors
Control signal input is used for decimal carry caused by after inputting；Described three, the six, the 9th and the 12nd alternative number
It is used to input last caused decimal carry according to the selection control signal input of selector；The first alternative data choosing
Two inputs for selecting device are used to input the first output signal with door and the first OR gate；The second alternative data selector
Two inputs be used for input the first OR gate output signal and 1 signal；The 3rd alternative data selector
Two inputs are used for the output signal for inputting the first to the second alternative data selector；The 4th alternative data selection
Two inputs of device are used for the output signal for inputting the second OR gate and the first NAND gate；The 5th alternative data selector
Two inputs be used for input the first NAND gate and first with OR gate output signal；The 6th alternative data selector
Two inputs be used for input the 4th to the 5th alternative data selector output signal；The 7th alternative data choosing
Two inputs for selecting device are used for the output signal for inputting the first XOR gate and the first nor gate；The 8th alternative data choosing
Select device two inputs be used to inputting the first nor gate and second with the output signal of door；The 9th alternative data selection
Two inputs of device are used for the output signal for inputting the 7th to the 8th alternative data selector；The tenth alternative data
Two inputs of selector be used to inputting 0 signal and the 3rd with the output signal of door；The 11st alternative data
Two inputs of selector are used to input the 3rd output signal with door and the 3rd OR gate；The 12nd alternative data choosing
Two inputs for selecting device are used for the output signal for inputting the tenth to the 11st alternative data selector.
The principle that the carry according to caused by elder generation first counts, compressed tree and ODDS Partial product compression error correction are accumulated to binary parts
All decimal carries caused by square carry out the classified counting operation of 4-bit ODDS × 6, produce erroneous character correction.
For 16 × 16-digit decimal multipliers, the 17 of highest row:2 binary parts overstock contracting (17:9,9:6,6:
4 and 4:2) 2 ODDS numbers (compression result) and 15 decimal carries are produced, it is necessary to 3 4-bit ODDS × 6 counters and 1
The counter of individual 3-bit ODDS × 6 counts to 15 decimal carries, is arranged in highest and produces 4 ODDS erroneous character corrections, merges 2
Individual ODDS numbers common property gives birth to 6 ODDS numbers, by this 6 ODDS numbers boil down tos, 2 ODDS number, while produces 4 decimal carries, adopts
1 ODDS erroneous character correction is produced with the counter of 1 4-bit ODDS × 6,3 ODDS numbers are given birth in highest row common property, finally with special
Decimal number 3:2 compressor reducers are by 3 ODDS numbers boil down tos, 2 BCD-8421 decimal numbers；
Described above is only the preferred embodiment of the present invention, it should be pointed out that：For the ordinary skill people of the art
For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should
It is considered as protection scope of the present invention.
Claims (4)
1. one kind 16 × 16-digit redundancy decimal multipliers, including partial product produces, Partial product compression and final product produce
Three modules；The partial product generation module common property gives birth to 17 row ODDS partial products, wherein the 17th behavior amendment row partial product；It is described
Partial product compression module is by 17 row ODDS Partial product compressions caused by the partial product generation module to two row BCD-8421 parts
Product：A and B；A is added to obtain 32-digit BCD- by the final product generation module with a BCD decade adder with B
8421 final product P；It is characterized in that：The Partial product compression module includes 17:3ODDS Partial product compressions module and special ten enter
Number 3 processed:2 compression squares；Described 17:3ODDS Partial product compressions module includes 17:2 binary parts product compressed tree square, ODDS
× 6 counter squares and 7:3ODDS Partial product compression error correction squares；The counter square of the ODDS × 6 accumulates binary parts
Caused all decimal carries carry out the counting operation of 4-bit ODDS × 6 in compression and ODDS Partial product compression error correction procedures,
Its result is ODDS number erroneous character corrections；
Described 17:2 binary parts product compressed tree square produces 2 row ODDS numbers and 182 decimal carries, 7:3ODDS portions
Point overstock contracting error correction square and produce 110 decimal carries, all decimal carries are sent to the counter square progress of ODDS × 6
Classified counting, produce erroneous character correction and 5 error correction rows are formed by erroneous character correction；Error correction row and 2 row ODDS numbers compression results totally 7 row ODDS
Partial product passes through 7:3ODDS Partial product compression error correction squares are compressed to 3 row ODDS partial products；The special decimal number 3:2 pressures
3 row ODDS partial products are converted to 2 row BCD-8421 partial products by contracting square.
2. 16 × 16-digit redundancies decimal multiplier according to claim 1, it is characterised in that：ODDS × 6
Counter square uses the principle that carry caused by elder generation first counts, and the decimal multiplier of compressed tree will be accumulated based on binary parts
All decimal carries caused by Partial product compression module carry out counting × 6 operations, and caused ODDS error correction row is as ODDS portions
Divide the input for overstocking contracting error correction square.
3. 16 × 16-digit redundancies decimal multiplier according to claim 1, it is characterised in that：The 4-bit
Shown in ODDS × 6 counter formula are specific as follows：
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</mtr>
</mtable>
</mfenced>
<mfenced open = "" close = "">
<mtable>
<mtr>
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</mrow>
</mtd>
</mtr>
</mtable>
</mfenced>
Wherein, Fi[3],Fi[2],Fi[1] and Fi[0] be the counter of 4-bit ODDS × 6 ODDS numbers output, position power is respectively
8,4,2,10, wherein, the F that position power is 10i[0] it is passed paramount one；Ci[1]-Ci[15] it is highest row 17:2 binary parts
15 decimal carries caused by product compressed tree square, Ci[16]-Ci[19] 7 are listed in for highest:3ODDS Partial product compression error correction
4 decimal carries caused by square.
4. 16 × 16-digit redundancies decimal multiplier according to claim 1, it is characterised in that：The 4-bit
The counter structure of ODDS × 6 including first to fourth 4 select a data selector, first to the 3rd with door, first to the 3rd or
Door, the first nor gate, the first NAND gate, the first XOR gate and the first same OR gate；Described first to fourth 4 select a data to select
Device is formed by three alternative data selectors, wherein, the one or four selects a data selector by the first to the 3rd alternative number
Formed according to selector, the two or four selects a data selector to be made up of the 4th to the 6th alternative data selector, and the three or four selects one
Data selector is made up of the 7th to the 9th alternative data selector, and the four or four selects a data selector by the tenth to the 12nd
Alternative data selector is formed；Described first to the 3rd with door, the first to the 3rd OR gate, the first nor gate, the first NAND gate,
First XOR gate and first includes two inputs with OR gate, for inputting two decimal carries caused by elder generation；Described
One to the 12nd alternative data selector includes two inputs and a selection control signal input；Described first to
Secondth, the selection control signal input of the 4th to the five, the 7th to the eight, the tenth to the 11st alternative data selectors is used
The caused decimal carry after input；Described three, the six, the 9th and the 12nd alternative data selector selection control
Signal input part processed is used to input last caused decimal carry；Two inputs of the first alternative data selector
For inputting the first output signal with door and the first OR gate；Two inputs of the second alternative data selector are used for
Input the output signal and 1 signal of the first OR gate；Two inputs of the 3rd alternative data selector are used for defeated
Enter the output signal of the first to the second alternative data selector；Two inputs of the 4th alternative data selector are used
In the output signal for inputting the second OR gate and the first NAND gate；Two inputs of the 5th alternative data selector are used for
Input the first NAND gate and first with OR gate output signal；Two inputs of the 6th alternative data selector are used for
Input the output signal of the 4th to the 5th alternative data selector；Two inputs of the 7th alternative data selector
For inputting the output signal of the first XOR gate and the first nor gate；Two inputs of the 8th alternative data selector
For input the first nor gate and second with the output signal of door；Two inputs of the 9th alternative data selector are used
In the output signal for inputting the 7th to the 8th alternative data selector；Two inputs of the tenth alternative data selector
Hold for input 0 signal and the 3rd with the output signal of door；Two inputs of the 11st alternative data selector
Hold for inputting the 3rd output signal with door and the 3rd OR gate；Two inputs of the 12nd alternative data selector
For inputting the output signal of the tenth to the 11st alternative data selector.
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| CN109144473A (en) * | 2018-07-19 | 2019-01-04 | 南京航空航天大学 | A kind of decimal system 3:2 compressor configuration based on redundancy ODDS number |
| CN112506472A (en) * | 2020-11-23 | 2021-03-16 | 南京航空航天大学 | Decimal 4:2 compressor structure based on redundant ODDS number |
| CN112926287A (en) * | 2021-03-10 | 2021-06-08 | 南京航空航天大学 | Decimal to binary number converter based on tree compression |
| CN113014265A (en) * | 2021-02-22 | 2021-06-22 | 南京航空航天大学 | Binary system to decimal number converter based on tree-shaped compression |
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| CN109144473A (en) * | 2018-07-19 | 2019-01-04 | 南京航空航天大学 | A kind of decimal system 3:2 compressor configuration based on redundancy ODDS number |
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| CN112506472B (en) * | 2020-11-23 | 2024-04-02 | 南京航空航天大学 | Decimal 4:2 compressor structure based on redundant ODDS number |
| CN113014265A (en) * | 2021-02-22 | 2021-06-22 | 南京航空航天大学 | Binary system to decimal number converter based on tree-shaped compression |
| CN113014265B (en) * | 2021-02-22 | 2024-01-02 | 南京航空航天大学 | Binary to decimal number converter based on tree compression |
| CN112926287A (en) * | 2021-03-10 | 2021-06-08 | 南京航空航天大学 | Decimal to binary number converter based on tree compression |
| CN112926287B (en) * | 2021-03-10 | 2024-01-30 | 南京航空航天大学 | Decimal-to-binary number converter based on tree compression |
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