CN107403641B - Memory read-write method based on finite-state machine control and memory device - Google Patents
Memory read-write method based on finite-state machine control and memory device Download PDFInfo
- Publication number
- CN107403641B CN107403641B CN201610342963.9A CN201610342963A CN107403641B CN 107403641 B CN107403641 B CN 107403641B CN 201610342963 A CN201610342963 A CN 201610342963A CN 107403641 B CN107403641 B CN 107403641B
- Authority
- CN
- China
- Prior art keywords
- state
- write
- state machine
- finite
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
Landscapes
- Read Only Memory (AREA)
Abstract
The invention provides a memory read-write method based on finite-state machine control and a memory device. The finite state machine comprises a reading state, a loading state, an erasing state, a writing state and a discharging state. The method comprises the following steps: receiving an output enable signal after the finite state machine enters the load state; the output enable signal triggers the finite state machine to enter the read state such that the read state and the load state occur simultaneously. The memory read-write method based on the finite-state machine control effectively reduces the read-write operation time of the memory without an additional external read buffer.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a memory read-write method based on finite-state machine control and a memory device.
Background
Memory devices typically employ a finite state machine to transition their operation from one state to another. A counter is utilized to generate the required delay before each state transitions to the next.
In conventional memory devices, each state typically takes a relatively long time (typically on the order of microseconds to milliseconds). Also, only one state can exist on each specified state, thus making it inevitable to waste time during the waiting period.
Conventionally, in order to save time, careful design on SoC (system on chip) level is required to allow multitasking functions. With chip-level design, data is typically read out first and stored in an external buffer (typically using SRAM). The data stored on the external buffer may be read during other operating states of the memory device. However, the use of external buffers takes up a lot of chip space and ultimately results in a waste of resources in the production of the memory product.
Therefore, it is necessary to provide a memory read/write method and a memory device based on finite-state machine control to solve the existing technical problems.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to overcome the existing problems, one aspect of the present invention provides a memory read-write method based on finite-state machine control, where the finite-state machine includes a read state and a load state, and the method includes:
receiving an output enable signal after the finite state machine enters the load state;
the output enable signal triggers the finite state machine to enter the read state such that the read state and the load state occur simultaneously.
Illustratively, the finite state machine further comprises an erase state, a write state, the output enable signal triggering the finite state machine to enter the read state before entering the erase state or the write state.
Illustratively, the method further comprises receiving a write enable signal, the finite state machine entering the load state when the write enable signal is received.
Illustratively, the finite state machine further comprises a write state, the method further comprising:
loading data to a write buffer while in the load state;
receiving a write start signal that triggers the finite state machine to enter the write state from the load state.
According to another aspect of the present invention there is provided a finite state machine control based memory device, said memory device comprising a memory controller, wherein said finite state machine is implemented on said memory controller and said finite state machine comprises a read state, a load state,
the memory controller comprises an output enable terminal;
wherein, after the finite state machine enters the load state, when an output enable signal is received at the output enable terminal, the output enable signal triggers the finite state machine to enter the read state, such that the read state and the load state occur simultaneously.
Illustratively, the finite state machine further comprises an erase state, a write state, the output enable signal triggering the finite state machine to enter the read state before entering the erase state or the write state.
Illustratively, the memory controller further comprises a write enable terminal;
wherein the write enable signal triggers the finite state machine to enter the load state when a write enable signal is received at the write enable terminal.
Illustratively, the finite state machine further comprises a write state, the memory controller further comprising a write start;
wherein data is loaded to a write buffer while in the load state;
when a write start signal is received at the write start end, the write start signal triggers the state machine to enter the write state from the read state and the load state.
Illustratively, the memory device further comprises a storage array coupled to the memory controller, and the memory device does not have a storage buffer located outside the storage array.
Illustratively, the memory device is an EEPROM.
In summary, the memory read-write method based on finite-state machine control according to the present invention enables the read state and the load state to overlap in time, so that no additional external buffer is needed to store the data to be read, thereby reducing the complexity of SoC design of the memory device. The size of the memory chip can also be reduced by eliminating the need for external buffers. In addition, since the external buffer is no longer required, the external power supply required for the external buffer can be eliminated and thus the effect of saving power can be achieved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent by describing in more detail embodiments of the present invention with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings, like reference numbers generally represent like parts or steps.
In the drawings:
FIG. 1 shows a schematic flow diagram of a finite state machine employed by a memory device according to an embodiment of the present invention;
FIG. 2 shows a schematic flow diagram of a method for reading and writing a memory based on finite state machine control according to an embodiment of the invention;
FIG. 3 illustrates a timing diagram of the read and load states of a memory based on finite state machine control according to an embodiment of the present invention;
FIG. 4 shows a schematic block diagram of a memory device according to an embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
As mentioned above, to save memory operating time, current solutions assume careful design on the SoC level to allow multitasking functions. Usually the data will first be read out and stored in an external buffer. The data stored on the external buffer may be read during other operating states of the memory device. However, using an external buffer would take up a lot of chip space and consume more power.
Therefore, the present invention proposes a memory read/write method and a memory device based on a new finite state machine control, wherein the finite state machine is designed to save the operation time of the memory without additional external buffer.
As is known to those skilled in the art, the operation of a memory device is typically controlled using a finite state machine such that the memory transitions from one operating state to another.
A state machine can be said to be a generalized sequential circuit, and flip-flops, counters, shift registers, etc. can be one of the specific functional types. The number of states in a real sequential circuit is limited and is therefore commonly referred to as a finite state machine. Typically finite state machines are designed in the VHDL language. The state machine is designed with VHDL without knowing its circuit specific implementation details, but rather only needs to be described logically. Thus, when the term state machine is used herein, it is used more generally to describe states and state transitions than to refer to a specific sequential circuit. However, the state machine itself can be realized by a sequential circuit, and specific logic circuits such as a flip-flop, a counter, a shift register, and the like are designed by programming and the like.
The finite state machine needs to go through a series of internal state transitions, the next state being determined by the state decoder based on the current state and the input signal. From the signal output mode of the finite state machine, the finite state machine can be divided into a MOORE type and a MEALY type, the output of the former depends on the state of the former, and the finite state machine has to wait for the arrival of a clock after the input changes, and the clock causes the change of the output when the state changes. The output of the latter is related to the current state and the current input.
As an example, a finite state machine for a memory device of an embodiment of the present invention may include 5 states: read/wait state, load state, erase state, write state, discharge state. These 5 states are triggered by an external signal to make a state transition.
According to the finite state machines currently used for memory devices, if the finite state machine is in a load state, it may then enter a write state or an erase state, then a discharge state, and finally a read state, from which the load state may be entered again. Wherein the loading state takes a relatively long time, typically in the order of milliseconds. Also, the finite state machine is in only one operating state at the same time. Therefore, according to the operation procedure of the conventional finite state machine, it takes a long time for the read and write operations of the memory device.
Therefore, the invention provides a memory read-write method and a memory device based on a new finite-state machine. According to the finite-state machine provided by the embodiment of the invention, the loading state and the reading state of the memory device can be overlapped in time, so that the reading and writing operation time of the memory is effectively reduced. Furthermore, no additional external buffer is needed to store the data that needs to be read, but the reading of the data is done simultaneously during the loading of the memory. The following is a detailed description of embodiments of the invention.
According to an embodiment of the present invention, a memory device includes a memory controller, wherein a finite state machine is implemented on the memory controller, and the finite state machine includes a read/wait state, a load state, an erase state, a write state, a discharge state.
The transition flow of a finite state machine employed by a memory device according to an embodiment of the present invention is described in conjunction with fig. 1.
FIG. 1 shows a schematic flow diagram of a finite state machine employed by a memory device according to an embodiment of the present invention.
As shown in fig. 1, the finite state machine includes 5 states: read/wait state, load state, erase state, write state, discharge state. These 5 states are triggered by an external signal to make a state transition. The read/wait state is a cooperative state, and the finite state machine can be in a read state or a wait state in the cooperative state. When the chip select signal CEN of the memory device is high, the finite state machine is in a wait state in the cooperative state.
When the finite state machine is in a read/wait state, the loading state is entered if a write enable signal (WEN) is received. Otherwise, stay in the read/wait state.
When the finite state machine is in the loading state, if an output enable signal (OEN) is received, the read state is returned. Illustratively, a falling edge of the output enable signal OEN triggers the finite state machine to return from the load state to the read state. The falling edge of the output enable signal OEN indicates when data is read. Even if the two states substantially overlap in time when returning from the loading state to the reading state, the reading operation of the data is caused only when the falling edge of the output enable signal OEN.
In addition, since there is a delay (Address to output delay, tacc) from the read Address preparation to the data output, the finite state machine actually returns from the load state to the read state after tacc time after the falling edge of the output enable signal OEN.
Thus, the output enable signal OEN triggers the finite state machine to return from the load state to the read state, so that the read state and the load state can occur simultaneously.
In addition, when the finite state machine is in the loading state, the writing state or the erasing state is entered if the writing start signal (WS) is received. Typically the finite state machine will enter the erase state first, followed by the write state. However, if the memory is in the full erase mode or in some test modes, the memory may select the pure erase function or the write function, and thus the finite state machine may enter the write state or the erase state upon receiving the write start signal WS.
When the finite state machine is in a write state, a discharge state is entered based on the control of the internal counter.
When the finite state machine is in the erased state, the discharge state is entered based on the control of the internal counter as well.
When the finite state machine is in a discharge state, based on the control of the internal counter, the state is shifted to a write state after the discharge is completed. But if the memory is in the full erase mode or in some test mode, when the discharge is completed, a transition to the read/wait state is determined based on the internal counter and the state opportunity.
The above-described embodiments of the present invention may be implemented, for example, using a MEALY-type finite state machine.
The memory read-write method based on the control of the finite-state machine enables the read state and the load state to be overlapped in time, so that an additional external buffer is not needed for storing data to be read, and the complexity of SoC design of a memory device is reduced. The size of the memory chip can also be reduced by eliminating the need for external buffers. In addition, since the external buffer is no longer required, the external power supply required for the external buffer can be eliminated and thus the effect of saving power can be achieved.
Example one
The embodiment of the invention provides a memory read-write method based on finite-state machine control.
The method for reading and writing the memory based on the finite-state machine control according to the embodiment of the invention is described with reference to fig. 2.
Fig. 2 shows a schematic flow chart of a finite state machine control-based memory read-write method according to an embodiment of the present invention.
The memory read-write method based on the finite-state machine control as shown in FIG. 2 comprises the following steps:
in step S201, a read state or a wait state in which the memory can be in a cooperative state (read/wait state);
if the memory is in a wait state at step S201, the memory controller may trigger a write enable signal WEN at step S202. The step S203 is proceeded after receiving the WEN signal, and the memory enters a loading state;
after the memory enters the loading state, the memory controller may trigger the output enable signal OEN or the write start signal WS at step S204;
if the output enable signal OEN is received at step S204, it returns to step S201 and enters a read state. As described above, the output enable signal OEN at this time triggers the finite state machine to return from the load state to the read state, so that the read state and the load state can occur simultaneously.
If the write start signal WS is received at step S204, proceeding to step S205, the memory enters a write state or an erase state; and, the memory controller enables the output enable signal OEN before the write start signal WS so that the memory enters a read state before entering an erase state or a write state.
In step S205, when the memory is in a write state or an erase state, monitoring whether the counting of the internal counter of the memory control is finished, and if the counting is finished, proceeding to step S206, the memory enters a discharge state;
in step S206, when the memory enters the discharging state, monitoring whether the counting of the internal counter of the memory control is finished, if the counting is finished, returning to step S205, and the memory enters the erasing state; in addition, if the memory is only in the erasing operation, when the counting is finished, the judgment is returned to the step S201 according to the state opportunity, and the memory returns to the read/wait state.
Further, if the memory is in a read state at step S201, the memory controller may trigger the write start WS at step S202. Receiving the write start WS signal proceeds to step S205, and the memory enters a write state or an erase state. At this time, the write state is actually entered from the read state simultaneously with the load state.
The operation method of the above memory according to an embodiment of the present invention may be implemented by a design of a finite state machine. According to the finite-state machine of the embodiment of the invention, the read state and the load state can be overlapped in time, so that an additional external buffer is not needed for storing data to be read, and the complexity of the design of the SoC of the memory device is reduced. The size of the memory chip can also be reduced by eliminating the need for external buffers. In addition, since the external buffer is no longer required, the external power supply required for the external buffer can be eliminated and thus the effect of saving power can be achieved.
The overlap in time of the read state and the load state can be seen more clearly from the timing diagrams of the various signals described above.
FIG. 3 shows a timing diagram of the read and load states of a memory based on finite state machine control according to an embodiment of the invention.
FIG. 3 shows timing diagrams of the output enable signal OEN, the address bus A, the write enable signal WEN, the data bus input DBI, the data bus output DBO, and the write start signal WS, respectively.
As shown in FIG. 3, the falling edge of the write enable signal WEN triggers the memory to enter a load state, and the data bus input DBI shows data input start and data hold; subsequently, a rising edge of the write start signal WS triggers entry into the write state. Therefore, the memory is in the loaded state from the falling edge of the write enable signal WEN to the rising edge of the write start signal WS.
As shown in fig. 3, the falling edge of the output enable signal OEN triggers the entering of the read state, and since it takes a certain time for the address to output delay tacc to elapse, the memory enters the read state at the time tacc elapses after the falling edge of the output enable signal OEN until the rising edge of the OEN triggers the end of the read state.
Thus, as can be seen from FIG. 3, the read state period is actually within a period of the load state period, overlapping the load state during that period.
Example two
Embodiments of the present invention provide a memory device comprising a memory controller, wherein a finite state machine is implemented on the memory controller, and the finite state machine comprises a read state, a load state, an erase state, a write state, a discharge state.
FIG. 4 shows a schematic block diagram of a memory device according to an embodiment of the invention.
As shown in fig. 4, the memory device 300 includes a memory controller 301 and a memory array 302.
The memory controller comprises an output enable terminal OEN, a write enable terminal WEN and a write start terminal WS; the memory array includes a data bus input DBI, an address bus A, and a data bus output.
Wherein, after the finite state machine enters the loading state, when the output enable signal is received at the output enable terminal OEN, the output enable signal triggers the finite state machine to enter the reading state, thereby enabling the reading state and the loading state to occur simultaneously.
And, the output enable signal triggers the finite state machine to enter a read state before entering an erase state or a write state.
When a write enable signal is received at the write enable terminal WS, the write enable signal triggers the finite state machine to enter the loading state.
Loading data to the write buffer while in a load state; when a write start signal is received at the write start WS, the write start signal triggers the state machine to enter the write state from the read state and the load state.
Since the memory controller based on finite state machine control is included for implementing the method of the first embodiment, the memory device also has the advantages described above with respect to the first embodiment.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (8)
1. A memory read-write method based on finite state machine control, the finite state machine comprises a read state and a load state, the method is characterized by comprising:
receiving a write enable signal, the finite state machine entering the loading state when receiving the write enable signal;
receiving an output enable signal after the finite state machine enters the load state;
the output enable signal triggers the finite state machine to enter the read state such that the read state and the load state occur simultaneously.
2. The finite state machine controlled memory read-write method of claim 1, wherein the finite state machine further comprises an erase state, a write state, the output enable signal triggering the finite state machine to enter the read state before entering the erase state or the write state.
3. The finite state machine controlled memory read-write method of claim 1, wherein the finite state machine further comprises a write state, the method further comprising:
loading data to a write buffer while in the load state;
receiving a write start signal that triggers the finite state machine to enter the write state from the load state.
4. A finite state machine control based memory device, the memory device comprising a memory controller, wherein the finite state machine is implemented on the memory controller and the finite state machine comprises a read state, a load state,
the memory controller comprises an output enable terminal and a write enable terminal;
wherein the write enable signal triggers the finite state machine to enter the load state when a write enable signal is received at the write enable terminal;
after the finite state machine enters the load state, when an output enable signal is received at the output enable terminal, the output enable signal triggers the finite state machine to enter the read state, such that the read state and the load state occur simultaneously.
5. The finite state machine control-based memory device of claim 4, wherein the finite state machine further comprises an erase state, a write state, the output enable signal triggering the finite state machine to enter the read state before entering the erase state or the write state.
6. The finite state machine control-based memory device of claim 4, wherein the finite state machine further comprises a write state,
the memory controller further comprises a write start terminal;
wherein data is loaded to a write buffer while in the load state;
when a write start signal is received at the write start end, the write start signal triggers the state machine to enter the write state from the read state and the load state.
7. The finite state machine control-based memory device according to claim 4, wherein the memory device further comprises a storage array connected with the memory controller, and the memory device does not have a storage buffer located outside the storage array.
8. The finite state machine control-based memory device in accordance with claim 4, wherein the memory device is an EEPROM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610342963.9A CN107403641B (en) | 2016-05-20 | 2016-05-20 | Memory read-write method based on finite-state machine control and memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610342963.9A CN107403641B (en) | 2016-05-20 | 2016-05-20 | Memory read-write method based on finite-state machine control and memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107403641A CN107403641A (en) | 2017-11-28 |
| CN107403641B true CN107403641B (en) | 2020-12-18 |
Family
ID=60389174
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610342963.9A Active CN107403641B (en) | 2016-05-20 | 2016-05-20 | Memory read-write method based on finite-state machine control and memory device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107403641B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101083490A (en) * | 2006-06-02 | 2007-12-05 | 飞力凯网路股份有限公司 | Data communication system, information processing terminal, ic card, reader/writer and program |
| CN101303884A (en) * | 2008-06-13 | 2008-11-12 | 炬力集成电路设计有限公司 | Nand type flash memory controller and read-write control system and method |
| CN101599294A (en) * | 2009-05-11 | 2009-12-09 | 曙光信息产业(北京)有限公司 | A kind of method of the multiple virtual queues data storage based on FPGA |
| CN102483948A (en) * | 2009-08-10 | 2012-05-30 | 桑迪士克3D公司 | Semiconductor memory with improved memory block switching |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100498473B1 (en) * | 2003-01-06 | 2005-07-01 | 삼성전자주식회사 | Control signal generation circuit and data transmission circuit having the same |
| JP4996277B2 (en) * | 2007-02-09 | 2012-08-08 | 株式会社東芝 | Semiconductor memory system |
-
2016
- 2016-05-20 CN CN201610342963.9A patent/CN107403641B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101083490A (en) * | 2006-06-02 | 2007-12-05 | 飞力凯网路股份有限公司 | Data communication system, information processing terminal, ic card, reader/writer and program |
| CN101303884A (en) * | 2008-06-13 | 2008-11-12 | 炬力集成电路设计有限公司 | Nand type flash memory controller and read-write control system and method |
| CN101599294A (en) * | 2009-05-11 | 2009-12-09 | 曙光信息产业(北京)有限公司 | A kind of method of the multiple virtual queues data storage based on FPGA |
| CN102483948A (en) * | 2009-08-10 | 2012-05-30 | 桑迪士克3D公司 | Semiconductor memory with improved memory block switching |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107403641A (en) | 2017-11-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7506126B2 (en) | Detection circuit for mixed asynchronous and synchronous memory operation | |
| US6567338B1 (en) | Fully synchronous pipelined RAM | |
| EP0355560B1 (en) | Conditional write ram | |
| CN111613259B (en) | Pseudo static random access memory and operation method thereof | |
| US20060146612A1 (en) | Flash memory devices configured to output data without waiting for bitline and wordline recovery and methods of operating same | |
| CN102326205A (en) | Dynamic random access memory (DRAM) refresh | |
| US20170165730A9 (en) | Memory interface configurable for asynchronous and synchronous operation and for accessing storage from any clock | |
| US20060020764A1 (en) | Information processing apparatus including non-volatile memory device, non-volatile memory device and methods thereof | |
| JP2012155843A (en) | Synchronous burst memory | |
| KR100564598B1 (en) | Synchronous flash memory device and method of operating the same | |
| CN106158012A (en) | Sequential processing method, on-chip SRAM and the FPGA of FPGA on-chip SRAM | |
| US8996738B2 (en) | Data transfer operation completion detection circuit and semiconductor memory device provided therewith | |
| US20130073790A1 (en) | Magnetic random access memory with burst access | |
| US20150092475A1 (en) | Pseudo retention till access mode enabled memory | |
| CN107403641B (en) | Memory read-write method based on finite-state machine control and memory device | |
| US6798712B2 (en) | Wordline latching in semiconductor memories | |
| US6349059B1 (en) | Method for reading data from a non-volatile memory device with autodetect burst mode reading and corresponding reading circuit | |
| US20090282303A1 (en) | Built in test controller with a downloadable testing program | |
| CN102568574B (en) | Nonvolatile semiconductor memory member | |
| US20050223157A1 (en) | Fast non-volatile random access memory in electronic devices | |
| US6374313B1 (en) | FIFO and method of operating same which inhibits output transitions when the last cell is read or when the FIFO is erased | |
| US8547758B2 (en) | Semiconductor memory device and method of operating the same | |
| US20100287337A1 (en) | Nonvolatile memory device and method of operating the same | |
| US7752410B1 (en) | System and method for accessing data in a multicycle operations cache | |
| US7516290B2 (en) | Memory controller |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |