CN107403641A - W method of memory and storage arrangement based on finite states machine control - Google Patents
W method of memory and storage arrangement based on finite states machine control Download PDFInfo
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- CN107403641A CN107403641A CN201610342963.9A CN201610342963A CN107403641A CN 107403641 A CN107403641 A CN 107403641A CN 201610342963 A CN201610342963 A CN 201610342963A CN 107403641 A CN107403641 A CN 107403641A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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Abstract
The present invention provides a kind of W method of memory and storage arrangement based on finite states machine control.The finite state machine includes read states, stress state, erase status, write state, discharge condition.Methods described includes：After the finite state machine enters the stress state, Rreceive output enable signal；The output enable signal triggers the finite state machine and enters the read states, so that the read states and the stress state occur simultaneously.W method of memory based on finite states machine control effectively reduces the read-write operation time of memory without extra outside read buffer.
Description
Technical field
The present invention relates to memory technology field, and finite state machine is based in particular to one kind
The W method of memory and storage arrangement of control.
Background technology
Storage arrangement generally use finite state machine makes its operating process turn from state
Fade to another state.Counter next life is utilized before each state is converted to next state
Into required delay.
In the storage arrangement of routine, it is (general that each state typically takes up longer time
In the magnitude of several microseconds to millisecond).Also, there can only be a state on each designated state
In the presence of hence in so that inevitably causing the time to waste during latent period.
Conventionally, in order to save the time, it is necessary to carried out in SoC (on-chip system) level it is careful
Design to allow multitask function.By piece, higher level is designed, and data would generally be first read out simultaneously
It is stored on the buffer of outside (ordinary circumstance uses SRAM).Deposited on external buffer
The data of storage can be read out during other modes of operation of storage arrangement.However, make
Substantial amounts of chip space will be taken with external buffer, and ultimately results in memory product and is producing
On a kind of wasting of resources.
Therefore, it is necessary to propose a kind of W method of memory based on finite states machine control and
Storage arrangement, to solve existing technical problem.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will be specific real
Apply and be further described in mode part.The Summary of the present invention is not meant to
Attempt to limit the key feature and essential features of technical scheme claimed, less
Mean to attempt the protection domain for determining technical scheme claimed.
In order to overcome the problem of presently, there are, one aspect of the present invention provides one kind and is based on finite state
The W method of memory of machine control, the finite state machine include read states, stress state,
Methods described includes：
After the finite state machine enters the stress state, Rreceive output enable signal；
The output enable signal triggers the finite state machine and enters the read states, so that
Obtain the read states and the stress state occurs simultaneously.
Exemplarily, the finite state machine also includes erase status, write state, the output
Enable signal trigger the finite state machine enter the erase status or the write state it
Advance into the read states.
Exemplarily, methods described further comprises, write enable signal is received, when receiving
State finite state machine during write enable signal and enter the stress state.
Exemplarily, the finite state machine also includes write state, and methods described further comprises：
Write buffer is loaded data into the stress state；
Commencing signal is write in reception, and the commencing signal triggering finite state machine of writing adds from described
Load state enters the write state.
A kind of memory based on finite states machine control is provided according to another aspect of the present invention
Device, the storage arrangement includes Memory Controller, wherein the finite state machine is in institute
State and realized on Memory Controller, and the finite state machine includes read states, stress state,
Characterized in that,
The Memory Controller includes output Enable Pin；
Wherein, after the finite state machine enters the stress state, when in the output
When Enable Pin receives output enable signal, the output enable signal triggers the finite state
Machine enters the read states, so that the read states and the stress state occur simultaneously.
Exemplarily, the finite state machine also includes erase status, write state, the output
Enable signal trigger the finite state machine enter the erase status or the write state it
Advance into the read states.
Exemplarily, the Memory Controller further comprises writing Enable Pin；
Wherein, when it is described write Enable Pin and receive write enable signal when, the write enable signal
Trigger the finite state machine and enter the stress state.
Exemplarily, the finite state machine also includes write state, and the Memory Controller enters
One step includes writing starting end；
Wherein, write buffer is loaded data into the stress state；
When it is described write starting end receive write commencing signal when, it is described write commencing signal triggering institute
State state machine and enter the write state from the read states and the stress state.
Exemplarily, the storage arrangement further comprises being connected with the Memory Controller
Storage array, and the storage arrangement do not have be located at the storage array outside depositing
Store up buffer.
Exemplarily, the memory device is set to EEPROM.
In summary, the W method of memory of the invention based on finite states machine control causes
Read states and stress state can be overlapping in time, come without extra external buffer
The data that will be read are stored, therefore reduce the complexity of storage arrangement SoC design.
By cancelling the needs of external buffer can also be reduced with the size of memory chip.In addition,
Due to no longer needing external buffer, it can consequently also cancel the external power source needed for external buffer
And therefore reach the effect of energy-conservation.
Brief description of the drawings
The embodiment of the present invention is described in more detail in conjunction with the accompanying drawings, of the invention is above-mentioned
And other purposes, feature and advantage will be apparent.Accompanying drawing is used for providing to the present invention
Embodiment is further understood, and a part for constitution instruction, with the embodiment of the present invention one
Rise and be used to explain the present invention, be not construed as limiting the invention.In the accompanying drawings, identical is joined
Examine label and typically represent same parts or step.
In accompanying drawing：
Fig. 1 shows finite state used by storage arrangement according to embodiments of the present invention
The indicative flowchart of machine；
Fig. 2 shows the memory according to embodiments of the present invention based on finite states machine control
The indicative flowchart of reading/writing method；
Fig. 3 shows the memory according to embodiments of the present invention based on finite states machine control
Read states and stress state timing diagram；
Fig. 4 shows the schematic block diagram of storage arrangement according to an embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is it is, however, obvious to a person skilled in the art that of the invention
It can be carried out without one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, be not described for some technical characteristics well known in the art.
It should be appreciated that the present invention can be implemented in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, providing these embodiments disclosure will be made thoroughly and complete
Entirely, those skilled in the art be will fully convey the scope of the invention to and.In the accompanying drawings,
For clarity, the size and relative size in Ceng He areas may be exaggerated.It is identical attached from beginning to end
Icon note represents identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to "
Or when " being coupled to " other elements or layer, its can directly on other elements or layer, with
It is adjacent, be connected or coupled to other elements or layer, or there may be element or layer between two parties.
On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.Should
Understand, although can be used term first, second, third, etc. describe various elements, part,
Area, floor and/or part, these elements, part, area, floor and/or part should not be by these
Term limits.These terms be used merely to distinguish an element, part, area, floor or part with
Another element, part, area, floor or part.Therefore, do not depart from present invention teach that under,
First element discussed below, part, area, floor or part be represented by the second element, part,
Area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... it
Under ", " ... on ", " above " etc., herein can for convenience description and by use from
And an element shown in figure or feature and other elements or the relation of feature are described.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of and operation
In device different orientation.For example, if the device upset in accompanying drawing, then, is described as
" below other elements " or " under it " or " under it " element or feature will be orientated
For other elements or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this hair
Bright limitation.Herein in use, " one " of singulative, "one" and " described/should "
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " composition " and/or " comprising ", when in this specification in use, determine the feature,
Integer, step, operation, the presence of element and/or part, but be not excluded for it is one or more its
Its feature, integer, step, operation, the presence or addition of element, part and/or group.
Herein in use, term "and/or" includes any and all combination of related Listed Items.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description
Suddenly, to explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is described in detail
It is as follows, but in addition to these detailed descriptions, the present invention can also have other embodiment.
As described above, in order to save the operating time of memory, current solution is taken
Carefully design is carried out in SoC levels to allow multitask function.Usual data can be first read out simultaneously
It is stored on the buffer of outside.The data stored on external buffer are in storage arrangement
It can be read out during other modes of operation.However, it will be taken using external buffer a large amount of
Chip space and consume more electric energy.
Therefore, the present invention proposes a kind of memory read/write based on new finite states machine control
Method and storage arrangement, wherein finite state machine are designed to save the operation of memory
Time is without extra external buffer.
As it is known by the man skilled in the art, the operation generally use finite state machine of storage arrangement
To be controlled so that memory is changed to another mode of operation from a mode of operation.
State machine can be described as a broad sense sequence circuit, trigger, counter, shift LD
Device etc. can be one kind of its specific function type.Status number in actual sequence circuit is
Limited, it is thus generically referred to as finite state machine.Usual finite state machine uses VHDL languages
Speech is designed.Its circuit specific implementation details is needed not know about with VHDL design point machines,
And only need logically to be described.Therefore, when proposing one word of state machine, it is more
Refer to and the totality of state and state transfer is described, without referring to a specific sequence circuit.So
And state machine in itself can be by sequence circuit, trigger, counter, shift register etc.
Specific logic circuit is realized by designs such as programmings.
Finite state machine needs to undergo a series of internal state conversion, and next state is by state
Decoder determines according to current state and input signal.From the mode signal output of finite state machine
On, finite state machine can be divided into MOORE types and MEALY types at present, the former output
Its status is only dependent upon, this kind of finite state machine must also wait after input changes
The arrival of clock, clock make state just cause the change exported when changing.And the latter's is defeated
Go out, it is relevant with being presently in state and current input.
As an example, the finite state machine for storage arrangement of embodiments of the invention can be with
Including 5 kinds of states：Reading/wait state, stress state, erase status, write state, electric discharge
State.This 5 kinds of states trigger carry out state transfer by external signal.
According to the finite state machine currently used for storage arrangement, add if finite state machine is in
Load state, then possibly into write state or erase status, followed by discharge condition, most Zhongdao
Read states, stress state can be again introduced into from read states.Wherein, stress state needs to compare
Long time, the generally magnitude in millisecond.Also, the finite state machine within the identical time
In a mode of operation.Therefore, according to the operating process of existing finite state machine, storage
The read-write operation of device device needs to spend longer time.
Therefore, the present invention provide a kind of W method of memory based on new finite state machine and
Storage arrangement.Finite state machine according to embodiments of the present invention, the loading shape of storage arrangement
State and read states can be overlapping in time, during so as to effectively reduce the read-write operation of memory
Between.Also, it is not necessary to extra external buffer needs the data that read to store, but
The reading of data is carried out during the loading of memory simultaneously.Enter with reference to embodiments of the invention
Row specifically describes.
According to an embodiment of the invention, storage arrangement includes Memory Controller, wherein limited
State machine realizes on Memory Controller, and finite state machine include reading/wait state,
Stress state, erase status, write state, discharge condition.
Illustrate with reference to Fig. 1 limited used by storage arrangement according to an embodiment of the invention
The flow path switch of state machine.
Fig. 1 shows finite state used by storage arrangement according to embodiments of the present invention
The indicative flowchart of machine.
As shown in figure 1, finite state machine includes 5 kinds of states：Reading/wait state, loading shape
State, erase status, write state, discharge condition.This 5 kinds of states are triggered by external signal and carried out
State shifts.Wherein, reading/wait state is a collaboration state, and finite state machine is cooperateing with
Read states or wait state are may be under state.As the chip selection signal CEN of storage arrangement
For high level when, wait state that finite state machine is under collaboration state.
When finite state machine is in reading/wait state, if receiving write enable signal (WEN)
Then enter stress state.Otherwise, reading/wait state is rested on.
When finite state machine is in stress state, if receiving output enable signal (OEN),
Then return to read states.Exemplarily, the trailing edge triggering for exporting enable signal OEN is limited
State machine returns to read states from stress state.Export enable signal OEN trailing edge instruction
Data are at what time read.Even if substantial two when returning to read states from stress state
State is overlapping in time, but only just causes when exporting enable signal OEN trailing edge
The read operation of data.
Further, since prepare there is one section of delay (to prolong to output address to data output from address is read
Slow Address to output delay, tacc), therefore finite state machine is actually enabled in output
After the tacc times after signal OEN trailing edges read states are returned to from stress state.
Therefore, enable signal OEN triggering finite state machines are exported and return to reading from stress state
State, so that read states and stress state can occur simultaneously.
In addition, when finite state machine is in stress state, commencing signal (WS) is write if receiving
Then enter write state or into erase status.Usual finite state chance is introduced into erasing shape
State, subsequently enter write state.However, if memory is under full sheet erasing mode or at some
Under test pattern, memory can select simple erasing function or write function, therefore finite state
Machine can enter write state or into erase status when receiving and writing commencing signal WS.
When finite state machine is in write state, the control based on internal counter enters electric discharge shape
State.
When finite state machine is in erase status, the control equally based on internal counter enters
Discharge condition.
When finite state machine is in discharge condition, the control based on internal counter, work as electric discharge
After the completion of be transferred to write state.But if memory is under full sheet erasing mode or in some tests
Under pattern, after the completion of electric discharge, it can judge to be transferred to reading based on internal counter and state machine
/ wait state.
Exemplarily, it can realize that the present invention's is upper using the finite state machine of MEALY types
State embodiment.
The present invention the W method of memory based on finite states machine control cause read states and
Stress state can be overlapping in time, will to store without extra external buffer
The data of reading, therefore reduce the complexity of storage arrangement SoC design.Pass through cancellation
The size of memory chip can also be reduced to the needs of external buffer.Further, since no longer
External buffer is needed, can consequently also cancel the external power source needed for external buffer and therefore arrive
Up to the effect of energy-conservation.
Embodiment one
A kind of memory based on finite states machine control is provided according to an embodiment of the invention to read
Write method.
Illustrate with reference to Fig. 2 according to embodiments of the present invention based on finite states machine control
W method of memory.
Fig. 2 shows the memory according to embodiments of the present invention based on finite states machine control
The indicative flowchart of reading/writing method.
The W method of memory based on finite states machine control includes following step as described in Figure 2
Suddenly：
In step S201, in the collaboration state (reading/wait state) that memory may be at
Read states or wait state；
If be waited in step S201 memories, in step S202 memory controls
Device processed can trigger write enable signal WEN.Write enable signal WEN is received then to advance to
Step S203, memory enter stress state；
After memory enters stress state, it can be touched in step S204 Memory Controllers
Hair output enable signal OEN writes commencing signal WS；
If receive output enable signal OEN, return to step S201 in step S204
And enter read states.As described above, now export enable signal OEN triggering finite state machines
Read states are returned to from stress state, so that read states and stress state can be sent out simultaneously
It is raw.
If being received in step S204 and writing commencing signal WS, proceed to step S205,
Memory enters write state or erase status；Also, Memory Controller is writing commencing signal
Enabled output enable signal OEN before WS so that memory is entering erase status or writing shape
State advances into read states.
In step S205, when memory is in write state or erase status, monitoring reservoir control
Whether the counting of internal counter terminates, and proceeds to step S206 if counting and terminating, deposits
Reservoir enters discharge condition；
In step S206, when memory enters discharge condition, monitoring reservoir control is internal to be counted
Whether the counting of number device terminates, and returns to step S205 if counting and terminating, memory enters
Enter erase status；In addition, if when memory is only erasing operation, when counting terminates, root
It can judge to return to step S201 according to state machine, memory returns to reading/wait state.
If in addition, being in read states in step S201 memories, stored in step S202
Device controller, which can trigger to write, starts WS.Receive write start ws signal then advance to step
S205, memory enter write state or erase status.Now, actually from stress state
The read states carried out simultaneously enter write state.
The operating method of above-mentioned memory according to an embodiment of the invention can pass through limited shape
The design of state machine is realized.Finite state machine according to embodiments of the present invention so that read states and
Stress state can be overlapping in time, will to store without extra external buffer
The data of reading, therefore reduce the complexity of storage arrangement SoC design.Pass through cancellation
The size of memory chip can also be reduced to the needs of external buffer.Further, since no longer
External buffer is needed, can consequently also cancel the external power source needed for external buffer and therefore arrive
Up to the effect of energy-conservation.
It can find out read states and stress state with clearer from the timing diagram of above-mentioned each signal
In time overlapping.
Fig. 3 shows the memory according to embodiments of the present invention based on finite states machine control
Read states and stress state timing diagram.
Fig. 3 respectively illustrates output enable signal OEN, address bus A, write enable signal
WEN, data/address bus input DBI, data/address bus export DBO and write commencing signal WS
Timing diagram.
As shown in figure 3, write enable signal WEN trailing edge triggering memory enters loading shape
State, data/address bus input DBI show that data input starts to keep with data；Then, write
Commencing signal WS rising edge triggering enters write state.Therefore, from write enable signal WEN
Trailing edge to the rising edge for writing commencing signal WS during, memory is all in stress state.
Again as shown in figure 3, output enable signal OEN trailing edge triggering enters read states,
It is therefore, enabled in output due to needing to undergo the address of a period of time to the delay tacc of output
The time by tacc after signal OEN trailing edges, memory enters read states, until OEN
Rising edge triggering read states terminate.
Therefore, from figure 3, it can be seen that the read states cycle is physically located the stress state cycle
In a period of time, with stress state within the period it is overlapping.
Embodiment two
Embodiments of the invention provide a kind of storage arrangement, and the storage arrangement includes storage
Device controller, wherein finite state machine are realized on Memory Controller, and finite state machine
Including read states, stress state, erase status, write state, discharge condition.
Fig. 4 shows the schematic block diagram of storage arrangement according to an embodiment of the invention.
As shown in figure 4, storage arrangement 300 includes Memory Controller 301 and storage array
302。
Memory Controller includes output Enable Pin OEN, writes Enable Pin WEN and writes starting end
WS；Storage array includes data/address bus input DBI, address bus A, data/address bus output.
Wherein, after finite state machine enters stress state, when in output Enable Pin OEN
When place receives output enable signal, output enable signal triggering finite state machine enters to study in shape
State, so that read states and stress state occur simultaneously.
Also, export enable signal triggering finite state machine enter erase status or write state it
Advance into read states.
When write receive write enable signal at Enable Pin WS when, write enable signal triggering it is limited
State machine enters stress state.
Write buffer is loaded data into stress state；When writing at starting end WS receive
When writing commencing signal, write commencing signal triggering state machine and write shape from read states and stress state entrance
State.
Due to including the Memory Controller based on finite states machine control be used for implement it is above-mentioned
The method of embodiment one, the storage arrangement equally have for above-mentioned excellent described in embodiment one
Point.
The present invention is illustrated by above-described embodiment, but it is to be understood that, it is above-mentioned
The purpose that embodiment is only intended to illustrate and illustrated, and be not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that not office of the invention
It is limited to above-described embodiment, more kinds of modifications can also be made according to the teachings of the present invention and repaiied
Change, these variants and modifications are all fallen within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and its equivalent scope.
Claims (10)
1. a kind of W method of memory based on finite states machine control, the finite state
Machine includes read states, stress state, it is characterised in that methods described includes：
After the finite state machine enters the stress state, Rreceive output enable signal；
The output enable signal triggers the finite state machine and enters the read states, so that
Obtain the read states and the stress state occurs simultaneously.
2. the W method of memory based on finite states machine control as claimed in claim 1,
Characterized in that, the finite state machine also includes erase status, write state, the output makes
Energy signal triggers the finite state machine before the erase status or the write state is entered
Into the read states.
3. the W method of memory based on finite states machine control as claimed in claim 1,
Characterized in that, methods described further comprises, write enable signal is received, it is described when receiving
The finite state machine enters the stress state during write enable signal.
4. the W method of memory based on finite states machine control as claimed in claim 1,
Characterized in that, the finite state machine also includes write state, methods described further comprises：
Write buffer is loaded data into the stress state；
Commencing signal is write in reception, and the commencing signal triggering finite state machine of writing adds from described
Load state enters the write state.
5. a kind of storage arrangement based on finite states machine control, the storage arrangement bag
Memory Controller is included, wherein the finite state machine is realized on the Memory Controller,
And the finite state machine includes read states, stress state, it is characterised in that
The Memory Controller includes output Enable Pin；
Wherein, after the finite state machine enters the stress state, when in the output
When Enable Pin receives output enable signal, the output enable signal triggers the finite state
Machine enters the read states, so that the read states and the stress state occur simultaneously.
6. the storage arrangement based on finite states machine control as claimed in claim 5, its
It is characterised by, the finite state machine also includes erase status, write state, and the output is enabled
Signal triggers the finite state machine and is entering the advance of the erase status or the write state
Enter the read states.
7. the storage arrangement based on finite states machine control as claimed in claim 5, its
It is characterised by,
The Memory Controller further comprises writing Enable Pin；
Wherein, when it is described write Enable Pin and receive write enable signal when, the write enable signal
Trigger the finite state machine and enter the stress state.
8. the storage arrangement based on finite states machine control as claimed in claim 5, its
It is characterised by, the finite state machine also includes write state,
The Memory Controller further comprises writing starting end；
Wherein, write buffer is loaded data into the stress state；
When it is described write starting end receive write commencing signal when, it is described write commencing signal triggering institute
State state machine and enter the write state from the read states and the stress state.
9. the storage arrangement based on finite states machine control as claimed in claim 5, its
It is characterised by, the storage arrangement further comprises depositing with what the Memory Controller was connected
Array is stored up, and the storage arrangement does not have the storage being located at outside the storage array and delayed
Rush device.
10. the storage arrangement based on finite states machine control as claimed in claim 5, its
It is characterised by, the memory device is set to EEPROM.
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| Publication number | Publication date |
|---|---|
| CN107403641B (en) | 2020-12-18 |
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