CN107403610A - One kind scanning GOA circuits - Google Patents
One kind scanning GOA circuits Download PDFInfo
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- CN107403610A CN107403610A CN201710860740.6A CN201710860740A CN107403610A CN 107403610 A CN107403610 A CN 107403610A CN 201710860740 A CN201710860740 A CN 201710860740A CN 107403610 A CN107403610 A CN 107403610A
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- film transistor
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
- Shift Register Type Memory (AREA)
Abstract
The present invention provides a kind of scanning GOA circuits, and it includes：First film transistor, the second thin film transistor (TFT), the 3rd thin film transistor (TFT), the 4th thin film transistor (TFT), the first electric capacity；The first end access inverting clock signal of first film transistor, the second end is connected with the first end of the second thin film transistor (TFT), as output end；The grid access scan start signal of 3rd thin film transistor (TFT), and the first end of the 3rd thin film transistor (TFT) is connected with the grid of the second thin film transistor (TFT), the second end of the 3rd thin film transistor (TFT) is connected with the second end of the second thin film transistor (TFT) and accesses high level signal；The grid of 4th thin film transistor (TFT) is connected with source electrode and accesses scan start signal, and drain electrode is connected with the grid of first film transistor；First electric capacity is connected in parallel on the second end with the grid of first film transistor and first film transistor, and first end is source electrode, and the second end is drain electrode, or first end is drain electrode, and the second end is source electrode.The present invention can ensure output end normal output signal.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of scanning GOA circuits.
Background technology
It is aobvious that GOA (Gate Driver on Array, the driving of array base palte row) technology can allow gate driving circuit to be integrated in
Show on panel, can so save the IC (integrated circuit, integrated circuit) that grid potential signal is provided.For soft
Property OLED display, due to needing the threshold voltage and mobility of compensation film transistor, thus need more signals,
So, providing signal from exterior I C becomes extremely difficult.GOA stability is also very for display panel simultaneously
It is important.In order to improve display image quality, each company puts forward a variety of GOA circuits, and Fig. 1 is a kind of GOA circuits announced, and Fig. 2 is
CK (clock signal), XCK (inverting clock signal), STV (scan start signal) oscillogram, the operation of the GOA circuits
It is as follows：
Stage 1：CK (clock signal) is L (low level), and XCK (inverting clock signal) is H (high level), and STV (open by scanning
Dynamic signal) it is L (low level), M3, M4, M5, M10, M11, M12 are opened, and thin film transistor (TFT) M1 grid voltage is L+Vth, Vth
For M2 threshold voltage, thin film transistor (TFT) M3 grid voltage is L, therefore M1, M3 are opened, and M2 grid voltage is H, therefore M2
Close.Output end OUT outputs are XCK, are high level.
Stage 2：CK is H, XCK L, STV H, and thin film transistor (TFT) M10, M11, M12, M6, M7 are opened, M3, M4, M5, M8
Close.Because electric capacity C1, C2 effect, M1 and M2 grid voltage keep voltage status on last stage.C1 one end and M1's
Grid is connected, and when the other end is connected with VGH, at stage 2, output end OUT should export XCK signals, but due to M1 grid electricity
Press as L+Vth, therefore M1 has and opens incomplete risk, easily causes output end OUT output voltages and is more than L, so that can not be complete
The whole normal XCK signals of output.And during GOA levels biography, the output end OUT of one-level GOA circuits exports abnormal ripple
Shape signal, can cause follow-up GOA circuits can not output waveform, so as to cause follow-up GOA circuit outputs to break down.Together
When, the signal of output end OUT outputs is changed into L from H, because of M2 parasitic capacitance effect M2 grid voltage can be caused to be pulled low,
So that M2 and M9 is opened by mistake, M2, which is opened, causes M2 output end to export high level signal VGH, so as to cause output end OUT defeated
Make mistake；M9 is opened, and causes the current potential in Fig. 1 at PD to be driven high, and so as to which M1 be closed, causes output end OUT output to be sent out
Raw failure.
Stage 3：CK is L, and XCK H, STV H, M7, M8, M9, M12 are opened so that M2 grid voltage is L+Vth, M1
Grid voltage be H, then M2 open, M1 close, OUT terminal output VGH, be high level.
By above-mentioned GOA circuit connected in series in use, the STV signals of the 1st grade of GOA circuits access are as shown in Fig. 2 next stage
The grid of M4 in GOA circuits is connected with the output end OUT of upper level GOA circuits.It can be seen that the 1st grade of GOA from Fig. 3 a, 3b
Circuit can not export correct SCAN (scanning signal) waveform, because in the stage 2, the voltage of PD points can not be drawn lower, make CK
Or XCK signal waveforms can not be exported completely., can be because parasitic capacitance effect causes PU simultaneously when M2 parasitic capacitance is larger
Point is pulled low at stage 2, and M9 is opened so that PD point voltages are driven high, and M1 grid voltages are too high, cause not exporting normally
SCAN waveforms.
The content of the invention
In order to solve the above technical problems, the present invention provides a kind of scanning GOA circuits, it can ensure that its output end normally exports
Signal, do not break down.
A kind of scanning GOA circuits provided by the invention, including：It is first film transistor, the second thin film transistor (TFT), the 3rd thin
Film transistor, the 4th thin film transistor (TFT), the first electric capacity；
The first end access inverting clock signal of the first film transistor, the second end of the first film transistor
It is connected with the first end of second thin film transistor (TFT), and is used as output end；
3rd thin film transistor (TFT) grid access scan start signal, the first end of the 3rd thin film transistor (TFT) with
The grid connection of second thin film transistor (TFT), the second end and second thin film transistor (TFT) of the 3rd thin film transistor (TFT)
Second end connects and access high level signal；
The grid of 4th thin film transistor (TFT) connects with source electrode and accesses scan start signal, drains and described first is thin
The grid connection of film transistor；
The both ends of first electric capacity grid with the first film transistor and the first film crystal respectively
The second end connection of pipe；
Wherein, first end is source electrode, and the second end is drain electrode, or first end is drain electrode, and the second end is source electrode.
Preferably, in addition to：5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th thin film transistor (TFT), the 8th film are brilliant
Body pipe；
The grid of 6th thin film transistor (TFT) is connected with source electrode and accesses inverting clock signal, and the 6th film is brilliant
The grid with the 7th thin film transistor (TFT), the first end of the 5th thin film transistor (TFT) are connected respectively for the drain electrode of body pipe；
The grid of 8th thin film transistor (TFT) is connected with the first end of the 7th thin film transistor (TFT) and incoming clock is believed
Number, the first end of the 8th thin film transistor (TFT) is connected with the second end of the 7th thin film transistor (TFT), and the 8th film is brilliant
Second end of body pipe is connected with the first end of the 3rd thin film transistor (TFT)；
The grid of 5th thin film transistor (TFT) is connected with the grid of the 3rd thin film transistor (TFT) and accesses sweep start
Signal, the second end of the 5th thin film transistor (TFT) are connected with the second end of second thin film transistor (TFT).
Preferably, in addition to：It is 9th thin film transistor (TFT), the tenth thin film transistor (TFT), the 11st thin film transistor (TFT), the 12nd thin
Film transistor, the second electric capacity, the 3rd electric capacity；
The drain electrode of 4th thin film transistor (TFT) passes through the tenth thin film transistor (TFT) and the first film transistor
Grid, and the first end connection of the 12nd thin film transistor (TFT)；
Tenth thin film transistor (TFT) grid access scan start signal, the first end of the tenth thin film transistor (TFT) with
The drain electrode connection of 4th thin film transistor (TFT), the second end and the first film transistor of the tenth thin film transistor (TFT)
Grid, and the first end connection of the 12nd thin film transistor (TFT)；
The grid access low level signal of 12nd thin film transistor (TFT), and the source electrode of the 12nd thin film transistor (TFT)
It is connected with the other end of drain electrode with the first end of the 9th thin film transistor (TFT), the second end of the 9th thin film transistor (TFT) and institute
State the second end connection of the second thin film transistor (TFT), the grid of the 9th thin film transistor (TFT) and the grid of second thin film transistor (TFT)
Pole connects；
The grid access low level signal of 11st thin film transistor (TFT), the first end of the 11st thin film transistor (TFT)
Scan start signal is accessed, the second end of the 11st thin film transistor (TFT) is connected with the grid of the 3rd thin film transistor (TFT)；
The both ends of second electric capacity grid with the 9th thin film transistor (TFT), and the 9th film crystal respectively
The second end connection of pipe；
The both ends of 3rd electric capacity connect with the source electrode of the 9th thin film transistor (TFT) and drain electrode respectively.
Preferably, in addition to the 4th electric capacity；
The both ends of 4th electric capacity connect with the source electrode of the 5th thin film transistor (TFT) and drain electrode respectively.
Preferably, in addition to the 13rd thin film transistor (TFT)；
Grid of the grid of 13rd thin film transistor (TFT) respectively with the first film transistor is connected, and the described tenth
The first end access high level signal of three thin film transistor (TFT)s, the second end and second film of the 13rd thin film transistor (TFT)
The grid connection of transistor.
Preferably, the first film transistor, the second thin film transistor (TFT), the 3rd thin film transistor (TFT), the 4th film crystal
Pipe, the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th thin film transistor (TFT), the 8th thin film transistor (TFT), the 9th film crystal
Pipe, the tenth thin film transistor (TFT), the 11st thin film transistor (TFT), the 12nd thin film transistor (TFT), the 13rd thin film transistor (TFT) are p-type
Metal-oxide-semiconductor.
Preferably, high level signal and low level signal are direct current signal.
Preferably, scan start signal on startup between be low level, clock signal is low level in first half period,
And the startup time and first half period are corresponding.
Implement the present invention, have the advantages that：The both ends of the first electric capacity grid with first film transistor respectively
And the second end connection of first film transistor.Because the first electric capacity be directly parallel in first film transistor grid and
On second end of first film transistor, at stage 2 shown in Fig. 2, the first electric capacity can maintain on last stage i.e. stage 1
Voltage status, it is low level L, along with the parasitic capacitance of first film transistor, the grid voltage of first film transistor is small
In 2L so that first film transistor is opened completely, low level signal corresponding to output end output inverting clock signal.Meanwhile
First electric capacity is directly parallel on the grid of first film transistor and the second end of first film transistor, output end by
When high level H is changed into low level L, prevent because the grid voltage that drags down of parasitic capacitance, open and draw high current potential at PD, close
First film transistor.Therefore, the output end of GOA circuits can be with normal output signal.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is the GOA circuit diagrams in background technology provided by the invention.
Fig. 2 is clock signal provided by the invention, inverting clock signal, the oscillogram of scan start signal.
Fig. 3 a be it is provided by the invention selection 20 background technologies in GOA circuits be connected in series after, obtain 1~
The simulation result figure of 4 grades of GOA circuit outputs.
Fig. 3 b be it is provided by the invention selection 20 background technologies in GOA circuits be connected in series after, obtain 16
The simulation result figure of~20 grades of GOA circuit outputs.
Fig. 4 is scanning GOA circuit diagrams provided by the invention.
Fig. 5 a be it is provided by the invention choose after 20 scanning GOA circuits are connected in series, obtained 1~4 grade of GOA electricity
The simulation result figure of road output.
Fig. 5 b be it is provided by the invention choose after 20 scanning GOA circuits are connected in series, obtained 16~20 grades of GOA
The simulation result figure of circuit output.
Embodiment
The present invention provides a kind of scanning GOA circuits, as shown in figure 4, scanning GOA circuits include：First film transistor
M1, the second thin film transistor (TFT) M2, the 3rd thin film transistor (TFT) M3, the 4th thin film transistor (TFT) M4, the first electric capacity C1.
First film transistor M1 first end access inverting clock signal XCK, first film transistor M1 the second end
It is connected with the second thin film transistor (TFT) M2 first end, and is used as output end.
3rd thin film transistor (TFT) M3 grid access scan start signal STV, the 3rd thin film transistor (TFT) M3 first end with
Second thin film transistor (TFT) M2 grid connection, the 3rd thin film transistor (TFT) M3 the second end and the second thin film transistor (TFT) M2 the second end
Connection and access high level signal VGH.
4th thin film transistor (TFT) M4 grid connects with source electrode and accesses scan start signal STV, drain electrode and the first film
Transistor M1 grid connection.
First electric capacity C1 both ends respectively with first film transistor M1 grid and first film transistor M1
Two ends connect.
Wherein, first end is the source electrode of thin film transistor (TFT), and the second end is the drain electrode of thin film transistor (TFT), or first end is thin
The drain electrode of film transistor, the second end are the source electrode of thin film transistor (TFT).
Because the first electric capacity C1 is directly parallel in first film transistor M1 grid and first film transistor M1
On second end, at stage 2 shown in Fig. 2, the first electric capacity C1 can maintain on last stage the voltage status in i.e. stage 1, be low
Level L, along with first film transistor M1 parasitic capacitance, first film transistor M1 grid voltage is less than 2L so that
First film transistor M1 is opened completely, low level signal corresponding to output end OUT output inverting clock signals XCK.Meanwhile the
One electric capacity C1 is directly parallel on first film transistor M1 grid and first film transistor M1 the second end, is being exported
When end OUT is changed into low level L from high level H, prevent from, because M2 parasitic capacitance drags down M2 grid voltage, opening M9 and drawing high
Current potential at PD, close M1.Therefore, the output end OUT of GOA circuits can be with normal output signal.
Further, scanning GOA circuits also include：It is 5th thin film transistor (TFT) M5, the 6th thin film transistor (TFT) M6, the 7th thin
Film transistor M7, the 8th thin film transistor (TFT) M8.
6th thin film transistor (TFT) M6 grid is connected with source electrode and accesses inverting clock signal XCK, the 6th film crystal
The grid with the 7th thin film transistor (TFT) M7, the 5th thin film transistor (TFT) M5 first end are connected respectively for pipe M6 drain electrode.
8th thin film transistor (TFT) M8 grid is connected with the 7th thin film transistor (TFT) M7 first end and incoming clock signal CK,
8th thin film transistor (TFT) M8 first end is connected with the 7th thin film transistor (TFT) M7 the second end, and the second of the 8th thin film transistor (TFT) M8
End is connected with the 3rd thin film transistor (TFT) M3 first end.
5th thin film transistor (TFT) M5 grid is connected with the 3rd thin film transistor (TFT) M3 grid and accesses scan start signal
STV, the 5th thin film transistor (TFT) M5 the second end are connected with the second thin film transistor (TFT) M2 the second end.
Further, scanning GOA circuits also include：9th thin film transistor (TFT) M9, the tenth thin film transistor (TFT) M10, the tenth
One thin film transistor (TFT) M11, the 12nd thin film transistor (TFT) M2, the second electric capacity C2, the 3rd electric capacity C3.
4th thin film transistor (TFT) M4 drain electrode passes through the tenth thin film transistor (TFT) M10 and first film transistor M1 grid,
And the 12nd thin film transistor (TFT) M12 first end connection.
Tenth thin film transistor (TFT) M10 grid access scan start signal STV, the tenth thin film transistor (TFT) M10 first end
Drain electrode with the 4th thin film transistor (TFT) M4 is connected, the tenth thin film transistor (TFT) M10 the second end and first film transistor M1 grid
Pole, and the 12nd thin film transistor (TFT) M12 first end connection.
12nd thin film transistor (TFT) M12 grid access low level signal VGL, and the 12nd thin film transistor (TFT) M12 source
The other end of pole and drain electrode is connected with the 9th thin film transistor (TFT) M9 first end, the 9th thin film transistor (TFT) M9 the second end and second
Thin film transistor (TFT) M2 the second end connection, the 9th thin film transistor (TFT) M9 grid are connected with the second thin film transistor (TFT) M2 grid.
11st thin film transistor (TFT) M11 grid access low level signal VGL, the first of the 11st thin film transistor (TFT) M11
Terminate and connect into scan start signal STV, the 11st thin film transistor (TFT) M11 the second end with the 3rd thin film transistor (TFT) M3 grid
Connect.
The second electric capacity C2 both ends grid with the 9th thin film transistor (TFT) M9, and the of the 9th thin film transistor (TFT) M9 respectively
Two ends connect.Second electric capacity C2 can be avoided in the stage 2, because the parasitic capacitance inside the second thin film transistor (TFT) M2, cause
Two thin film transistor (TFT) M2 and the 9th thin film transistor (TFT) M9 grid voltage is pulled low, so as to cause the second thin film transistor (TFT) M2 and
Nine thin film transistor (TFT) M9 are opened by mistake, when the 9th thin film transistor (TFT) M9 is opened, the voltage at PD can be caused to be driven high, so as to
First film transistor M1 is closed, triggers output failure.Therefore, the second electric capacity C2 can maintain the second thin film transistor (TFT) M2 and
Nine thin film transistor (TFT) M9 grid voltage is stable, and then avoids first film transistor M1 from being closed by mistake, maintains output end OUT
Normal output.
3rd electric capacity C3 both ends connect with the 9th thin film transistor (TFT) M9 source electrode and drain electrode respectively.3rd electric capacity C3 can be with
The electric charge of the 9th thin film transistor (TFT) M9 leakage current release is stored, maintains the 9th thin film transistor (TFT) M9 and the 12nd thin film transistor (TFT)
The current potential of tie point is stable between M12.
Further, scanning GOA circuits also include the 4th electric capacity C4.4th electric capacity C4 both ends respectively with the 5th film
Transistor M5 source electrode and drain electrode connect.
Further, scanning GOA circuits also include the 13rd thin film transistor (TFT) M13.4th electric capacity C4 purpose is dimension
It is stable to hold the 7th thin film transistor (TFT) M7 grid voltage, avoids inverting clock signal XCK during (being changed into L from H) is changed,
Because the 6th thin film transistor (TFT) M6 parasitic capacitance, cause the 7th thin film transistor (TFT) M7 grid voltage to reduce, and then beaten by mistake
Open, cause the output failure of GOA circuits.
Grid of the 13rd thin film transistor (TFT) M13 grid respectively with first film transistor M1 is connected, the 13rd film
Transistor M13 first end access high level signal VGH, the 13rd thin film transistor (TFT) M13 the second end and the second film crystal
Pipe M2 grid connection.13rd thin film transistor (TFT) M13 in order to ensure at PD when being in low potential, prevent that the second film is brilliant
Body pipe M2 is opened by mistake, so as to ensure that the output of GOA circuits is stable.
Further, first film transistor M1, the second thin film transistor (TFT) M2, the 3rd thin film transistor (TFT) M3, the 4th film
Transistor M4, the 5th thin film transistor (TFT) M5, the 6th thin film transistor (TFT) M6, the 7th thin film transistor (TFT) M7, the 8th thin film transistor (TFT) M8,
9th thin film transistor (TFT) M9, the tenth thin film transistor (TFT) M10, the 11st thin film transistor (TFT) M11, the 12nd thin film transistor (TFT) M12,
13 thin film transistor (TFT) M13 are p-type metal-oxide-semiconductor.
Further, high level signal VGH and low level signal VGL is direct current signal.
Further, scan start signal STV on startup between be low level, clock signal CK is in first half period
Low level, and startup time and first half period are corresponding.It is the stage 1 shown in Fig. 2 to start the time.Inverting clock signal
XCK current potential is corresponding with clock signal CK current potential opposite.
The action process of GOA circuit structure of the present invention is：
Stage 1：CK is that L XCK are H, and STV L, M3, M4, M5, M10, M11, M12 openings, M1 grid voltage is L+
Vth, the Vth are M2 threshold voltage, and M1 is opened, and M2 grid voltage is H, and M2 is closed.The output of OUT terminal is XCK, for high electricity
It is flat.
Stage 2：CK is H, and XCK L, STV H, M10, M11, M12, M13, M6, M7 opening, M4, M3, M5, M8 are closed.
Because now M13 is opened, the grid voltage for ensureing M2 is H, M2 and M9 will not be caused to be opened by mistake because of M2 parasitic capacitance,
Cause output error.Meanwhile because the first electric capacity C1 maintains the current potential in stage 1, and because M1 parasitic capacitance, therefore M1
Grid voltage be less than 2L so that M1 is opened completely, OUT terminal output be XCK, be low level L.
Stage 3：CK is L, and XCK H, STV H, M12, M9, M8, M7 are opened so that M2 grid voltage is L+Vth, should
Locate the threshold voltage that Vth is M2, open M9, so that M1 grid voltage is H, then M2 is opened, and M1 is closed, OUT terminal output
VGH, it is high level.
20 above-mentioned GOA circuit structures are connected in series, the output end OUT of upper level GOA circuits is as next
The STV inputs of level GOA circuits, the i.e. grid with the M4 of next stage GOA circuits are connected.In the STV inputs of the 1st grade of GOA circuit
STV signals shown in end input Fig. 2, are inputted shown in Fig. 2 in the CK inputs and XCK inputs of every one-level GOA circuits
CK signals and XCK signals.
The simulation result figure of 1~4 grade of GOA circuit output finally given as shown in Figure 5 a, 16~20 grades of GOA circuit outputs
Simulation result figure as shown in Figure 5 b, in Fig. 5 b it can also be seen that the 20th grade of GOA circuit in the current potential of PU points and PD points.It can see
GOA circuits corresponding to going out can export normal waveform.
A C1 end is connected to output end OUT by the GOA circuits of the present invention, also adds M13, C4, during multistage is transmitted,
It can ensure to export more stable.Avoid because the parasitic capacitance effect of thin film transistor (TFT) causes opening by mistake and missing for thin film transistor (TFT)
Close, cause OUT terminal output error.
Above content is to combine specific preferred embodiment further description made for the present invention, it is impossible to is assert
The specific implementation of the present invention is confined to these explanations.For general technical staff of the technical field of the invention,
On the premise of not departing from present inventive concept, some simple deduction or replace can also be made, should all be considered as belonging to the present invention's
Protection domain.
Claims (8)
1. one kind scanning GOA circuits, it is characterised in that including：First film transistor, the second thin film transistor (TFT), the 3rd film
Transistor, the 4th thin film transistor (TFT), the first electric capacity；
The first end access inverting clock signal of the first film transistor, the second end of the first film transistor and institute
The first end connection of the second thin film transistor (TFT) is stated, and is used as output end；
3rd thin film transistor (TFT) grid access scan start signal, the first end of the 3rd thin film transistor (TFT) with it is described
The grid connection of second thin film transistor (TFT), the second end of the 3rd thin film transistor (TFT) and the second of second thin film transistor (TFT)
End connection and access high level signal；
The grid of 4th thin film transistor (TFT) connects with source electrode and accesses scan start signal, and drain electrode is brilliant with the first film
The grid connection of body pipe；
The both ends of first electric capacity respectively with the grid of the first film transistor and the first film transistor
Second end connects；
Wherein, first end is source electrode, and the second end is drain electrode, or first end is drain electrode, and the second end is source electrode.
2. scanning GOA circuits according to claim 1, it is characterised in that also include：It is 5th thin film transistor (TFT), the 6th thin
Film transistor, the 7th thin film transistor (TFT), the 8th thin film transistor (TFT)；
The grid of 6th thin film transistor (TFT) is connected with source electrode and accesses inverting clock signal, the 6th thin film transistor (TFT)
Drain electrode the grid with the 7th thin film transistor (TFT), the first end of the 5th thin film transistor (TFT) are connected respectively；
The grid of 8th thin film transistor (TFT) is connected with the first end of the 7th thin film transistor (TFT) and incoming clock signal, institute
The first end for stating the 8th thin film transistor (TFT) is connected with the second end of the 7th thin film transistor (TFT), the 8th thin film transistor (TFT)
Second end is connected with the first end of the 3rd thin film transistor (TFT)；
The grid of 5th thin film transistor (TFT) is connected with the grid of the 3rd thin film transistor (TFT) and accesses scan start signal,
Second end of the 5th thin film transistor (TFT) is connected with the second end of second thin film transistor (TFT).
3. scanning GOA circuits according to claim 2, it is characterised in that also include：It is 9th thin film transistor (TFT), the tenth thin
Film transistor, the 11st thin film transistor (TFT), the 12nd thin film transistor (TFT), the second electric capacity, the 3rd electric capacity；
The grid to drain by the tenth thin film transistor (TFT) and the first film transistor of 4th thin film transistor (TFT),
And the first end connection of the 12nd thin film transistor (TFT)；
Tenth thin film transistor (TFT) grid access scan start signal, the first end of the tenth thin film transistor (TFT) with it is described
The drain electrode connection of 4th thin film transistor (TFT), the second end of the tenth thin film transistor (TFT) and the grid of the first film transistor
Pole, and the first end connection of the 12nd thin film transistor (TFT)；
The grid access low level signal of 12nd thin film transistor (TFT), and the source electrode of the 12nd thin film transistor (TFT) and leakage
The other end of pole is connected with the first end of the 9th thin film transistor (TFT), the second end of the 9th thin film transistor (TFT) and described the
The second end connection of two thin film transistor (TFT)s, the grid of the 9th thin film transistor (TFT) connect with the grid of second thin film transistor (TFT)
Connect；
The grid access low level signal of 11st thin film transistor (TFT), the first end access of the 11st thin film transistor (TFT)
Scan start signal, the second end of the 11st thin film transistor (TFT) are connected with the grid of the 3rd thin film transistor (TFT)；
The both ends of second electric capacity grid with the 9th thin film transistor (TFT) respectively, and the 9th thin film transistor (TFT)
Second end connects；
The both ends of 3rd electric capacity connect with the source electrode of the 9th thin film transistor (TFT) and drain electrode respectively.
4. scanning GOA circuits according to claim 3, it is characterised in that also including the 4th electric capacity；
The both ends of 4th electric capacity connect with the source electrode of the 5th thin film transistor (TFT) and drain electrode respectively.
5. scanning GOA circuits according to claim 4, it is characterised in that also including the 13rd thin film transistor (TFT)；
Grid of the grid of 13rd thin film transistor (TFT) respectively with the first film transistor is connected, and the described 13rd is thin
The first end access high level signal of film transistor, the second end and second film crystal of the 13rd thin film transistor (TFT)
The grid connection of pipe.
6. scanning GOA circuits according to claim 5, it is characterised in that the first film transistor, the second film are brilliant
Body pipe, the 3rd thin film transistor (TFT), the 4th thin film transistor (TFT), the 5th thin film transistor (TFT), the 6th thin film transistor (TFT), the 7th film crystal
Pipe, the 8th thin film transistor (TFT), the 9th thin film transistor (TFT), the tenth thin film transistor (TFT), the 11st thin film transistor (TFT), the 12nd film are brilliant
Body pipe, the 13rd thin film transistor (TFT) are p-type metal-oxide-semiconductor.
7. scanning GOA circuits according to claim 5, it is characterised in that high level signal and low level signal are straight
Flow signal.
8. scanning GOA circuits according to claim 6, it is characterised in that scan start signal on startup between be low electricity
Flat, clock signal is low level in first half period, and the startup time and first half period are corresponding.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710860740.6A CN107403610B (en) | 2017-09-21 | 2017-09-21 | A kind of scanning GOA circuit |
| PCT/CN2017/109116 WO2019056508A1 (en) | 2017-09-21 | 2017-11-02 | Scan goa circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710860740.6A CN107403610B (en) | 2017-09-21 | 2017-09-21 | A kind of scanning GOA circuit |
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| CN107403610B CN107403610B (en) | 2019-10-11 |
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Also Published As
| Publication number | Publication date |
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| WO2019056508A1 (en) | 2019-03-28 |
| CN107403610B (en) | 2019-10-11 |
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