CN107393941B - Low-temperature microwave source, low-temperature microwave source chip and manufacturing method thereof - Google Patents

Low-temperature microwave source, low-temperature microwave source chip and manufacturing method thereof Download PDF

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CN107393941B
CN107393941B CN201710685503.0A CN201710685503A CN107393941B CN 107393941 B CN107393941 B CN 107393941B CN 201710685503 A CN201710685503 A CN 201710685503A CN 107393941 B CN107393941 B CN 107393941B
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transmission cavity
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CN107393941A (en
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郭国平
段鹏
孔伟成
贾志龙
薛光明
郭光灿
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University of Science and Technology of China USTC
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    • H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
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Abstract

The invention discloses a low-temperature microwave source, a low-temperature microwave source chip and a manufacturing method thereof, wherein the chip comprises a substrate, a transmission cavity, a bias junction, a voltage bias line and a direct current bias line, wherein the transmission cavity, the bias junction, the voltage bias line and the direct current bias line are positioned on the surface of the substrate; the transmission cavity comprises a SQUID chain for emitting microwave photons; the bias junction is electrically connected with the transmission cavity and is used for generating microwave photons; the voltage bias line is used for applying bias voltage to the bias junction to convert the electron Cooper pairs in the bias junction into microwave photons in a stimulated emission mode; the direct current bias line is used for applying a magnetic field to the transmission cavity; wherein the resonant frequency of the transmission cavity is determined by the total capacitance and total inductance of the SQUID chain; the total inductance of the SQUID chain varies with the magnitude of the magnetic field, which varies with the magnitude of the current in the dc bias line. The low-temperature microwave source chip provided by the invention generates microwave photons in a stimulated emission mode, ensures the stability of the frequency, amplitude and phase of the emitted microwave photons, and meets the requirements of a microwave source.

Description

Low-temperature microwave source, low-temperature microwave source chip and manufacturing method thereof
Technical Field
The invention relates to a microwave circuit element, in particular to a low-temperature microwave source, a low-temperature microwave source chip and a manufacturing method thereof.
Background
In the field of solid-state quantum computing, the quantum characteristics of qubits can be fully highlighted only by placing a quantum chip in an extremely low temperature environment, and the influence of environmental noise on quantum coherence needs to be suppressed. However, in the prior art, the measurement techniques used for manipulating the qubits are all performed by using classical instruments, and for example, the microwave sources used for manipulating the qubits are difficult to meet the requirements of current solid-state quantum chip manipulation and quantum computation.
In the prior art, a microwave source used for controlling a qubit has the problem of large noise on one hand, and on the other hand, because the microwave source is applied through a room-temperature line, complicated optimization designs such as filtering and attenuation need to be performed before a microwave signal reaches a very-low-temperature quantum chip from room temperature, but the optimized microwave signal still cannot meet the requirements of solid-state quantum chip control and quantum computation.
Disclosure of Invention
In view of the above, the present invention provides a low temperature microwave source, a low temperature microwave source chip and a manufacturing method thereof, wherein the manufacturing process of the low temperature microwave source chip is compatible with the process of a quantum chip, and the low temperature microwave source chip can be directly integrated onto the quantum chip, so that in-situ control can be directly performed on a quantum bit, and the problem of the microwave source in the prior art is solved.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
a low-temperature microwave source chip comprises a substrate, a transmission cavity, a bias junction, a voltage bias line and a direct current bias line, wherein the transmission cavity, the bias junction, the voltage bias line and the direct current bias line are positioned on the surface of the substrate;
wherein the transmission cavity is used for emitting microwave photons, the transmission cavity comprises a SQUID chain, the SQUID chain comprises a plurality of SQUID structures, and the SQUID structures are connected in series;
the bias junction is electrically connected with the transmission cavity and is used for generating microwave photons;
the voltage bias line is used for applying bias voltage to the bias junction to convert the electron Cooper pairs in the bias junction into microwave photons in a stimulated emission mode;
the direct current bias line is used for applying a magnetic field to the transmission cavity;
wherein the resonant frequency of the transmission cavity is determined by the total capacitance and total inductance of the SQUID chain; the total inductance of the SQUID chain changes with the change of the magnitude of the magnetic field, and the magnitude of the magnetic field changes with the change of the magnitude of the current in the direct current bias line.
Preferably, the total inductance of the transmission cavity is greater than the total inductance of the bias junction, so that the electron cooper pair can tunnel through the bias junction by generating or absorbing a photon under constant voltage bias.
Preferably, the emission rate of the microwave photons emitted from the transmission cavity is smaller than the tunneling rate of the electron cooper pair tunneling through the bias junction, so that the microwave photons are absorbed by the electron cooper pair again before being emitted, so as to promote the next tunneling of the electron cooper pair to continuously generate the microwave photons.
Preferably, the SQUID structure is a ring structure formed by two josephson junctions connected in parallel;
the Josephson junction includes a first superconducting layer, an insulating layer, and a second superconducting layer sequentially on the surface of the substrate.
Preferably, the dc bias line includes an elongated electrode strip, and a long side of the electrode strip is parallel to the SQUID chain.
Preferably, the substrate surface further includes a metal layer besides the transmission cavity, the bias junction, the voltage bias line, and the dc bias line, the metal layer surrounds the transmission cavity, the bias junction, the voltage bias line, and the dc bias line, and the metal layer, the voltage bias line, and the dc bias line are formed in the same photolithography process;
the transmission cavity, the metal layer and the direct current bias line which are respectively positioned at the two sides of the transmission cavity form a coplanar waveguide structure;
the direct current bias line and the metal layer around the direct current bias line form a coplanar waveguide structure.
Preferably, the bias junction is a josephson junction.
Preferably, one end of the bias junction is directly connected to the output end of the transmission cavity, and the other end of the bias junction is directly connected to the metal layer.
Preferably, the formation direction of the bias junction is consistent with the formation direction of the josephson junction in the SQUID chain transmission cavity, so that the bias junction and the SQUID chain are formed in the same process step.
Preferably, the connection mode of the bias junction and the output end of the transmission cavity is as follows: a long strip-shaped conductive material is extended out of the long edge of the transmission cavity and is close to the output end of the transmission cavity to serve as a first connecting line, and the first connecting line is in direct contact with the first edge of the bias junction;
the bias junction and the metal layer are connected in the following mode: and a strip-shaped conductive material is extended from the second edge of the bias junction to serve as a second connecting line, a strip-shaped conductive material is extended from the metal layer in the direction towards the bias junction to serve as a third connecting line, the second connecting line is directly connected with the third connecting line, the included angle between the second connecting line and the third connecting line is a right angle, and the first edge and the second edge of the bias junction are two opposite edges along the length direction of the transmission cavity.
Preferably, the first connecting line, the second connecting line and the bias junction are formed in the same process step; the third connecting line and the metal layer are formed in the same process step.
Preferably, the connection mode of the bias junction and the output end of the transmission cavity is as follows: a long strip-shaped conductive material is extended out of the long edge of the transmission cavity and is close to the output end of the transmission cavity to serve as a first connecting line, and the first connecting line is in direct contact with the first edge of the bias junction;
the bias junction and the metal layer are connected in the following mode: and a strip-shaped conductive material is extended from the second edge of the bias junction to serve as a fourth connecting line, a strip-shaped conductive material is extended from the metal layer towards the bias junction to serve as a third connecting line, a conductive material extended from the tail part of the third connecting line towards the fourth connecting line serves as a fifth connecting line, the fourth connecting line is in lap joint with the fifth connecting line, the included angle between the third connecting line and the fifth connecting line is a right angle, and the first edge and the second edge of the bias junction are two opposite edges along the length direction of the transmission cavity.
Preferably, the first connection line, the fourth connection line and the bias junction are formed in the same process step, and the third connection line, the fifth connection line and the metal layer are formed in the same process step.
Preferably, the voltage bias line comprises an electrode plate and an inductor surrounding the electrode plate, wherein a first end of the inductor is directly connected with the electrode plate, and a second end of the inductor is connected with the transmission cavity.
Preferably, the transmission cavity is a half-wavelength resonant cavity, the center position of the transmission cavity is a voltage node, and the second end of the inductor is directly connected with the center position of the transmission cavity.
Preferably, the relationship between the output end of the transmissive cavity and the first coupling capacitor C1 between the metal layers and the input end of the transmissive cavity and the second coupling capacitor C2 between the metal layers is C1: c2 is more than or equal to 10:1, and the emitting speed omega of the microwave photons from the output end of the transmission cavity is proportional to C12。
Preferably, the resonant frequency f of the transmission cavity and the constant voltage U applied to the voltage bias line satisfy the relation mhf ═ 2eU, where m is a positive integer, h is a planckian constant, and e is an electric quantity of one electron; wherein the resonant frequency of the transmissive cavity is equal to the output frequency of the low temperature microwave source.
Preferably, the total inductance L ═ L of the transmissive cavity0+nLj-2, the total capacitance of said transmission cavity, C ═ nc + cj, resonance frequency
Figure BDA0001376621330000041
Wherein L isjInductance of a single Josephson junction, L0The inductance between the SQUID chain and the metal layer, c is the capacitance between a single SQUID structure and the metal layer, cj is the capacitance of the SQUID chain, and n is the number of the SQUID structures on the SQUID chain.
Preferably, the materials of the transmission cavity, the bias junction, the voltage bias line, the direct current bias line and the metal layer are all low-temperature superconducting materials.
Preferably, the metal layer, the voltage bias line, and the dc bias line are made of aluminum, niobium nitride, or titanium niobium nitride.
Preferably, the material of the transmission cavity and the bias junction is aluminum.
Preferably, the microwave source chip further comprises a metal heat sink located on a surface of the substrate facing away from the metal layer, so as to dissipate heat of the low-temperature microwave source chip.
The invention also discloses a low-temperature microwave source, which comprises a control circuit and the low-temperature microwave source chip of any one of claims 1 to 19, wherein the control circuit is used for applying working voltage to the low-temperature microwave source chip to enable the low-temperature microwave source chip to generate and emit microwave photons;
the control circuit comprises a constant current source and a voltage stabilizing circuit connected with the voltage bias line;
the constant current source is used for providing power supply input for the voltage stabilizing circuit;
the voltage stabilizing circuit is used for providing bias voltage for a bias junction of the low-temperature microwave source;
the constant current source is arranged in a room temperature environment, the low-temperature microwave source chip is arranged in a low-temperature environment, the voltage stabilizing circuit comprises a room temperature voltage stabilizing circuit and a low-temperature voltage stabilizing circuit, and the low-temperature voltage stabilizing circuit and the low-temperature microwave source chip are arranged in the same environment.
Preferably, the room temperature voltage stabilizing circuit comprises a first low-pass filter electrically connected with the constant current source and used for eliminating voltage fluctuation caused by noise on a circuit;
the low temperature voltage stabilizing circuit includes:
a second low-pass filter electrically connected to the first low-pass filter for eliminating voltage fluctuations due to noise on the circuit;
the first voltage dividing resistor and the second voltage dividing resistor are connected with the voltage bias line in series, the first end of the first voltage dividing resistor is electrically connected with the first end of the second voltage dividing resistor, the second end of the first voltage dividing resistor is grounded through the first grounding impedance element, the second end of the second voltage dividing resistor is electrically connected with the electrode plate of the voltage bias line, and the metal layer is grounded in the working process;
the output end of the constant current source is electrically connected with the first end of the first divider resistor through a first low-pass filter and a second low-pass filter, and the bias voltage provided by the constant current source is applied to two ends of a bias junction through the inductance of the voltage bias line, the transmission cavity and the metal layer in the working process.
Preferably, the room temperature voltage stabilizing circuit further comprises:
the differential voltmeter is used for detecting the voltage at two ends of the second voltage-dividing resistor;
a third low-pass filter and a fourth low-pass filter for eliminating voltage fluctuation due to noise on the circuit;
the low temperature voltage stabilizing circuit further comprises:
a fifth low-pass filter and a sixth low-pass filter for eliminating voltage fluctuation due to noise on the circuit;
a first capacitor and a second grounding impedance element, a second capacitor and a third grounding impedance element for isolating thermal noise on the circuit;
the first end of the differential voltmeter is connected with the first end of the second divider resistor through the third low-pass filter and the fifth low-pass filter, and the second end of the differential voltmeter is connected with the second end of the second divider resistor through the fourth low-pass filter and the sixth low-pass filter; a first polar plate of the first capacitor is connected with a first end of the second divider resistor, and a second polar plate is grounded through the second grounding impedance element; a first pole plate of the second capacitor is connected with a second end of the second divider resistor, and the second pole plate is grounded through the third grounding impedance element;
the voltage applied to the voltage bias line is IR1- [ (R1/R2) +1] U ', where R1 is the resistance value of the first voltage-dividing resistor, R2 is the resistance value of the second voltage-dividing resistor, I is the current value of the constant current source, and U' is the voltage across the second voltage-dividing resistor.
Preferably, the number of the first low-pass filter and the number of the sixth-pass filter are at least one, the wires used for connecting each circuit element in the low-temperature voltage stabilizing circuit are low-temperature direct-current wires, and the low-temperature microwave source chip and the low-temperature voltage stabilizing circuit are arranged on the same circuit board.
Preferably, the control circuit further comprises a current regulating circuit and a direct current source connected to the direct current bias line;
the direct current source is used for outputting current to the direct current bias line;
the current adjusting circuit is used for adjusting the current output from the direct current source to the direct current bias line.
Preferably, the output frequency of the low-temperature microwave source is within 1GHz-10GHz, the regulation rate of the output frequency is in the order of hundred nanoseconds, the output power is within-90 dBm to-140 dBm, and the energy conversion efficiency is more than 10%.
The invention also discloses a manufacturing method of the low-temperature microwave source chip, which is used for manufacturing the low-temperature microwave source chip and comprises the following steps:
providing a substrate;
forming a metal layer on the substrate;
in the same process step, removing all metal layers in a transmission cavity area and a bias junction area, and removing partial metal layers in a voltage bias line area and a direct current bias line area to form a voltage bias line and a direct current bias line, and forming an input end and an output end at two ends of the transmission cavity area, wherein the output end is positioned at one side close to the bias junction area;
in the same process step, a transmission cavity comprising a SQUID chain is formed on the surface of the substrate of the transmission cavity region, and a bias junction is formed on the surface of the substrate of the bias junction region.
Preferably, the voltage bias line includes an electrode plate and an inductor surrounding the electrode plate, the dc bias line includes an elongated electrode strip, all the metal layers of the transmissive cavity region and the bias junction region are removed, and a part of the metal layers of the voltage bias line region and the dc bias line region are removed to form the voltage bias line and the dc bias line, including:
forming a photoresist layer on the surface of the metal layer, wherein the photoresist layer covers the electrode plate, the inductor and the long-strip-shaped electrode strip region, and exposes the transmission cavity region, the bias junction region and the metal layer in a certain region around the inductor and the electrode strip;
etching the metal layer material which is not covered by the photoresist layer by taking the photoresist layer as a mask;
and removing the photoresist layer, and reserving the electrode plate, the inductor and the long-strip-shaped electrode strip.
Preferably, forming a transmission cavity including a SQUID chain on a substrate surface of the transmission cavity region and forming a bias junction on a substrate surface of the bias junction region includes:
sequentially forming a first photoresist layer and a second photoresist layer on the substrate surface of the transmission cavity region and the substrate surface of the offset junction region;
exposing and developing the first photoresist layer and the second photoresist layer to form a plurality of suspension bridge structures which are sequentially arranged along the length direction of the transmission cavity area, wherein the suspension bridge structures are formed by the second photoresist layer with the first photoresist layer at the bottom removed;
forming a first superconducting layer on the surface of the substrate by using the suspension bridge structure as a mask and adopting a first incidence angle;
oxidizing a surface of the first superconducting layer to form an insulating layer;
forming a second superconducting layer on the surface of the insulating layer by using the suspension bridge structure as a mask and adopting a second incidence angle;
wherein a stack of the first superconducting layer, the insulating layer, and the second superconducting layer formed in a region under the suspension bridge structure constitutes the josephson junction, and the josephson junction formed in the bias junction region is the bias junction; in the length direction of the transmission cavity, superconducting layer materials between two adjacent suspension bridge structures form a conductive interval structure, in the width direction of the transmission cavity, two Josephson junctions respectively positioned at two sides of the suspension bridge structures are connected in parallel through the conductive interval structure to form the SQUID structure, and in the length direction of the transmission cavity, a plurality of SQUID structures are connected in series through the conductive interval structure to form the SQUID chain.
Compared with the prior art, the technical scheme provided by the invention at least has the following advantages:
the invention provides a low-temperature microwave source, a low-temperature microwave source chip and a manufacturing method thereof, the low-temperature microwave source comprises a low-temperature microwave source chip and a control circuit, the control circuit is used for applying working voltage to the low-temperature microwave source chip to enable the low-temperature microwave source chip to generate and emit microwave photons, wherein, the transmission cavity, the bias junction, the voltage bias line, the direct current bias line and the like on the low-temperature microwave source chip are all manufactured by a semiconductor process, the manufacturing process is compatible with the manufacturing process of the quantum chip, so the low-temperature microwave source chip and the quantum chip can be integrated together, in the working process, the low-temperature microwave source chip and the quantum chip are jointly in the low-temperature environment, so that the microwave photons emitted by the low-temperature microwave source chip can directly carry out in-situ control on the qubit in the low-temperature environment, and various defects of applying a microwave source through a room-temperature line in the prior art are avoided.
In addition, the low-temperature microwave source chip provided by the invention generates microwave photons in a stimulated emission mode, ensures the stability of the frequency, amplitude and phase of the emitted microwave photons, and meets the requirements of a microwave source. Meanwhile, the output frequency of the low-temperature microwave source is the resonant frequency of the transmission cavity, and the resonant frequency of the transmission cavity can be adjusted by adjusting the current in the direct-current bias line, so that the output frequency range required by the control of the quantum chip can be met.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a top view of a low-temperature microwave source chip according to an embodiment of the present disclosure;
fig. 2 is an enlarged top view of a SQUID chain structure in a low-temperature microwave source chip according to an embodiment of the present disclosure;
FIG. 3 is a cross-sectional view of a Josephson junction;
FIG. 4 is a schematic diagram of the manner in which the voltage bias lines are connected to the transmissive cavity;
FIGS. 5 a-5 b are enlarged top views of two bias junction connections provided in accordance with embodiments of the present application;
fig. 6-7 are top views of steps of a method for manufacturing a low-temperature microwave source chip according to an embodiment of the present disclosure;
FIG. 8 is a top view of the transmission cavity region and the bias junction region after photolithography;
FIG. 9 is a cross-sectional view of the suspension bridge structure D in the transmissive cavity region cut along AA';
FIG. 10 is a cross-sectional view of the suspension bridge structure D of the transmission cavity region cut along BB';
FIGS. 11-13 are sectional views of steps of a Josephson junction fabrication method;
FIG. 14 is an enlarged top view of the offset junction region after photolithography;
FIG. 15 is a cross-sectional view of the cantilever structure D of the offset junction region cut along AA';
FIG. 16 is a cross-sectional view of the bridge structure D of the offset junction region cut along BB';
fig. 17 is a circuit structure diagram of a low-temperature microwave source according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a low-temperature microwave source chip, and particularly, as shown in fig. 1, the low-temperature microwave source chip is a top view of the low-temperature microwave source chip, and the low-temperature microwave source chip includes a substrate 1, and a transmission cavity 2, a bias junction 4, a voltage bias line 5, and a direct current bias line 3 which are located on a surface of the substrate 1.
The substrate 1 is a semiconductor substrate, such as silicon or sapphire. Because the dielectric loss of the monocrystalline silicon and the sapphire materials is the lowest, the working performance of the low-temperature microwave source chip can be ensured to reach the optimal state. Alternatively, the substrate 1 may be a sapphire substrate having a crystal orientation of 100 and a thickness of 0.5 mm. Further, the sapphire substrate may have a scattering tangent of 2e-7. In this embodiment, the low-temperature microwave source chip is fabricated on a semiconductor substrate by a semiconductor nano-fabrication technique, and the overall size of the low-temperature microwave source chip is smaller than 1mm × 1 mm.
Specifically, the transmission cavity 2 is used for emitting microwave photons, the transmission cavity 2 comprises a SQUID chain, the SQUID chain comprises a plurality of SQUID structures, and the SQUID structures are connected in series;
the bias junction 4 is electrically connected with the transmission cavity 2 and is used for generating microwave photons;
the voltage bias line 5 is used for applying bias voltage to the bias junction 4 to enable the electron Cooper pairs in the bias junction 4 to be converted into microwave photons in a stimulated emission mode;
the direct current bias line 3 is used for applying a magnetic field to the transmission cavity 2;
wherein the resonant frequency of the transmission cavity 2 is determined by the total capacitance and total inductance of the SQUID chain; the total inductance of the SQUID chain changes with the change of the magnitude of the magnetic field, and the magnitude of the magnetic field changes with the change of the magnitude of the current in the direct current bias line.
It should be noted that the surface of the substrate 1 further includes a metal layer 6 in addition to the transmissive cavity 2, the bias junction 4, the voltage bias line 5, and the dc bias line 3, as shown in fig. 1, the metal layer 6 surrounds the transmissive cavity 2, the bias junction 4, the voltage bias line 5, and the dc bias line 3, and the metal layer 6, the voltage bias line 5, and the dc bias line 3 are formed in the same photolithography process.
The metal layer 6 in this embodiment is grounded. It can be understood by those skilled in the art that as long as the low-temperature microwave source chip and the quantum chip are in an integrated state, when the quantum chip is placed in a low-temperature environment, the low-temperature microwave source chip is also placed in a low-temperature environment, and the metal layer 6 is in a grounded state regardless of whether the low-temperature microwave source including the low-temperature microwave source chip is in an operating state or not.
The embodiment of the invention adopts a stimulated emission mode to generate microwave photons, so that the design of the transmission cavity, the bias junction and the bias voltage applied to the bias junction can meet the condition of stimulated emission.
It should be noted that the host for generating microwave photons by stimulated emission is an electron cooper pair in a biased junction, where the electron cooper pair is two electrons located near the fermi surface, and a bound state is formed due to a net attraction, and the bound state is the cooper pair, and the two corresponding electrons are the electron cooper pair, or is called the cooper pair. The fermi surface is an isoenergetic surface in the momentum space of the electron state in a metal.
If the electron cooper pair is to be stimulated to emit photons, it is necessary to provide sufficient energy to the electron cooper pair to break loose from its bound state on the fermi surface, i.e. to allow the electron to undergo an energy level transition, in other words, to allow the electron cooper pair in the bias junction to tunnel through the bias junction. The premise that the electron Cooper pair tunnels through the bias junction is that in a superconducting state, the electron Cooper pair can realize tunneling through the bias junction if and only if absorbing or releasing energy equivalent to 2eU under the premise that constant voltage U is applied to two ends of the bias junction.
The bias junction in this embodiment is connected to the transmissive cavity so that the portion of energy required for electron tunneling can be provided by the electron generating or absorbing a photon. However, the premise that the electron can generate or absorb a photon is that the resonant frequency f of the transmission cavity and the constant voltage U applied to the voltage bias line satisfy the relation mhf ═ 2eU, where m is a positive integer, h is the planck constant, h ≈ 6.626 × 10^ -34J · s, and e is the electric quantity of an electron. The microwave photons generated by the stimulated emission mode are finally output from the transmission cavity, and the microwave photons generated and emitted by the stimulated emission mode have high stability in frequency, amplitude and phase, so that the requirement of a microwave source is met.
To ensure the tunneling of the electron cooper pair, and the tunneling process of the electron cooper pair is infinitely cycled, the following two conditions need to be satisfied, condition 1 is a coupling condition, and condition 2 is a stimulated emission condition:
1) the microwave source meets the following equation when in work:
Figure BDA0001376621330000101
wherein the content of the first and second substances,
Figure BDA0001376621330000102
representing the total phase of the current, κ, of the microwave photons in the transmission cavitycDenotes the total dissipation of the transmission cavity, IjIn order to bias the junction critical current,
Figure BDA0001376621330000103
in order to be a quantum magnetic flux,
Figure BDA0001376621330000104
is magnetic flux passing through the interior of the SQUID chain, where ω0F is the resonant frequency of the transmission cavity, kc=Ω+κiOmega is the photon emission rate at the output port of the transmission cavity, kappaiAs is the rate of energy dissipation inside the transmissive cavity,
Figure BDA0001376621330000111
l is the total inductance of the transmission cavity and Lj is the total inductance of the bias junction.
In order to make the microwave source work effectively, on the basis of applying a constant bias voltage to two ends of the bias junction, energy released in the process of tunneling through the bias junction by electron couette pairs needs to be ensuredThe efficiency of conversion into microwave photons is high enough, i.e. the bias junction and the transmission cavity need to be well coupled, corresponding to the above equation, the ratio of the photon generation term (i.e. the fourth term in the equation) to the third term in the equation needs to be greater than 1, i.e. the ratio of the photon generation term to the third term in the equation is large enough
Figure BDA0001376621330000112
Obtaining L/L by equivalent transformationj＞1。
That is to say, in order to realize tunneling, the total inductance L of the transmission cavity 2 in this embodiment needs to be greater than the total inductance Lj of the bias junction 4, so that the electron cooper pair can tunnel through the bias junction by generating or absorbing one photon under the condition of constant voltage bias, whereas if the total inductance L of the transmission cavity 2 is smaller than the total inductance Lj of the bias junction 4, the electron cooper pair cannot complete the process of generating or absorbing one photon.
In order to satisfy this condition, the bias junction 4 in the present embodiment is a josephson junction including a first superconducting layer, an insulating layer, and a second superconducting layer in this order on the surface of the substrate, and the transmission chamber 2 is formed using a SQUID chain, and a specific formation method is described in detail in the following embodiments.
The structure of the transmission cavity 2 is shown in fig. 1-2, fig. 2 is an enlarged view of a SQUID chain structure, the SQUID chain comprises a plurality of SQUID structures 20, the SQUID structures 20 are connected in series, and a conductive spacing structure 23 is arranged between the SQUID structures 20. Specifically, the SQUID structure 20 is a ring structure formed by two parallel josephson junctions 21, a blank region 22 is formed between the two josephson junctions 21, the substrate material is directly exposed on the blank region 22, the two josephson junctions 21 are connected in parallel through conductive spacer structures 23 located at two sides of the blank region, that is, the two josephson junctions 21 are connected in parallel through the conductive spacer structures 23 arranged between the adjacent SQUID structures. Also, the plurality of SQUID structures are connected in series by conductive spacer structures 23 disposed between adjacent SQUID structures.
As shown in fig. 3, which is a cross-sectional view of a josephson junction 21, the structure of the josephson junction 21 is a sandwich structure consisting of a superconducting metal layer/(insulating layer or semiconductor layer)/superconducting metal layer, and the material used in each layer directly affects the physical properties of the josephson junction. In order to meet the performance requirements of the low-temperature microwave source chip in this embodiment, it is preferable that the structure of the josephson junction 21 includes a first superconducting layer 211, an insulating layer 212, and a second superconducting layer 213, which are sequentially located on the surface of the substrate 1. First superconducting layer 211 and second superconducting layer 213 are formed using a low-temperature superconducting material, and insulating layer 212 is formed by oxidizing the surface of first superconducting layer 211. Further, since the process of preparing the josephson junction by using other superconducting metal materials is complicated, in this embodiment, in order to simplify the fabrication process of the transmission cavity and to make the fabrication process of the transmission cavity compatible with the fabrication process of the subsequent quantum chip, so as to facilitate the integration of the low-temperature microwave source chip and the quantum chip, it is preferable that the first superconducting layer 211 and the second superconducting layer 213 are made of aluminum, and the insulating layer 212 is made of aluminum oxide.
In the SQUID structure 20 of the present embodiment, two josephson junctions 21 are formed in the same process step as the bias junction 4, and the conductive spacer 23 is also formed during the formation of the josephson junctions 21, but the cross-sectional structures of the conductive spacer 23 are different according to different regions and different sizes, which will be described in detail in the following method embodiments.
The two josephson junctions 21 in the SQUID structure 20 in this embodiment are formed in the same process step as the bias junction 4. I.e. if the inductance of the bias junction 4 is the inductance L of a josephson junction0The total inductance L of the transmission cavity is the sum of the inductances of all Josephson junctions on the SQUID chain and the inductance L between the SQUID chain and the ground0I.e. L is nLj/2+ L0And n is the number of josephson junctions on the SQUID chain. The number of josephson junctions in the transmission cavity in the embodiment is hundreds, so that the total inductance of the transmission cavity is about dozens of times or even hundreds of times of that of the bias junction, and the coupling condition of microwave photon emission is met.
2) In order to make the stimulated emission process of the electron cooper pair circulate infinitely, the microwave photon is continuously emitted under the constant voltage bias, and the size of the emission rate omega when the microwave photon is emitted from the transmission cavity is also required to be controlled, namely, the emission rate omega when the microwave photon is emitted from the transmission cavity is ensured to be smaller than the tunneling rate when the electron cooper pair tunnels through the bias junction 4, namely, the tunneling rate is larger than omega, so that the microwave photon is absorbed by the electron cooper pair again before being emitted, the next tunneling of the electron cooper pair is promoted, and the continuous tunneling of the electron cooper pair is promoted, and the microwave photon is continuously generated.
Specifically, I is the actual dc current passing through the bias junction when the bias voltage U is applied across the bias junction, and if m in formula mhf ═ 2eU is larger, I is larger, and the tunneling rate of electron cooper pairs tunneling through the bias junction 4 is larger.
The emission rate of the microwave photons emitted from the transmission cavity is determined by the coupling capacitance between the input end 24 and the output end 25 of the transmission cavity and the metal layer 6, specifically, the coupling capacitance between the output end of the transmission cavity and the metal layer is a first coupling capacitance C1, the coupling capacitance between the input end of the transmission cavity and the metal layer is a second coupling capacitance C2, and the rate of the microwave photons emitted from the transmission cavity is proportional to (C1)2+C22) Wherein the rate Ω (i.e., the effective rate) of microwave photons emitted from the output end of the transmission cavity is proportional to C12。
In this embodiment, the sizes of C1 and C2 are reduced as much as possible, so that the emission rate Ω of microwave photons emitted from the transmission cavity is reduced, and the bias voltage U across the bias junction is increased as much as possible, so that the tunneling rate of electron cooper tunneling through the bias junction 4 is increased, thereby satisfying > Ω.
Specifically, the sizes of C1 and C2 can be adjusted by adjusting the shapes of the port electrodes between the input and output ends of the transmission cavity and the metal layer, for example, decreasing the distance between the port of the transmission cavity and the metal layer and decreasing the facing area between the port of the transmission cavity and the metal layer, so that C1 and C2 can be decreased.
In the embodiment, through the transmission cavity with the structure, the electron cooper pairs in the bias junction 4 are ensured to be continuously excited, so that microwave photons are continuously emitted, and the function of a microwave source is realized.
Specifically, as shown in fig. 1, in the embodiment of the present invention, one end of the bias junction 4 is directly connected to the output end of the transmission cavity 2, and the other end is directly connected to the metal layer 6, that is, in the working process, the bias junction 4 is directly grounded through the metal layer 6, so that the coupling strength between the bias junction 4 and the transmission cavity 2 is enhanced to the maximum extent, the loss of signals is avoided, and the energy conversion efficiency of the low-temperature microwave source is improved.
In this embodiment, the formation direction of the bias junction 4 is the same as the formation direction of the josephson junction in the SQUID chain transmission cavity, so that the bias junction and the SQUID chain are formed in the same process step. At least two connection modes of the bias junction region are described below, and the following description is respectively provided with reference to the drawings.
As shown in fig. 5a, the metal around the offset junction 4 is arranged in a meander shape, connected to the metal layer 6 and the output 25 of the transmission cavity, respectively. Specifically, the connection mode of the bias junction 4 and the output end 25 of the transmission cavity 2 is as follows: a long strip-shaped conductive material is extended from the long side of the transmission cavity 2 and near the output end 25 of the transmission cavity 2 to serve as a first connecting line 43, and the first connecting line 43 is in direct contact with the first edge 41 of the bias junction 4. The bias junction 4 and the metal layer 8 are connected in the following manner: a strip-shaped conductive material is extended from the second edge 42 of the bias junction 4 to serve as a second connection line 44, a strip-shaped conductive material is extended from the metal layer 6 in the direction towards the bias junction to serve as a third connection line 45, the second connection line 44 is directly connected with the third connection line 45, the included angle between the second connection line and the third connection line is a right angle, and the first edge 41 and the second edge 42 of the bias junction are two opposite edges along the length direction of the transmission cavity. In order to increase the process speed, the first connection line 43, the second connection line 44 and the bias junction 4 are formed in the same process step, and the third connection line 45 and the metal layer 6 are formed in the same process step.
In other embodiments, due to the different selection of the photolithography process and the different time spent by the process, if the connecting line around the offset junction is formed by using the electron beam direct writing exposure method, the problem of process efficiency needs to be considered, so in order to improve the photolithography process efficiency for forming the connecting line around the offset junction, the connection method of the offset junction 4 with the transmission cavity 2 and the metal layer 6 is as shown in fig. 5b, specifically, the connection method of the offset junction 4 with the output end 25 of the transmission cavity 2 is as follows: and a long strip-shaped conductive material is extended from the long edge of the transmission cavity 2 and is close to the output end of the transmission cavity 2 to be used as a first connecting line 43, and the first connecting line 43 is directly contacted with the first edge of the bias junction 4.
The bias junction 4 and the metal layer 6 are connected in the following manner: a strip-shaped conductive material is extended from the second edge of the bias junction 4 to serve as a fourth connecting line 46, a strip-shaped conductive material is extended from the metal layer towards the bias junction to serve as a third connecting line 45, a strip-shaped conductive material is extended from the tail of the third connecting line 45 towards the fourth connecting line 46 to serve as a fifth connecting line 47, the fourth connecting line 46 is in lap joint with the fifth connecting line 47, an included angle between the third connecting line 45 and the fifth connecting line 47 is a right angle, and the first edge 41 and the second edge 42 of the bias junction are two opposite edges along the length direction of the transmission cavity.
Wherein the first connection line 43, the fourth connection line 46 and the bias junction 4 are formed in the same process step, and the third connection line 45, the fifth connection line 47 and the metal layer 6 are formed in the same process step.
It should be noted that whether the bias voltage applied across the bias junction is stable directly determines whether the output frequency of the low-temperature microwave source is stable, and based on this, referring to fig. 1, the voltage bias line 5 in this embodiment includes an electrode plate 51 and an inductor 52 surrounding the electrode plate 51, and during the operation of the low-temperature microwave source, the electrode plate 51 is connected to a circuit outside the low-temperature microwave source chip and is used for receiving a constant bias voltage provided by the external circuit for the low-temperature microwave source chip. The inductor 52 has a first terminal directly connected to the electrode plate 51 and a second terminal connected to the transmissive cavity 2, and applies a bias voltage from an external circuit to a bias junction via the electrode plate 51 and the inductor 52.
In the working process of the low-temperature microwave source, the inductor 52 can play a role of a filter, on one hand, energy leakage in the transmission cavity can be prevented, and on the other hand, adverse effects on the performance of the low-temperature microwave source caused by external high-frequency noise entering the transmission cavity can be prevented, so that the stability of the bias voltage is improved to a certain extent. In addition, other external circuits are added to the low-temperature microwave source to ensure the stability of the bias voltage, and for the specific structure of the external circuit, the following embodiments will explain this in detail, and will not be described here again.
In addition to the above arrangement of the voltage bias line structure, in order to ensure that the bias voltage of the voltage bias line can be effectively applied to the bias junction and at the same time reduce the influence of the bias voltage on the microwave signal in the transmission cavity to the maximum extent, in this embodiment, the bias voltage is preferably applied to the position of the voltage node of the transmission cavity, and preferably, the transmission cavity 2 in this embodiment is a half-wavelength resonant cavity, the central position of the transmission cavity 2 is the voltage node, and the electric field intensity of the transmission cavity is the weakest at this position, so that the second end of the inductor 52 on the voltage bias line 5 in this embodiment is directly connected to the central position of the transmission cavity 2, that is, the bias voltage is applied to the center of the transmission cavity, so as to weaken the influence of the bias voltage on the microwave signal in the transmission cavity to the maximum extent, as shown in fig.
It will be appreciated by those skilled in the art that the use of a quarter wavelength reflective cavity results in no effective location for the bias voltage to be applied, and hence stimulated emission of the electron cooper pair is not achieved. However, since the half-wavelength resonant cavity has two ports, i.e. an input port and an output port, in this embodiment, in order to ensure that the microwave photons are output through the output port of the transmission cavity and to minimize the signal loss caused by the leakage of the microwave photons from the input port of the transmission cavity, it is preferable that the size relationship between C1 and C2 is C1: c2 ≈ 10:1, more preferably, C1: c2 is more than or equal to 10: 1.
It should be noted that, in the present embodiment, the output frequency of the low temperature microwave source is the frequency of the output signal of the low temperature microwave source, the output frequency of the low temperature microwave source is determined by the resonant frequency f of the transmissive cavity, and the output frequency of the low temperature microwave source in the present embodiment is equal to the resonant frequency f of the transmissive cavity. While the resonant frequency f of the transmission cavity is determined by the total capacitance and total inductance on the SQUID chain.
It should be noted that the SQUID structure is a superconducting quantum interference device, as described above, the SQUID structure is formed by connecting two superconducting josephson junctions in parallel to form a ring, and the magnitude of the critical current of the path in the SQUID structure is changed by adjusting the vertical magnetic field energy in the SQUID structure, so as to change the magnitude of the inductance of the SQUID structure, that is, the magnitude of the total inductance of the SQUID chain, and further change the resonant frequency f of the transmission cavity.
The specific principle is that the total inductance L of the transmission cavity 2 is L0+ nLj/2, where Lj is the inductance of a single josephson junction, and L0 is the inductance between the SQUID chain and the coplanar waveguide ground plane, that is, L0 is the inductance between the SQUID chain and the metal layer 6, and in practice, L0 is 1 to 2 orders of magnitude smaller than nLj/2, and L0 can be ignored in the calculation process. Similarly, the total capacitance C of the transmission cavity 2 is nc + cj, C is the capacitance between a single SQUID structure and the metal layer 6, n is the number of josephson junctions on the SQUID chain, and cj is the capacitance of the SQUID chain itself, but in practice cj is approximately 3 orders of magnitude smaller than nc and therefore cj can be ignored in the calculation process. Based on the above, the resonant frequency of the transmission cavity 2
Figure BDA0001376621330000161
The electron cooper pairs in the josephson junction 21 can pass through the intermediate insulating layer according to the tunneling effect, and the superconducting current that appears is unobstructed. When the dc current passes, if the current is smaller than the critical current of the josephson junction 21, the josephson junction 21 exhibits the non-blocking characteristic, and the property of allowing the non-zero dc current to pass and keeping the voltage zero becomes the dc josephson effect. The critical current of the josephson junction 21 is sensitive to external magnetic fields, i.e. the magnetic field applied to the josephson junction 21 can significantly influence the magnitude of the critical current.
Therefore, the SQUID chain is adopted to form the transmission cavity in the embodiment, on one hand, the condition of stimulated emission of the electron couette pair is met, even if the total inductance of the SQUID chain is far larger than the inductance of the bias junction, on the other hand, the adjustable range of the inductance of the SQUID chain is larger, the adjusting mode is simple and direct, namely, the size of the vertical magnetic field applied to the SQUID chain can be adjusted by adjusting the size of the current in the direct current bias line 3, so that the critical current of the josephson junction 21 is adjusted, the size of the total inductance of the SQUID chain is adjusted, the resonant frequency f of the transmission cavity is adjusted, and the output frequency of the low-temperature microwave source is changed. In this embodiment, the output frequency of the low-temperature microwave source can be adjusted in the frequency range of 1GHz to 10GHz by designing appropriate parameters of the SQUID chain 20 and a specific magnetic field size.
Specifically, as shown in fig. 1, in this embodiment, the dc bias line 3 includes a long strip-shaped electrode strip, and a long side of the electrode strip is arranged in parallel with the SQUID chain, so that the transmission cavity 2 and the dc bias line 3 form a coplanar waveguide structure, and a portion of the transmission cavity 2 corresponding to the metal layer 6 on one side of the transmission cavity also forms a coplanar waveguide structure, that is, the transmission cavity 2 is a coplanar waveguide superconducting transmission line transmission cavity formed by the SQUID chain. And, the dc bias line 3 and the metal layer 6 around it constitute a coplanar waveguide structure, i.e. the structure of the dc bias line is a coplanar waveguide with its end directly to the ground plane.
When a dc current is applied to the dc bias line 3, a magnetic field distribution is formed around the dc bias line 3. The parallel arrangement of the electrode strips of the DC bias line 3 and the SQUID chain can not only ensure that the magnetic field passing through the SQUID chain is a vertical magnetic field, but also ensure the uniform distribution of the magnetic field on the whole SQUID chain 20.
Based on this, a coplanar waveguide structure is formed among the transmission cavity 2, the direct current bias line 3 and the metal layer 6, so that the direct current bias line 3 has the capability of rapidly adjusting the magnetic field while the magnetic field adjusting effect is ensured. The speed of the fastest adjusting magnetic field can reach hundreds of nanoseconds, so that the microwave source has the capability of high-speed frequency conversion output, and the output frequency of the low-temperature microwave source in the embodiment can be adjusted in a frequency band of 1GHz-10 GHz.
In addition, in order to satisfy the basic condition for realizing the quantum principle of stimulated emission, the materials of the transmission cavity 2, the bias junction 4, the voltage bias line 5, the direct current bias line 3 and the metal layer 6 in the present embodiment are all low-temperature superconducting materials. More preferably, the metal layer 6, the voltage bias line 5, and the dc bias line 3 are made of aluminum, niobium nitride, or titanium niobium nitride. In order to form a josephson junction and make the low temperature microwave source chip compatible with subsequent processes, the material of the transmission cavity 2 and the bias junction 4 is preferably aluminum. Based on this, the low-temperature microwave source chip can work below the corresponding superconducting critical temperature, not only can meet the requirements of low-temperature weak signal processing fields such as quantum bit manipulation and the like, but also can greatly reduce current loss and additional noise.
The low-temperature microwave source chip in the embodiment further comprises a metal heat sink located on the surface of the substrate 1, which is far away from the metal layer 6. In the working process, the metal heat sink not only can dissipate heat of the low-temperature microwave source chip, but also can be used as a ground plane of the low-temperature microwave source chip. That is, the dc bias line 3, the electrode plate 51 of the voltage bias line 5, and the metal layer 6 are all connected to a metal heat sink at the bottom of the substrate 1 so as to be grounded during operation.
The low-temperature microwave source chip provided by the invention generates microwave photons in a stimulated emission mode, ensures the stability of the frequency, amplitude and phase of the emitted microwave photons, and meets the requirements of a microwave source. Meanwhile, the output frequency of the low-temperature microwave source is the resonant frequency of the transmission cavity, and the resonant frequency of the transmission cavity can be adjusted by adjusting the current in the direct-current bias line, so that the output frequency range required by the control of the quantum chip can be met.
Specifically, the size of the whole low-temperature microwave source chip provided by this embodiment is small, only 500 μm × 600 μm, taking the length of the transmission cavity as 400 μm, the serial connection of 48 SQUID structures on the SQUID chain, and the inductance of a single SQUID structure as 0.8nH as an example, the upper limit output frequency of the obtained low-temperature microwave source chip is 10.8 GHz. In the actual working process, different currents are applied to the direct current bias line 3 to adjust the vertical magnetic field intensity on the SQUID chain, so that the output frequency of the low-temperature microwave source can be effectively and continuously adjusted from 10GHz to 1GHz, and the requirement of the output frequency of the low-temperature microwave source is met.
Specifically, in the actual working process, the lower limit value of the total inductance of the SQUID chain corresponds to the upper limit value of the output frequency of the microwave source. Therefore, in the low-temperature microwave source chip in the embodiment, the maximum output frequency of the low-temperature microwave source can reach 10GHz only by setting the total inductance value of the SQUID chain as the lower limit value which can be reached by the processing technology and designing the length of the SQUID chain appropriately.
It should be noted that, in the present embodiment, the length of the transmission cavity in the low-temperature microwave source chip, the number of SQUID structures on the SQUID chain, and the inductance value of a single SQUID structure include, but are not limited to, the above values, and different values may be designed according to the requirements of the output frequency of the specific low-temperature microwave source.
The embodiment of the invention also provides a manufacturing method of a low-temperature microwave source chip, which is applied to the preparation of the low-temperature microwave source chip provided by any one of the embodiments, wherein the top view of the preparation process is shown in fig. 6, fig. 7 and fig. 1, and the specific preparation process comprises the following steps:
step S1: as shown in fig. 6, a substrate 1 is provided.
The substrate 1 is a semiconductor substrate, for example, a silicon or sapphire substrate, and the substrate 1 is a sapphire substrate, for example, a sapphire substrate polished on both sides is used, and the crystal orientation of the sapphire substrate may be a [100] crystal orientation. It should be noted that, in the embodiment, the substrate material, the crystal orientation, the thickness, the scattering tangent value, and the like are selected, and an appropriate and clean substrate material can be selected on the basis of satisfying the output frequency required by the low-temperature microwave source according to the impedance matching principle, which is not limited in the embodiment.
Step S2: as shown in fig. 6, a metal layer 6 is formed on the substrate 1.
Specifically, the metal layer 6 may be formed on the surface of the substrate 1 by using an electron beam evaporation process or a magnetron sputtering coating process, and the specific process for forming the metal layer 6 and the thickness requirement of the metal layer 6 may be selected according to the difference of the metal layer material and the difference of the thickness, which is not limited in this embodiment.
The metal layer 6 is made of a superconducting material, for example, if the metal layer is made of aluminum, an aluminum film with a certain thickness may be deposited on the surface of the substrate 1 by using processes such as electron beam evaporation, and the aluminum film is used as a superconducting material, and the thickness of the aluminum film needs to exceed 50nm to achieve a good superconducting state, and therefore, the thickness of the aluminum film needs to exceed 50nm, for example, the thickness of the aluminum film is 60nm, 70nm, 80nm, 90nm, or 100nm, and the specific thickness is not limited in this embodiment.
If niobium is used as the metal layer material, a process such as magnetron sputtering may be used to deposit a niobium film with a certain thickness on the surface of the substrate 1, and since niobium is used as the superconducting material and the thickness thereof needs to exceed 20nm to achieve a good superconducting state, the thickness of the niobium film needs to exceed 20nm, for example, the thickness of the niobium film is 30nm, 40nm, 60nm, 80nm, or 100nm, and the specific thickness is not limited in this embodiment.
Step S3: as shown in fig. 7, in the same process step, all metal layers of the transmission cavity region and the bias junction region are removed, and part of the metal layers of the voltage bias line region and the dc bias line region are removed to form the voltage bias line 5 and the dc bias line 3, and an input end 61 and an output end 62 of the transmission cavity are formed at two ends of the transmission cavity region, and the output end 62 is located at a side close to the bias junction region.
In this step, a pattern in fig. 7 may be formed by using photolithography and etching processes, for example, a photoresist is spin-coated on the surface of the metal layer 6 shown in fig. 6, then a mask having patterns with structures of voltage bias lines 5 and dc bias lines 3 is used, exposure and development are performed by using an ultraviolet lithography technique, the photoresist covering the transmission cavity region and the bias junction region is removed, and a photoresist layer having patterns with structures of voltage bias lines 5 and dc bias lines 3 is obtained; then, by using a reactive ion etching technique, the photoresist layer having the structural patterns of the voltage bias line 5 and the dc bias line 3 is used as a mask to remove the metal layer material not covered by the photoresist layer, and then the photoresist layer is cleaned, so as to obtain the metal layer pattern shown in fig. 7, that is, the voltage bias line 5 including the electrode plate 51 and the inductor 52 surrounding the electrode plate 51, the dc bias line 3 including the strip-shaped electrode strip, and other structures are formed.
It should be noted that the metal layer remaining in the dc bias line region also forms the lead 30 and the lead 31, and the metal layers at the two ends of the transmissive cavity region are also etched to form the input terminal 61 and the output terminal 62. In the working process of the low-temperature microwave source, the lead 30 and the lead 31 are electrically connected with a metal heat sink at the bottom of the low-temperature microwave source chip, and an external circuit connected with the direct current bias line 3 is also connected with the metal heat sink at the bottom of the substrate 1, so that the current of the direct current bias line is adjusted. The electrode plate 51 of the voltage bias line 5 is also electrically connected to the metal heat sink at the bottom of the low temperature microwave source chip, and an external circuit for supplying a bias voltage to the electrode plate 51 is also electrically connected to the metal heat sink, thereby supplying a bias voltage to the voltage bias line 5.
The metal layer in the transmissive cavity region and the bias junction region during this etching is removed to form the transmissive cavity and the bias junction in the following steps.
Step S4: as shown in fig. 1, in the same process step, a transmission cavity including a SQUID chain is formed on the substrate surface of the transmission cavity region, and a bias junction is formed on the substrate surface of the bias junction region.
The basic structures of the transmission cavity 2 including the SQUID chain and the bias junction 4 in this embodiment are all josephson junctions, so the process steps for forming the transmission cavity 2 and the bias junction 4 are the same. Specifically, the processes of the transmission chamber 2 and the bias junction 4 will be described below with reference to the cross-sectional view and the top view of each step.
As shown in fig. 8, it is a top view of the transmission cavity region and the bias junction region after photolithography, specifically, two layers of photoresist of different materials are spin-coated on the substrate surface of the transmission cavity region and the substrate surface of the bias junction region, and a first photoresist layer 70 and a second photoresist layer 71 are sequentially formed. In the exposure process, the exposure doses required for the first photoresist layer 70 and the second photoresist layer 71 are greatly different, so that the suspension bridge structure D is successfully processed during exposure, the structure located in the dashed box of the transmission cavity region in fig. 8 is the suspension bridge structure D, and the structure located in the dashed box of the offset junction region (i.e., the region within the dashed circle in fig. 8) is the suspension bridge structure D required for forming the offset junction.
In order to facilitate the formation process of the offset junction to be performed simultaneously with the formation process of the josephson junction in the transmission cavity, blank regions are reserved on two sides of the offset junction in fig. 8, so as to facilitate the subsequent double-layer bevel evaporation process, for the offset junction structure in fig. 5a, the blank regions reserved on two sides of the offset junction are the region where the first connection line 43 is located and the region where the second connection line 44 is located, and for the offset junction structure in fig. 5b, the blank regions reserved on two sides of the offset junction are the region where the first connection line 43 is located and the region where the fourth connection line 46 is located. In the following, only the offset junction structure in fig. 5b is taken as an example, and the difference between the two structures is that the second connection line 44 in fig. 5a is formed at the same time as the offset junction, the fourth connection line 46 in fig. 5b is formed at the same time as the offset junction, and the fifth connection line 47 and the third connection line 45 are formed in the same etching process as the metal layer.
Since the fifth connection line 47 and the third connection line 45 are formed in the metal layer etching process, the double-layer photoresist layer in fig. 8 needs to cover the surfaces of the fifth connection line 47 and the third connection line 45 to prevent the subsequent process from affecting the shapes of the fifth connection line 47 and the third connection line 45.
The manner of the first photoresist layer 70 and the second photoresist layer 71 are shown in fig. 8, and are only used to illustrate that the first photoresist layer 70 is located below the second photoresist layer 71, and cannot be used to illustrate the difference in the spin coating ranges of the first photoresist layer 70 and the second photoresist layer 71.
Specifically, as shown in fig. 8-10, fig. 9 is a schematic cross-sectional view of the suspension bridge structure D in fig. 8 cut along AA ', and fig. 10 is a schematic cross-sectional view of the suspension bridge structure D in fig. 8 cut along BB'.
After the first photoresist layer 70 and the second photoresist layer 71 are spin-coated in the transmission cavity region and the bias junction region, a projection lithography technique, a laser direct writing technique, or an electron beam exposure lithography technique is adopted, so that after exposure and development, the first photoresist layer 70 in the region of the suspension bridge structure D in the transmission cavity region is removed, the second photoresist layer 71 is remained, the first photoresist layer 70 and the second photoresist layer 71 in the blank region 22 are both remained, the first photoresist layer 70 and the second photoresist layer 71 in the region of the conductive spacer structure 23 are both removed, and the region except the transmission cavity is also covered by the first photoresist layer 70 and the second photoresist layer 71, so as to prevent the subsequent process from affecting the structure formed before step S4.
As shown in fig. 14-16, fig. 14 is an enlarged view of the offset junction region of fig. 8, fig. 15 is a schematic cross-sectional view of the offset junction region of fig. 8 cut along AA ', and fig. 16 is a schematic cross-sectional view of the offset junction region of fig. 8 cut along BB'.
In the offset junction region, after exposure and development, a suspension bridge structure D is formed in the region where the offset junction is located, that is, the first photoresist layer 70 below the suspension bridge structure D is removed, the second photoresist layer 71 is remained, the first photoresist layer 70 and the second photoresist layer 71 on both sides of the offset junction a-a' direction are both remained, the first photoresist layer 70 and the second photoresist layer 71 in the regions of the first connecting line 43 and the fourth connecting line 46 are both removed, and the first photoresist layer 70 and the second photoresist layer 71 in the regions of the fifth connecting line 47 and the third connecting line 45 are both remained.
It should be noted that, for different photolithography techniques, different photoresists need to be selected, and whether a mask is used and which kind of mask is selected are determined according to characteristics of the photolithography techniques, for example, for a projection photolithography technique, a first photoresist layer and a second photoresist layer may be formed by using a reverse photoresist and a positive photoresist, respectively, and a halftone mask may be used in an exposure process. In this embodiment, only the structure formed after photolithography is limited as shown in fig. 8 to 10, and the process for forming the suspension bridge structure shown in the drawings is not particularly limited.
In this embodiment, a plurality of suspension bridge structures D are formed in the longitudinal direction of the transmissive cavity region, and are arranged in this order to form a plurality of SQUID structures. The suspension bridge structure D is formed by the second photoresist layer 71 after the first photoresist layer 70 at the bottom is removed. In fig. 9, the region between the two suspension bridge structures D covered by the first photoresist layer 70 and the second photoresist layer 71 is the blank region 22 between the two josephson junctions in fig. 2.
After the suspension bridge structure D is formed, a Josephson junction is formed on the surface of the substrate 1 in the transmission cavity area by using two different angles and a bias junction 5 is formed on the surface of the substrate 1 in the bias junction area by adopting a double-layer oblique angle evaporation technology. Specifically, taking the transmissive cavity region as an example to describe the double-layer oblique evaporation technique, the offset junction 4, the first connection line 43, and the fourth connection line 46 are also formed simultaneously in the process, and the specific forming processes are referred to each other, and are not described herein again. After the formation of the offset junction, the first photoresist 70 and the second photoresist 71 in the regions of the fifth connecting line 47 and the third connecting line 45 are removed, and then the fourth connecting line 46 is overlapped on the fifth connecting line 47, thereby forming the structure shown in fig. 5 b.
As shown in fig. 11, a first superconducting layer 211 is formed on the surface of the substrate 1 not covered with the first photoresist layer 70 using the first incident angle α 1 with the suspension bridge structure D as a mask. Then, oxygen-argon mixed gas with a certain pressure is introduced in situ to oxidize the surface of the first superconducting layer 211, so as to obtain the insulating layer 212, as shown in fig. 12. Thereafter, as shown in fig. 13, a second superconducting layer 213 is formed on the surface of the substrate 1 with the second incident angle α 2 using the suspension bridge structure D as a mask. Alternatively, the first superconducting layer 211 and the second superconducting layer 213 are metallic aluminum layers, and the insulating layer 212 is an aluminum oxide layer.
Through the above steps, that is, in the josephson junction region below the suspension bridge structure D, a sandwich structure of the first superconducting layer 211, the insulating layer 212, and the second superconducting layer 213 is formed, and the josephson junction 21 is obtained. While forming the josephson junction 21, a superconducting metal is deposited on the conductive spacer structure 23 region, as shown in fig. 13, a part of the conductive spacer structure 23 region has only the third superconducting layer metal material, a part of the conductive spacer structure 23 region is a stacked structure formed by the first superconducting layer metal material and the insulating layer material, and a part of the conductive spacer structure 23 region is a stacked structure formed by the first superconducting layer metal material, the insulating layer material and the third superconducting layer metal material. In the length direction of the transmission cavity, the conductive spacing structures 23 are located at two sides of the suspension bridge structure D, two josephson junctions 21 correspondingly formed by two suspension bridge structures D of the same SQUID structure 20 are connected in parallel through the conductive spacing structures 23, and different SQUID structures 21 are connected in series through the conductive spacing structures 23 between the two SQUID structures.
In the above process of forming the josephson junction in the transmission cavity, the josephson junction of the bias junction 4 is also formed at the same time.
Step S5: after completing fabrication of the josephson junction of transmission cavity 2 and bias junction 4, first photoresist layer 70 and second photoresist layer 71 are removed to complete processing of transmission cavity 2 and bias junction 4.
Step S6: those skilled in the art will appreciate that the low temperature microwave source chips are mass produced, and therefore, the substrate that has completed the above process steps is also subjected to dicing and cutting, so as to obtain individual microwave source chips as shown in fig. 1.
According to the preparation method of the low-temperature microwave source chip, the working frequency of the formed transmission cavity is determined by the total capacitance and the total inductance of the SQUID chain, the total inductance of the SQUID chain changes along with the change of the magnitude of the magnetic field, and the magnitude of the magnetic field changes along with the change of the magnitude of the current in the direct current bias line, so that the resonance frequency of the transmission cavity can be adjusted by adjusting the magnitude of the current of the direct current bias line, the output frequency of the low-temperature microwave source chip can be adjusted, and the requirement of the quantum chip on the frequency of the microwave source can be met.
In addition, the preparation method of the low-temperature microwave source chip disclosed in this embodiment is obtained by using a flow process such as ultraviolet lithography, electron beam exposure, magnetron sputtering coating, reactive ion etching, and the like. The low-temperature microwave source chip occupies small space, has no special process, and has a manufacturing process compatible with a manufacturing process of a quantum chip, so that the manufacturing process of the low-temperature microwave source chip can be directly integrated into the manufacturing process of the quantum chip, and the low-temperature microwave source chip can carry out in-situ control on a quantum bit. In addition, because microwave signals do not need to be transmitted from the room temperature, the whole high-frequency cable from the room temperature to the low temperature and the complicated filtering and attenuating design are omitted, the requirement of the current quantum chip control system on the number of signal lines is greatly simplified, the integration of quantum bits is more convenient, and the quantum chip scale is further enlarged.
Another embodiment of the present invention discloses a low temperature microwave source, the circuit structure diagram of which is shown in fig. 17, the low temperature microwave source includes the low temperature microwave source chip 100 and the control circuit, the control circuit is used for applying the operating voltage to the low temperature microwave source chip, so that the low temperature microwave source chip generates and emits microwave photons.
The control circuit comprises a constant current source 81 and a voltage stabilizing circuit connected with a voltage bias line of the low-temperature microwave source chip 100;
the constant current source 81 is used for providing power input for the voltage stabilizing circuit;
the voltage stabilizing circuit is used for providing stable bias voltage for the bias junction of the low-temperature microwave source.
It should be noted that, in the working process, the low-temperature microwave source chip is disposed in a low-temperature environment, and the bias voltage required by the low-temperature microwave source chip is from a constant current source at room temperature, that is, the constant current source 81 is disposed in the room-temperature environment, so that, in order to transmit the voltage from the constant current source at room temperature to the low-temperature microwave source chip, the voltage stabilizing circuit includes a room-temperature voltage stabilizing circuit 80 and a low-temperature voltage stabilizing circuit 90, and the low-temperature voltage stabilizing circuit and the low-temperature microwave source chip are disposed in the same environment.
Specifically, as shown in fig. 14, the room temperature stabilizing circuit 80 includes a first low pass filter 82 electrically connected to the constant current source 81 for eliminating voltage fluctuation caused by noise on the circuit in a room temperature environment.
The low temperature stabilizing circuit 90 includes a second low pass filter 91, a first voltage dividing resistor R1, a second voltage dividing resistor R2, and a first ground impedance element M1. Among them, the first divider resistor R1 and the second divider resistor R2 are preferably standard resistors.
The second low-pass filter 91 is electrically connected to the first low-pass filter 82, and is used for eliminating voltage fluctuation caused by noise on a circuit in a low-temperature environment;
the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 are connected in series with the voltage bias line 5 on the low-temperature microwave source chip. Specifically, a first end of the first voltage-dividing resistor R1 is electrically connected to a first end of the second voltage-dividing resistor R2, a second end of the first voltage-dividing resistor R3578 is grounded through the first grounding impedance element M1, and a second end of the second voltage-dividing resistor R2 is electrically connected to the electrode plate 51 of the voltage bias line 5 through a metal heat sink at the bottom of the low-temperature microwave source chip. An output terminal of the constant current source 81 is electrically connected to a first terminal of the first voltage dividing resistor R1 through the first low-pass filter 82 and the second low-pass filter 91.
In the working process, the constant current source 81 passes through the first voltage dividing resistor R1 and the second voltage dividing resistor R2 through the electrode plate 51 of the voltage bias line 5, the inductor 52, the transmission cavity 2 and the metal layer 6, and the obtained bias voltage is applied to two ends of the bias junction. Specifically, the metal layer 6 is grounded, that is, a first end of the bias junction 4 is directly connected to the metal layer 6 and grounded through the metal layer 6, and a stable bias voltage obtained after a voltage from the constant current source 81 passes through the first voltage dividing resistor R1, the second voltage dividing resistor R2, the electrode plate 51, and the inductor 52 is transmitted to a second end of the bias junction 4 directly connected to the transmission cavity 2 through the transmission cavity 2, so that the stable bias voltage is applied to two ends of the bias junction 4. The first voltage dividing resistor R1 and the second voltage dividing resistor R2 have voltage dividing and stabilizing functions, and the inductor 52 also has filtering and voltage stabilizing functions.
In addition, the room temperature voltage stabilizing circuit 80 further includes the following components:
a differential voltmeter 85, configured to detect a voltage across the second voltage-dividing resistor;
a third low pass filter 83 and a fourth low pass filter 84 for eliminating voltage fluctuations due to noise on the circuit.
The low temperature voltage regulator circuit 90 further includes the following components:
a fifth low-pass filter 92 and a sixth low-pass filter 93 for eliminating voltage fluctuations due to noise on the circuit;
the first capacitor C1 and the second grounding impedance element M2, the second capacitor C2 and the third grounding impedance element M3 are used for isolating thermal noise on the circuit.
A first terminal of the differential voltmeter 85 is connected to the first terminal of the second voltage-dividing resistor R2 through the third low-pass filter 83 and the fifth low-pass filter 92, and a second terminal of the differential voltmeter 85 is connected to the second terminal of the second voltage-dividing resistor R2 through the fourth low-pass filter 84 and the sixth low-pass filter 93; a first plate of the first capacitor C1 is connected to a first end of the second voltage-dividing resistor R2, and a second plate is grounded through the second grounding impedance element M2; the first plate of the second capacitor C2 is connected to the second end of the second divider resistor R2, and the second plate is grounded through the third grounding impedance element M3.
As can be seen from the circuit diagram shown in fig. 14, the voltage U applied to the voltage bias line is IR1- [ (R1/R2) +1] U ', where R1 is the resistance value of the first voltage-dividing resistor R1, R2 is the resistance value of the second voltage-dividing resistor R2, I is the current value of the constant current source, and U' is the voltage across the second voltage-dividing resistor R2 measured by the differential voltmeter 85. That is, in the case that the first divider resistor R1 and the second divider resistor R2 are standard resistors with known resistance values, an appropriate constant current source can be selected according to the requirement of the bias voltage applied to the voltage bias line, in other words, the magnitude of the bias voltage applied to the voltage bias line can be changed by selecting different constant current sources.
It should be noted that, in this embodiment, the number of the first low-pass filter to the sixth-pass filter is at least one, and the number of each stage of low-pass filters is not limited in this embodiment as long as the purpose of eliminating voltage fluctuation caused by thermal noise on the line can be achieved. In addition, in the embodiment, the wires used for connecting each circuit element in the low-temperature voltage stabilizing circuit are low-temperature direct current wires, for example, the low-temperature direct current wire in the embodiment may be a Lakeshore wire. In addition, in order to facilitate the expansion of the expansion circuit and the compatibility and isolation of different elements, the low-temperature microwave source chip and each element of the low-temperature voltage stabilizing circuit can be arranged on the same circuit board.
In the circuit structure of this embodiment, the voltage-dividing and voltage-stabilizing functions of the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 can reduce the voltage fluctuation caused by thermal noise on the circuit by two to three orders of magnitude. Furthermore, the first capacitor C1 and the second capacitor C2 are used as isolation capacitors and are matched with a grounding impedance element, so that thermal noise on a circuit is further isolated, and finally the fluctuation range of the bias voltage can be reduced to be within 100pV, thereby realizing accurate voltage division and stabilization effect.
In addition, the control circuit also comprises a current regulating circuit and a direct current source which are connected with the direct current bias line. Wherein the DC source is used for outputting current to the DC bias line; the current adjusting circuit is used for adjusting the current output from the direct current source to the direct current bias line.
The direct current source in this embodiment can be set at room temperature, the current regulating circuit can be partially set at room temperature and partially set at low temperature with reference to the setting mode of the voltage stabilizing circuit, and the current regulating circuit at low temperature is electrically connected with the metal heat sink at the bottom of the low-temperature microwave source chip through the low-temperature direct current lead, so as to be electrically connected with the direct current bias line.
In the embodiment, the output frequency of the low-temperature microwave source is controlled within 1GHz-10GHz by adjusting the current of the direct current bias line, and the adjustment rate of the output frequency can be in the order of hundreds of nanoseconds due to the structural arrangement of the low-temperature microwave source chip.
In addition, in the present embodiment, the output power of the low-temperature microwave source can be adjusted by adjusting the current value I of the constant current source 81, the resistance value R1 of the first divider resistor, and the resistance value R2 of the second divider resistor, specifically, the output power of the low-temperature microwave source in the present embodiment can be controlled within-90 dBm to-140 dBm, and due to the arrangement of the connection relationship among the transmission cavity, the bias junction, and the voltage bias line, the coupling strength between the bias junction and the transmission cavity can be enhanced to the greatest extent, and signal loss is avoided.
It should be noted that the output power of the low-temperature microwave source is determined by the input power and the energy conversion efficiency, during the operation, the energy conversion efficiency of the low-temperature microwave source in this embodiment is as high as more than 10%, and the output power is adjusted by changing the magnitude of the bias voltage input by the constant current source to the bias junction. Specifically, the low temperature microwave source needs to apply a constant voltage U to the voltage bias line during operation, according to the relationship between the voltage U and the resonant frequency of the transmission cavity, that is, mhf ═ 2 eU. Taking f as an example of 10GHz, U must satisfy U m × 20.71uV, which is an extremely small voltage value and needs to be accurate to 100 nV.
It should be noted that, because the fluctuation of the output voltage at room temperature of the most accurate constant voltage source is also about 3 μ V-5 μ V, even if a divider resistor is used, the stability of the output voltage cannot be ensured, and the stability of the constant current source at room temperature can reach the order of 10fA, a mode of matching a high-accuracy constant current source with a low-temperature standard resistor is selected as the output of the constant voltage source in this embodiment, thereby meeting the requirement of the low-temperature microwave source chip on the stability of the bias voltage. The constant-voltage source formed by the constant-current source and the low-temperature standard resistor in the embodiment has the stability reaching the precision of 10nV, the stability of the constant-voltage source is far higher than that of the most accurate room-temperature constant-voltage source, and the stability requirement of bias voltage required by a low-temperature microwave source chip can be met.
Constant voltage is applied to the voltage bias line, so that energy obtained by an electron Kuebu in the bias junction is converted into microwave photons, and further, the frequency, amplitude and phase of an output signal of the low-temperature microwave source can be highly stable. However, according to the principle of frequency conversion of microwave signals, when determining the specific value of U, the output power is not increased as the value of m is increased. Specifically, the microwave signal frequency conversion process is mainly caused by the nonlinear characteristics of the dielectric constant on the microwave signal propagation path. When only a microwave signal with a single frequency f passes through, f can be converted into mf, and the process can also occur reversibly, and the corresponding process can be understood as that m particles with energy hf are combined into a single particle with energy mhf, or a single particle with energy mhf is just decomposed into m particles with energy just equal to hf, wherein h is the Planck constant. The conversion efficiency that occurs in particular is determined by the magnitude of the dielectric constant nonlinearity in the propagation path. The larger m, the lower the probability P (n) that frequency conversion occurs, and the probability obeys a Poisson distribution. It will be understood by those skilled in the art that the magnitude of the bias voltage can be determined according to the frequency conversion principle of the microwave signal and the structure of the low-temperature microwave source chip, so as to select the appropriate constant current source 81, which will not be described in detail herein.
For example, the bias voltage U is 50 μ V, the current I' on the dc bias line is 2nA, the energy conversion efficiency is 10%, and the output power of the low temperature microwave source in this embodiment can reach-110 dBm. Although this value is much smaller than the output power range of the present room temperature microwave source, in practice, the microwave signal required for the quantum chip manipulation is extremely weak, and the power of the microwave signal actually arriving on the quantum chip is in between considering the signal strength required for highlighting the quantum property, and the filtering and attenuation on the line. Therefore, the actual output power of the invention basically covers the range of the requirements, and the low-temperature microwave source in the embodiment can meet the requirements of quantum chip control and quantum computation.
The low-temperature microwave source comprises a low-temperature microwave source chip and a control circuit, wherein the control circuit is used for applying working voltage to the low-temperature microwave source chip to enable the low-temperature microwave source chip to generate and emit microwave photons, a transmission cavity, a bias junction, a voltage bias line, a direct current bias line and the like on the low-temperature microwave source chip are all manufactured through a semiconductor process, and the manufacturing process of the control circuit is compatible with that of a quantum chip.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (33)

1. A low-temperature microwave source chip is characterized by comprising a substrate, a transmission cavity, a bias junction, a voltage bias line and a direct current bias line, wherein the transmission cavity, the bias junction, the voltage bias line and the direct current bias line are positioned on the surface of the substrate;
wherein the transmission cavity is used for emitting microwave photons, the transmission cavity comprises a SQUID chain, the SQUID chain comprises a plurality of SQUID structures, and the SQUID structures are connected in series;
the bias junction is electrically connected with the transmission cavity and is used for generating microwave photons;
the voltage bias line is used for applying bias voltage to the bias junction to convert the electron Cooper pairs in the bias junction into microwave photons in a stimulated emission mode;
the direct current bias line is used for applying a magnetic field to the transmission cavity;
wherein the resonant frequency of the transmission cavity is determined by the total capacitance and total inductance of the SQUID chain; the total inductance of the SQUID chain changes with the change of the magnitude of the magnetic field, and the magnitude of the magnetic field changes with the change of the magnitude of the current in the direct current bias line.
2. The low temperature microwave source chip according to claim 1, wherein the total inductance of the transmission cavity is larger than the total inductance of the bias junction, so that the electron cooper pair can tunnel through the bias junction by generating or absorbing a photon under constant voltage bias.
3. The low-temperature microwave source chip according to claim 2, wherein the emission rate of the microwave photons emitted from the transmission cavity is smaller than the tunneling rate of the electron cooper pair tunneling through the bias junction, so that the microwave photons are absorbed again by the electron cooper pair before being emitted to promote the next tunneling of the electron cooper pair to continuously generate microwave photons.
4. The cryogenic microwave source chip of claim 3, wherein the SQUID structure is a ring structure of two parallel Josephson junctions;
the Josephson junction includes a first superconducting layer, an insulating layer, and a second superconducting layer sequentially on the surface of the substrate.
5. The cryogenic microwave source chip of claim 4 wherein the DC bias line comprises an elongated electrode strip with a long side disposed parallel to the SQUID chain.
6. The low-temperature microwave source chip according to claim 5, wherein the substrate surface further comprises a metal layer besides the transmission cavity, the bias junction, the voltage bias line and the direct current bias line, the metal layer surrounds the transmission cavity, the bias junction, the voltage bias line and the direct current bias line, and the metal layer, the voltage bias line and the direct current bias line are formed in the same photolithography process;
the transmission cavity, the metal layer and the direct current bias line which are respectively positioned at the two sides of the transmission cavity form a coplanar waveguide structure;
the direct current bias line and the metal layer around the direct current bias line form a coplanar waveguide structure.
7. The cryogenic microwave source chip of claim 6 wherein the bias junction is a Josephson junction.
8. The low temperature microwave source chip of claim 7 wherein one end of the offset junction is directly connected to the output end of the transmission cavity and the other end is directly connected to the metal layer.
9. The cryogenic microwave source chip of claim 8 wherein the formation direction of the biased junction coincides with the formation direction of the josephson junction in the SQUID chain transmission chamber such that the biased junction and the SQUID chain are formed in the same process step.
10. The low-temperature microwave source chip of claim 9, wherein the bias junction and the output end of the transmission cavity are connected in a manner that: a long strip-shaped conductive material is extended out of the long edge of the transmission cavity and is close to the output end of the transmission cavity to serve as a first connecting line, and the first connecting line is in direct contact with the first edge of the bias junction;
the bias junction and the metal layer are connected in the following mode: and a strip-shaped conductive material is extended from the second edge of the bias junction to serve as a second connecting line, a strip-shaped conductive material is extended from the metal layer in the direction towards the bias junction to serve as a third connecting line, the second connecting line is directly connected with the third connecting line, the included angle between the second connecting line and the third connecting line is a right angle, and the first edge and the second edge of the bias junction are two opposite edges along the length direction of the transmission cavity.
11. The low temperature microwave source chip according to claim 10, wherein the first connection line, the second connection line and the bias junction are formed in the same process step; the third connecting line and the metal layer are formed in the same process step.
12. The low-temperature microwave source chip of claim 9, wherein the bias junction and the output end of the transmission cavity are connected in a manner that: a long strip-shaped conductive material is extended out of the long edge of the transmission cavity and is close to the output end of the transmission cavity to serve as a first connecting line, and the first connecting line is in direct contact with the first edge of the bias junction;
the bias junction and the metal layer are connected in the following mode: and a strip-shaped conductive material is extended from the second edge of the bias junction to serve as a fourth connecting line, a strip-shaped conductive material is extended from the metal layer towards the bias junction to serve as a third connecting line, a conductive material extended from the tail part of the third connecting line towards the fourth connecting line serves as a fifth connecting line, the fourth connecting line is in lap joint with the fifth connecting line, the included angle between the third connecting line and the fifth connecting line is a right angle, and the first edge and the second edge of the bias junction are two opposite edges along the length direction of the transmission cavity.
13. The low temperature microwave source chip of claim 12, wherein the first connection line, the fourth connection line and the bias junction are formed in a same process step, and the third connection line, the fifth connection line and the metal layer are formed in a same process step.
14. The low-temperature microwave source chip of claim 8, wherein the voltage bias line comprises an electrode plate and an inductor surrounding the electrode plate, a first end of the inductor is directly connected with the electrode plate, and a second end of the inductor is connected with the transmission cavity.
15. The cryogenic microwave source chip of claim 14 wherein the transmission cavity is a half-wavelength resonant cavity, the center of the transmission cavity is a voltage node, and the second end of the inductor is directly connected to the center of the transmission cavity.
16. The cryogenic microwave source chip of claim 14 wherein the relationship between the first coupling capacitance C1 between the output of the transmission cavity and the metal layer and the second coupling capacitance C2 between the input of the transmission cavity and the metal layer is C1: c2 is more than or equal to 10:1, and the emitting speed omega of the microwave photons from the output end of the transmission cavity is in direct proportionAt C12。
17. The low-temperature microwave source chip of claim 16, wherein the resonant frequency f of the transmission cavity and the constant voltage U applied to the voltage bias line satisfy the relation mhf ═ 2eU, where m is a positive integer, h is a planck constant, and e is an electric quantity of one electron; wherein the resonant frequency of the transmissive cavity is equal to the output frequency of the low temperature microwave source.
18. The low temperature microwave source chip of claim 17 wherein the total inductance L-L of the transmission cavity0+nLj-2, the total capacitance of said transmission cavity, C ═ nc + cj, resonance frequency
Figure FDA0002585356120000031
Wherein L isjInductance of a single Josephson junction, L0The inductance between the SQUID chain and the metal layer, c is the capacitance between a single SQUID structure and the metal layer, cj is the capacitance of the SQUID chain, and n is the number of the SQUID structures on the SQUID chain.
19. The low temperature microwave source chip of claim 6 wherein the material of the transmission cavity, the bias junction, the voltage bias line, the DC bias line and the metal layer are all low temperature superconducting materials.
20. The low-temperature microwave source chip of claim 19, wherein the metal layer, the voltage bias line, and the dc bias line are made of aluminum, niobium nitride, or titanium niobium nitride.
21. The cryogenic microwave source chip of claim 20 wherein the material of the transmissive cavity and the offset junction is aluminum.
22. The low-temperature microwave source chip of claim 6, further comprising a metal heat sink located on a surface of the substrate facing away from the metal layer to dissipate heat of the low-temperature microwave source chip.
23. A low-temperature microwave source, which comprises a control circuit and the low-temperature microwave source chip of any one of claims 1 to 19, wherein the control circuit is used for applying an operating voltage to the low-temperature microwave source chip to enable the low-temperature microwave source chip to generate and emit microwave photons;
the control circuit comprises a constant current source and a voltage stabilizing circuit connected with the voltage bias line;
the constant current source is used for providing power supply input for the voltage stabilizing circuit;
the voltage stabilizing circuit is used for providing bias voltage for a bias junction of the low-temperature microwave source;
the constant current source is arranged in a room temperature environment, the low-temperature microwave source chip is arranged in a low-temperature environment, the voltage stabilizing circuit comprises a room temperature voltage stabilizing circuit and a low-temperature voltage stabilizing circuit, and the low-temperature voltage stabilizing circuit and the low-temperature microwave source chip are arranged in the same environment.
24. The low temperature microwave source of claim 23 wherein the control circuit further includes a current regulation circuit and a dc source connected to the dc bias line;
the direct current source is used for outputting current to the direct current bias line;
the current adjusting circuit is used for adjusting the current output from the direct current source to the direct current bias line.
25. The source of claim 23 wherein the low temperature microwave source has an output frequency within 1GHz-10GHz, a rate of output frequency regulation on the order of hundreds of nanoseconds, an output power within-90 dBm to-140 dBm, and an energy conversion efficiency of greater than 10%.
26. A low-temperature microwave source, which comprises a control circuit and the low-temperature microwave source chip of any one of claims 6, 8, 10, 11, 12, 13, 16, 18 and 19, wherein the control circuit is used for applying an operating voltage to the low-temperature microwave source chip to enable the low-temperature microwave source chip to generate and emit microwave photons;
the control circuit comprises a constant current source and a voltage stabilizing circuit connected with the voltage bias line;
the constant current source is used for providing power supply input for the voltage stabilizing circuit;
the voltage stabilizing circuit is used for providing bias voltage for a bias junction of the low-temperature microwave source;
the constant current source is arranged in a room temperature environment, the low-temperature microwave source chip is arranged in a low-temperature environment, the voltage stabilizing circuit comprises a room temperature voltage stabilizing circuit and a low-temperature voltage stabilizing circuit, and the low-temperature voltage stabilizing circuit and the low-temperature microwave source chip are arranged in the same environment;
the room temperature voltage stabilizing circuit comprises a first low-pass filter electrically connected with the constant current source and used for eliminating voltage fluctuation caused by noise on a circuit;
the low temperature voltage stabilizing circuit includes:
a second low-pass filter electrically connected to the first low-pass filter for eliminating voltage fluctuations due to noise on the circuit;
the first voltage dividing resistor and the second voltage dividing resistor are connected with the voltage bias line in series, the first end of the first voltage dividing resistor is electrically connected with the first end of the second voltage dividing resistor, the second end of the first voltage dividing resistor is grounded through the first grounding impedance element, the second end of the second voltage dividing resistor is electrically connected with the electrode plate of the voltage bias line, and the metal layer is grounded in the working process;
the output end of the constant current source is electrically connected with the first end of the first divider resistor through a first low-pass filter and a second low-pass filter, and the bias voltage provided by the constant current source is applied to two ends of a bias junction through the inductance of the voltage bias line, the transmission cavity and the metal layer in the working process.
27. The low temperature microwave source of claim 26 wherein the room temperature voltage regulator circuit further comprises:
the differential voltmeter is used for detecting the voltage at two ends of the second voltage-dividing resistor;
a third low-pass filter and a fourth low-pass filter for eliminating voltage fluctuation due to noise on the circuit;
the low temperature voltage stabilizing circuit further comprises:
a fifth low-pass filter and a sixth low-pass filter for eliminating voltage fluctuation due to noise on the circuit;
a first capacitor and a second grounding impedance element, a second capacitor and a third grounding impedance element for isolating thermal noise on the circuit;
the first end of the differential voltmeter is connected with the first end of the second divider resistor through the third low-pass filter and the fifth low-pass filter, and the second end of the differential voltmeter is connected with the second end of the second divider resistor through the fourth low-pass filter and the sixth low-pass filter; a first polar plate of the first capacitor is connected with a first end of the second divider resistor, and a second polar plate is grounded through the second grounding impedance element; a first pole plate of the second capacitor is connected with a second end of the second divider resistor, and the second pole plate is grounded through the third grounding impedance element;
the voltage applied to the voltage bias line is IR1- [ (R1/R2) +1] U ', where R1 is the resistance value of the first voltage-dividing resistor, R2 is the resistance value of the second voltage-dividing resistor, I is the current value of the constant current source, and U' is the voltage across the second voltage-dividing resistor.
28. The low temperature microwave source of claim 27 wherein the number of the first low pass filter to the sixth pass filter is at least one, the wires of the low temperature voltage regulator circuit used for connecting each circuit component are low temperature direct current wires, and the low temperature microwave source chip and the low temperature voltage regulator circuit are disposed on the same circuit board.
29. The low temperature microwave source of claim 26 wherein the control circuit further includes a current regulation circuit and a dc source connected to the dc bias line;
the direct current source is used for outputting current to the direct current bias line;
the current adjusting circuit is used for adjusting the current output from the direct current source to the direct current bias line.
30. The source of claim 26 wherein the low temperature microwave source has an output frequency within 1GHz-10GHz, a rate of output frequency regulation on the order of hundreds of nanoseconds, an output power within-90 dBm to-140 dBm, and an energy conversion efficiency of greater than 10%.
31. A method for manufacturing a low-temperature microwave source chip, which is used for manufacturing the low-temperature microwave source chip of any one of claims 1 to 20, and comprises the following steps:
providing a substrate;
forming a metal layer on the substrate;
in the same process step, removing all metal layers in a transmission cavity area and a bias junction area, and removing partial metal layers in a voltage bias line area and a direct current bias line area to form a voltage bias line and a direct current bias line, and forming an input end and an output end at two ends of the transmission cavity area, wherein the output end is positioned at one side close to the bias junction area;
in the same process step, a transmission cavity comprising a SQUID chain is formed on the surface of the substrate of the transmission cavity region, and a bias junction is formed on the surface of the substrate of the bias junction region.
32. The method of claim 31, wherein the voltage bias line comprises an electrode plate and an inductor surrounding the electrode plate, the dc bias line comprises an elongated electrode strip, and the removing all metal layers of the transmissive cavity region and the bias junction region and removing portions of the metal layers of the voltage bias line region and the dc bias line region to form the voltage bias line and the dc bias line comprises:
forming a photoresist layer on the surface of the metal layer, wherein the photoresist layer covers the electrode plate, the inductor and the long-strip-shaped electrode strip region, and exposes the transmission cavity region, the bias junction region and the metal layer in a certain region around the inductor and the electrode strip;
etching the metal layer material which is not covered by the photoresist layer by taking the photoresist layer as a mask;
and removing the photoresist layer, and reserving the electrode plate, the inductor and the long-strip-shaped electrode strip.
33. The method of claim 32, wherein forming a transmission cavity comprising a SQUID chain at a substrate surface of the transmission cavity region and forming a bias junction at a substrate surface of the bias junction region comprises:
sequentially forming a first photoresist layer and a second photoresist layer on the substrate surface of the transmission cavity region and the substrate surface of the offset junction region;
exposing and developing the first photoresist layer and the second photoresist layer to form a plurality of suspension bridge structures which are sequentially arranged along the length direction of the transmission cavity area, wherein the suspension bridge structures are formed by the second photoresist layer with the first photoresist layer at the bottom removed;
forming a first superconducting layer on the surface of the substrate by using the suspension bridge structure as a mask and adopting a first incidence angle;
oxidizing a surface of the first superconducting layer to form an insulating layer;
forming a second superconducting layer on the surface of the insulating layer by using the suspension bridge structure as a mask and adopting a second incidence angle;
wherein a stack of the first superconducting layer, the insulating layer, and the second superconducting layer formed in a region under the suspension bridge structure constitutes a josephson junction, and the josephson junction formed in the bias junction region is the bias junction; in the length direction of the transmission cavity, superconducting layer materials between two adjacent suspension bridge structures form a conductive interval structure, in the width direction of the transmission cavity, two Josephson junctions respectively positioned at two sides of the suspension bridge structures are connected in parallel through the conductive interval structure to form the SQUID structure, and in the length direction of the transmission cavity, a plurality of SQUID structures are connected in series through the conductive interval structure to form the SQUID chain.
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