CN107390770B - Current mirroring circuit, display driver circuit, display device - Google Patents
Current mirroring circuit, display driver circuit, display device Download PDFInfo
- Publication number
- CN107390770B CN107390770B CN201710735702.8A CN201710735702A CN107390770B CN 107390770 B CN107390770 B CN 107390770B CN 201710735702 A CN201710735702 A CN 201710735702A CN 107390770 B CN107390770 B CN 107390770B
- Authority
- CN
- China
- Prior art keywords
- transistor
- control terminal
- connect
- operational amplifier
- current mirroring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Amplifiers (AREA)
Abstract
Present disclose provides a kind of current mirroring circuit, display driver circuit and display device, which includes: the first transistor, second transistor, third transistor, the 4th transistor, operational amplifier, the 5th transistor, the 6th transistor, the 7th transistor and the 8th transistor.The disclosure ensures that the ratio of the electric current of input terminal and the electric current of output end is equal to the ratio between breadth length ratio and breadth length ratio of third transistor of the first transistor, reduces the mirroring error of electric current, improves the accuracy of current mirror.
Description
Technical field
This disclosure relates to technical field of integrated circuits more particularly to a kind of current mirroring circuit, display driver circuit, display dress
It sets.
Background technique
Current mirroring circuit is most basic circuit in Analogous Integrated Electronic Circuits, can to a given driving ource electric current according to
Certain proportion carries out mirror image, keeps output electric current completely identical as driving current.Current mirroring circuit generally has high-resolution, height defeated
Impedance out has high tracking velocity when input current changes, and therefore, current mirroring circuit has been widely used in simulation
In the design of digital circuit.
As shown in Figure 1, cascode (cascade) current mirroring circuit includes 4 metal-oxide-semiconductors.It all works in 4 metal-oxide-semiconductors
When saturation state, according to saturation current calculation formula:
Wherein, u is mobility,For breadth length ratio, VgsFor gate source voltage,
VthFor threshold voltage, VdsFor drain-source voltage, γ is saturation channel-modulation parameter.
As it can be seen that in the V for guaranteeing above-mentioned metal-oxide-semiconductorgsIt is all the same and do not consider VdsUnder the premise of, input current and output electricity
The ratio of stream is equal to the ratio of the breadth length ratio of the breadth length ratio of the metal-oxide-semiconductor of input terminal and the metal-oxide-semiconductor of output end.
As shown from the above formula, it can be adjusted by adjusting the ratio of the breadth length ratio of input terminal and the metal-oxide-semiconductor of output end
The ratio of input current and output electric current, and then realize the mirror image in proportion of input current.
Obviously, in the actual course of work of circuit, it is difficult to ensure that the V of each metal-oxide-semiconductordsIt is essentially equal, therefore the mirror of electric current
As error is larger.
It should be noted that information is only used for reinforcing the reason to the background of the disclosure disclosed in above-mentioned background technology part
Solution, therefore may include the information not constituted to the prior art known to persons of ordinary skill in the art.
Summary of the invention
The disclosure is designed to provide a kind of current mirroring circuit, display driver circuit, display device, and then at least one
Determine to overcome the problems, such as in degree caused by the limitation and defect due to the relevant technologies one or more.
According to one aspect of the disclosure, a kind of current mirroring circuit is provided, comprising:
The first transistor, control terminal and second end are connect with input terminal, and first end receives the first power supply signal；
Second transistor, control terminal are connect with the control terminal of the first transistor, and first end receives first electricity
Source signal；
Third transistor, control terminal are connect with the control terminal of the first transistor, and first end receives first electricity
Source signal, second end connect output end；
4th transistor, control terminal are connect with the second end of the third transistor, and first end receives first electricity
Source signal；
Operational amplifier, first end are connect with the second end of the second transistor, second end and the 4th crystal
The second end of pipe connects；
5th transistor, control terminal are connect with the third end of the operational amplifier, first end and the operation amplifier
The first end of device connects；
6th transistor, control terminal are connect with the third end of the operational amplifier, first end and the operation amplifier
The second end of device connects；
7th transistor, control terminal and second end are connect with the second end of the 5th transistor, and first end receives
Second source signal；
8th transistor, control terminal are connect with the control terminal of the 7th transistor, and first end receives second electricity
Source signal, second end are connect with the second end of the 6th transistor.
In a kind of exemplary embodiment of the disclosure, the current mirroring circuit further include:
9th transistor, first end are connect with the second end of the third transistor, and second end and the output end connect
It connects；
Tenth transistor, control terminal are connect with the second end of the operational amplifier, and first end receives first electricity
Source signal；
11st transistor, control terminal are connect with the second end of the tenth transistor, and first end receives described first
Power supply signal, second end are connect with the control terminal of the 9th transistor；
Tenth two-transistor, control terminal and second end are connect with the second end of the tenth transistor, the first termination
Receive the second source signal；
The second end of 13rd transistor, control terminal and second end with the 11st transistor, first end receive
The second source signal.
In a kind of exemplary embodiment of the disclosure, the operational amplifier to the first end of the 5th transistor and
The voltage of the first end of 6th transistor carries out clamper.
In a kind of exemplary embodiment of the disclosure, the 4th transistor, the 9th transistor, the tenth crystalline substance
Body pipe and the 11st transistor constitute negative-feedback circuit.
In a kind of exemplary embodiment of the disclosure, the first transistor to the 6th transistor is p-type crystalline substance
Body pipe, the 7th transistor to the 8th transistor is N-type transistor.
In a kind of exemplary embodiment of the disclosure, the first transistor to the 6th transistor is p-type crystalline substance
Body pipe, the 9th transistor to the 11st transistor is P-type transistor, the 7th transistor to the 8th crystalline substance
Body pipe is N-type transistor, and the tenth two-transistor to the 13rd transistor is N-type transistor.
In a kind of exemplary embodiment of the disclosure, the first transistor, the second transistor and described
The size of three transistors is identical, and the 7th transistor is identical as the size of the 8th transistor.
In a kind of exemplary embodiment of the disclosure, the transistor is field effect transistor or bipolar transistor.
According to one aspect of the disclosure, a kind of display driver circuit is provided, including the electricity as described in above-mentioned any one
Current mirror circuit.
According to one aspect of the disclosure, a kind of display device is provided, comprising:
Display panel, including array substrate and for the multiple data lines to array substrate transmission data-signal；
Data driver, for providing data-signal to the multiple data lines；
Display driver circuit described in multiple above-mentioned any one, is electrically connected the data driver.
A kind of current mirroring circuit, the display driver circuit, display device that a kind of exemplary embodiment of the disclosure provides, the electricity
Current mirror circuit includes the first to the 8th transistor and operational amplifier.Pass through the 7th transistor, the 8th transistor, the 4th crystal
Pipe and operational amplifier so that the voltage between the control terminal and first end of the first transistor, the second end of the first transistor and
The second end of voltage, third transistor between the control terminal and first end of voltage, third transistor between first end and
Voltage between one end is all identical, and then ensures that the ratio of the electric current of input terminal and the electric current of output end is equal to first crystal
The ratio between breadth length ratio and the breadth length ratio of third transistor of pipe, and eliminate the electricity between the control terminal of the first transistor and first end
Pressure, the voltage between the second end and first end of the first transistor, the voltage between the control terminal and first end of third transistor
And the influence of the voltage between the second end and first end of third transistor, the mirroring error of electric current is reduced, electricity is improved
The accuracy of traffic mirroring.
Detailed description of the invention
It is described in detail its exemplary embodiment by referring to accompanying drawing, the above and other feature and advantage of the disclosure will become
It obtains more obvious.It should be evident that the accompanying drawings in the following description is only some embodiments of the present disclosure, it is common for this field
For technical staff, without creative efforts, it is also possible to obtain other drawings based on these drawings.Attached
In figure:
Fig. 1 is the schematic diagram of one cascode of the disclosure (cascade) current mirroring circuit；
Fig. 2 is the schematic diagram one of the current mirroring circuit provided in one exemplary embodiment of the disclosure；
Fig. 3 is the schematic diagram two of the current mirroring circuit provided in one exemplary embodiment of the disclosure；
Fig. 4 is the comparison diagram of the output electric current of the circuit in the Fig. 1 and Fig. 2 provided in one exemplary embodiment of the disclosure；
Fig. 5 is the output electricity of the circuit in output loading variation in Fig. 1 provided in one exemplary embodiment of the disclosure
The comparison diagram of stream and the output electric current of the circuit in Fig. 3；
Description of symbols:
MP1, the first transistor；
MP2, second transistor；
MP3, third transistor；
MP4, the 4th transistor；
MP5, the 5th transistor；
MP6, the 6th transistor；
MN1, the 7th transistor；
MN2, the 8th transistor；
MP7, the 9th transistor；
MP8, the tenth transistor；
MP9, the 11st transistor；
MN3, the tenth two-transistor；
MN4, the 13rd transistor；
A, operational amplifier；
Vdd, the first power supply signal；
Vss, second source signal；
Iin, input terminal；
Iout, output end.
Specific embodiment
Example embodiment is described more fully with reference to the drawings.However, example embodiment can be real in a variety of forms
It applies, and is not understood as limited to embodiment set forth herein；On the contrary, thesing embodiments are provided so that the disclosure will be comprehensively and complete
It is whole, and the design of example embodiment is comprehensively communicated to those skilled in the art.Described feature, structure or characteristic can
Be incorporated in one or more embodiments in any suitable manner.In the following description, provide many details from
And it provides and embodiment of the disclosure is fully understood.It will be appreciated, however, by one skilled in the art that can be of the disclosure
Technical solution, or can be using other methods, constituent element, material, dress without one or more in the specific detail
It sets, step etc..In other cases, known solution is not shown in detail or describes to avoid fuzzy all aspects of this disclosure.
In addition, attached drawing is only the schematic illustrations of the disclosure, not necessarily it is drawn to scale.Identical attached drawing in figure
Label identifies the same or similar part, thus will omit repetition thereof.
A kind of current mirroring circuit is provided in this example embodiment, referring to shown in Fig. 2, which be can wrap
It includes: the first transistor MP1, second transistor MP2, third transistor MP3, the 4th transistor MP4, operational amplifier A, the 5th crystalline substance
Body pipe MP5, the 6th transistor MP6, the 7th transistor MN1 and the 8th transistor MN2, in which:
The control terminal and second end of the first transistor MP1 is connect with input terminal Iin, the first end of the first transistor MP1
Receive the first power supply signal Vdd；
The control terminal of second transistor MP2 is connect with the control terminal of the first transistor MP1, second transistor MP2's
First end receives the first power supply signal Vdd；
The control terminal of third transistor MP3 is connect with the control terminal of the first transistor MP1, third transistor MP3's
First end receives the first power supply signal Vdd, and the second end of third transistor MP3 connects output end Iout；
The control terminal of 4th transistor MP4 is connect with the second end of the third transistor MP3, the 4th transistor MP4's
First end receives the first power supply signal Vdd；
The first end of operational amplifier A is connect with the second end of the second transistor MP2, and the second of operational amplifier A
End is connect with the second end of the 4th transistor MP4；
The control terminal of 5th transistor MP5 is connect with the third end of the operational amplifier A, and the of the 5th transistor MP5
One end is connect with the first end of the operational amplifier A；
The control terminal of 6th transistor MP6 is connect with the third end of the operational amplifier A, and the of the 6th transistor MP6
One end is connect with the second end of the operational amplifier A；
The control terminal and second end of 7th transistor MN1 is connect with the second end of the 5th transistor MP5, and the 7th is brilliant
The first end of body pipe MN1 receives second source signal Vss；
The control terminal of 8th transistor MN2 is connect with the control terminal of the 7th transistor MN1, the 8th transistor MN2's
First end receives the second source signal Vss, the second end of the 8th transistor MN2 and the second of the 6th transistor MP6
End connection.
In the present example embodiment, the operational amplifier A for example can be universal operational amplifier, high resistance type fortune
Calculate amplifier, Low Drift Temperature type operational amplifier, high-speed operational amplifier, low-coumption operational amplifier etc., this exemplary implementation
Example is not particularly limited this.
The operational amplifier A has first end, second end and third end.Specifically, the first end of operational amplifier A can
Think inverting input terminal, the second end of operational amplifier A can be non-inverting input terminal, and the third end of operational amplifier A can be
Output end.
Alternatively, the first end of operational amplifier A can be non-inverting input terminal, the second end of operational amplifier A can be anti-
To input terminal, the third end of operational amplifier A can be output end.
The transistor can be field effect transistor, can also be bipolar transistor.In addition, the transistor can
It can also be depletion mode transistor to be enhancement transistor, the present exemplary embodiment is not particularly limited this.
Described first to the 8th transistor all has control terminal, first end and second end.Specifically, the control of each transistor
End processed can be grid, and the first end of each transistor can be source electrode, and second end can be drain electrode.
On this basis, the first transistor MP1 to the 6th transistor MP6 can be P-type transistor, the 7th transistor
MN1 to the 8th transistor MN2 can be N-type transistor.In the case, the first power supply signal Vdd can be high electricity
Flat, the second source signal Vss can be low level.
Alternatively, the first transistor MP1 to the 6th transistor MP6 can be N-type transistor, the 7th transistor MN1 to
Eight transistor MN2 can be P-type transistor.In the case, the first power supply signal Vdd can be low level, described
Second source signal Vss can be high level.
It should be noted that P-type transistor is connected when grid is low level, end when grid is high level, N-type is brilliant
Body pipe ends when grid is low level, is connected when grid is high level.
The 7th transistor MN1 is identical as the size of the 8th transistor MN2, pass through second transistor MP2,
The electric current of 5th transistor MP5 and the 7th transistor MN1 and flow through the 4th transistor MP4, the 6th transistor MP6 and the 8th crystal
The electric current of pipe MN2 is equal.
Due to the first end and the two equal virtual earth of end voltage of operational amplifier A, operational amplifier A can be to described
The voltage of the first end of 5th transistor MP5 and the first end of the 6th transistor MP6 carries out clamper, to guarantee the 5th crystal
The voltage of the first end of the voltage of the first end of pipe MP5 and the 6th transistor MP6 is identical.
On this basis, since the second end of second transistor MP2 is connect with the first end of the 5th transistor MP5, the 4th
The second end of transistor MP4 is connected with the first end of the 6th transistor MP6, therefore, the second end of second transistor MP2 and the 4th
The voltage of the second end of transistor MP4 is identical.Again due to second transistor MP2 first end and the 4th transistor MP4 first
End receives the first power supply signal Vdd, and therefore, the voltage and the 4th between the second end and first end of second transistor MP2 are brilliant
Voltage between the second end and first end of body pipe MP4 is equal.
In conclusion since the electric current for flowing through second transistor MP2 is identical with the electric current for flowing through the 4th transistor MP4, and
Voltage between the second end and first end of second transistor MP2 and between the second end and first end of the 4th transistor MP4
Voltage is equal, therefore, the control terminal of voltage and the 4th transistor MP4 between the control terminal and first end of second transistor MP2
Voltage between first end is equal.Again since the control terminal of the 4th transistor MP4 is connected to the second of third transistor MP3
End, the first end of the first end connection third transistor MP3 of the 4th transistor MP4, therefore, the control terminal of second transistor MP2
Voltage between first end is equal with the voltage between the second end of third transistor MP3 and first end.
As shown in Figure 2, the first transistor MP1, second transistor MP2, third transistor MP3 constitute current mirror, therefore, the
Voltage between the control terminal and first end of one transistor MP1, the electricity between the second end and first end of the first transistor MP1
It presses, between the control terminal and first end of the voltage between the control terminal and first end of second transistor MP2, third transistor MP3
Voltage it is all equal.
It can obtain in summary, the voltage, the first transistor MP1 between the control terminal and first end of the first transistor MP1
Voltage between second end and first end, the voltage between the control terminal and first end of third transistor MP3, third transistor
Voltage between the second end and first end of MP3 is equal.
On this basis, according to the saturation current calculation formula of transistor:
Wherein, u is mobility,For breadth length ratio, VgsFor gate source voltage, VthFor threshold voltage, VdsFor drain-source voltage, γ
To be saturated channel-modulation parameter.
Since above-mentioned current mirroring circuit ensures voltage between the control terminal and first end of the first transistor MP1, first
Voltage between the control list and first end of voltage, third transistor MP3 between the second end and first end of transistor MP1,
Voltage between the second end and first end of third transistor MP3 is all equal (that is, Vgs(MP1)=Vds(MP1)=Vgs(MP3)=
Vds(MP3)), therefore, according to the saturation current calculation formula of above-mentioned transistor it is found that above-mentioned current mirroring circuit ensures input terminal
The width of the ratio of the electric current of the electric current and output end Iout of the Iin breadth length ratio equal to the first transistor MP1 and third transistor MP3
It is long than the ratio between, and eliminate the voltage between the control terminal and first end of the first transistor MP1, the first transistor MP1 second
Voltage and third transistor MP3 between the control list and first end of voltage, third transistor MP3 between end and first end
Second end and first end between voltage influence, reduce the mirroring error of electric current, improve the accuracy of current mirror.
On this basis, the first transistor MP1, the second transistor MP2 and the third transistor MP3
Size can be identical.Can be obtained by the saturation current calculation formula of transistor, in the first transistor MP1, second transistor MP2 and
When the size of third transistor MP3 is identical, the ratio between breadth length ratio and the breadth length ratio of third transistor MP3 of the first transistor MP1 are
1, so that the electric current of input terminal Iin is equal with the electric current of output end Iout.
It is illustrated below by current mirror precision of the experimental data to the current mirroring circuit in Fig. 2.Fig. 4 is shown
When the input current of the input terminal of circuit in Fig. 1 and Fig. 2 is 20uA, the comparison of the output electric current of the circuit in Fig. 1 and Fig. 2
Figure, wherein 1 is the schematic diagram of the output electric current of the circuit in Fig. 2, and 2 be the schematic diagram of the output electric current of the circuit in Fig. 1.By
Fig. 4 it is found that when the input current of the input terminal of circuit in fig. 1 and 2 is 20uA, the output end of the circuit in Fig. 1
Output electric current is 19.955uA, and the output electric current of the output end of the circuit in Fig. 2 is 19.999uA, relative to the circuit in Fig. 1,
The current mirror precision of mirror image circuit in Fig. 2 is significantly improved.
In addition, referring to shown in Fig. 3, the current mirroring circuit can also include:
The first end of 9th transistor MP7 is connect with the second end of the third transistor MP3, second end and the output
Hold Iout connection；
The control terminal of tenth transistor MP8 is connect with the second end of the operational amplifier A, and first end receives described first
Power supply signal Vdd；
The control terminal of 11st transistor MP9 is connect with the second end of the tenth transistor MP8, described in first end reception
First power supply signal Vdd, second end are connect with the control terminal of the 9th transistor MP7；
The control terminal and second end of tenth two-transistor MN3 is connect with the second end of the tenth transistor MP8, and first
End receives the second source signal Vss；
Second end of the control terminal and second end of 13rd transistor MN4 with the 11st transistor MP9, first end
Receive the second source signal Vss.
In the present example embodiment, the transistor can be field effect transistor, can also be bipolar transistor
Pipe.In addition, the transistor can be enhancement transistor, it can also be depletion mode transistor, the present exemplary embodiment
This is not particularly limited.
9th to the 13rd transistor all has control terminal, first end and second end.Specifically, each transistor
Control terminal can be grid, and the first end of each transistor can be source electrode, and second end can be drain electrode.
On this basis, the first transistor MP1 to the 6th transistor MP6 is P-type transistor, the 9th transistor
MP7 to the 11st transistor MP9 is P-type transistor, and the 7th transistor MN1 to the 8th transistor MN2 is N-type crystal
Pipe, the tenth two-transistor MN3 to the 13rd transistor MN4 is N-type transistor.Under the premise of herein, first power supply signal
Vdd can be high level, and the second source signal Vss can be low level.
Alternatively, the first transistor MP1 to the 6th transistor MP6 is N-type transistor, the 9th transistor MP7 to institute
Stating the 11st transistor MP9 is N-type transistor, and the 7th transistor MN1 to the 8th transistor MN2 is p-type crystalline substance
Body pipe, the tenth two-transistor MN3 to the 13rd transistor MN4 is P-type transistor.Under the premise of herein, described
One power supply signal Vdd can be low level, and the second source signal Vss can be high level.
It should be noted that P-type transistor is connected when grid is low level, end when grid is high level, N-type is brilliant
Body pipe ends when grid is low level, is connected when grid is high level.
Further, since the tenth two-transistor MN3 and the 13rd transistor MN4 are connected in a manner of diode, therefore the 4th
Transistor MP4, the 9th transistor MP7, the tenth transistor MP8 and the 11st transistor MP9 constitute negative-feedback circuit.It is right below
The course of work of the negative-feedback circuit is illustrated.
For example, when the voltage of the first end of the 9th transistor MP7 increases with the increase of the voltage of output end Iout, the
The voltage of the second end of 11 transistor MP9 will be because of 3 pole gain stage circuit (i.e. the 4th transistor MP4, the tenth transistor MP8
And the 11st transistor MP9) with the 9th transistor MP7 first end voltage increase and reduce.Based on this, due to the tenth
The second end of one transistor MP9 and the control terminal of the 9th transistor MP7 constitute negative-feedback, therefore, the first of the 9th transistor MP7
The voltage at end reduces with the reduction of the voltage of the second end of the 11st transistor MP9, so that the of the 9th transistor MP7
The voltage of one end is still remained unchanged when the voltage of output end Iout increases.
In conclusion the voltage of the first end of the 9th transistor MP7 is locked by negative-feedback circuit, not with output end voltage
Change and change, so that the output constant current hold of output end.
It is illustrated below by stability of the experimental data to the output electric current of the current mirroring circuit in Fig. 3.Fig. 5 is shown
The comparison diagram of the output electric current of circuit in the output electric current and Fig. 3 of circuit in output loading variation in Fig. 1, wherein 3
For the schematic diagram of the output electric current of the circuit in the variation diagram 3 with output loading, 4 is in the variation diagrams 1 of output loading
Circuit output electric current schematic diagram.As shown in Figure 5, when output loading is smaller, the output electricity of the circuit in Fig. 1 and Fig. 3
Stream is not much different, that is, the stability for exporting electric current is not much different.But the output electric current of the circuit in Fig. 3 under high load and
Output electric current under a low load is identical, and the output electric current of the circuit in Fig. 1 under high load and output under a low load
Electric current difference is larger, that is, under high load, the stability of the output electric current of the circuit in Fig. 3 is higher than the defeated of the circuit in Fig. 1
The stability of electric current out.
Further, since the output impedance of the output end Iout of the current mirroring circuit in Fig. 2 can be approximated to be gmr0, wherein gm
For the mutual conductance of the 8th transistor, r0For the intrinsic resistance of third transistor.Therefore, as shown in figure 3, the 9th transistor MP7's
Intrinsic resistance is r0, and when the gain stage gain that constitutes of the tenth transistor MP8 and the tenth two-transistor MN3 is A, output end Iout
Output impedance can be approximated to be
From the foregoing, it will be observed that the current mirroring circuit in Fig. 3 substantially increases output end compared to the current mirroring circuit in Fig. 2
The output impedance of Iout, and then also substantially increase the stability of output end output voltage.
It should be noted that current mirroring circuit provided by the disclosure is also readily modified as CMOS (Complementary
Metal Oxide Semiconductor, complementary metal oxide semiconductor) circuit etc., it is not limited to institute in the present embodiment
The current mirroring circuit of offer, which is not described herein again.
This example embodiment also provides a kind of display driver circuit, including above-mentioned current mirroring circuit.
In the present example embodiment, each section of the current mirroring circuit is described in detail in above-mentioned part,
Therefore it repeats no more.
This example embodiment also provides a kind of display device, which may include: display panel, including array
Substrate and for the array substrate transmission data-signal multiple data lines；Data driver is used for a plurality of number
Data-signal is provided according to line；Multiple display driver circuits are electrically connected the data driver.Wherein, the display device is for example
May include mobile phone, tablet computer, laptop, Digital Frame, etc. any products or components having a display function.It needs
Illustrate: the detail of each modular unit has carried out in corresponding display driver circuit in detail in the display device
Thin description, therefore details are not described herein again.
It should be noted that although being referred to several modules or list for acting the equipment executed in the above detailed description
Member, but this division is not enforceable.In fact, according to embodiment of the present disclosure, it is above-described two or more
Module or the feature and function of unit can embody in a module or unit.Conversely, an above-described mould
The feature and function of block or unit can be to be embodied by multiple modules or unit with further division.
In addition, although describing each step of method in the disclosure in the accompanying drawings with particular order, this does not really want
These steps must be executed in this particular order by asking or implying, or having to carry out step shown in whole could realize
Desired result.Additional or alternative, it is convenient to omit multiple steps are merged into a step and executed by certain steps, and/
Or a step is decomposed into execution of multiple steps etc..
Those skilled in the art after considering the specification and implementing the invention disclosed here, will readily occur to its of the disclosure
Its embodiment.This application is intended to cover any variations, uses, or adaptations of the disclosure, these modifications, purposes or
Person's adaptive change follows the general principles of this disclosure and including the undocumented common knowledge in the art of the disclosure
Or conventional techniques.The description and examples are only to be considered as illustrative, and the true scope and spirit of the disclosure are by appended
Claim is pointed out.
Claims (10)
1. a kind of current mirroring circuit characterized by comprising
The first transistor, control terminal and second end are connect with input terminal, and first end receives the first power supply signal；
Second transistor, control terminal are connect with the control terminal of the first transistor, and first end receives the first power supply letter
Number；
Third transistor, control terminal are connect with the control terminal of the first transistor, and first end receives the first power supply letter
Number, second end connects output end；
4th transistor, control terminal are connect with the second end of the third transistor, and first end receives the first power supply letter
Number；
Operational amplifier, first end are connect with the second end of the second transistor, second end and the 4th transistor
Second end connection；
5th transistor, control terminal are connect with the third end of the operational amplifier, first end and the operational amplifier
First end connection；
6th transistor, control terminal are connect with the third end of the operational amplifier, first end and the operational amplifier
Second end connection；
7th transistor, control terminal and second end are connect with the second end of the 5th transistor, and first end receives second
Power supply signal；
8th transistor, control terminal are connect with the control terminal of the 7th transistor, and first end receives the second source letter
Number, second end is connect with the second end of the 6th transistor.
2. current mirroring circuit according to claim 1, which is characterized in that the current mirroring circuit further include:
9th transistor, first end are connect with the second end of the third transistor, and second end is connect with the output end；
Tenth transistor, control terminal are connect with the second end of the operational amplifier, and first end receives the first power supply letter
Number；
11st transistor, control terminal are connect with the second end of the tenth transistor, and first end receives first power supply
Signal, second end are connect with the control terminal of the 9th transistor；
Tenth two-transistor, control terminal and second end are connect with the second end of the tenth transistor, and first end receives institute
State second source signal；
13rd transistor, control terminal and second end are connect with the second end of the 11st transistor, and first end receives
The second source signal.
3. current mirroring circuit according to claim 1, which is characterized in that the operational amplifier is to the 5th transistor
First end and the 6th transistor first end voltage carry out clamper.
4. current mirroring circuit according to claim 2, which is characterized in that the 4th transistor, the 9th transistor,
Tenth transistor and the 11st transistor constitute negative-feedback circuit.
5. current mirroring circuit according to claim 1, which is characterized in that the first transistor to the 6th transistor
It is P-type transistor, the 7th transistor to the 8th transistor is N-type transistor.
6. current mirroring circuit according to claim 2, which is characterized in that the first transistor to the 6th crystal
Pipe is P-type transistor, and the 9th transistor to the 11st transistor is P-type transistor, the 7th transistor
It is N-type transistor to the 8th transistor, the tenth two-transistor to the 13rd transistor is N-type crystal
Pipe.
7. current mirroring circuit described according to claim 1~any one of 6, which is characterized in that the first transistor, institute
The size for stating second transistor and the third transistor is identical, the size of the 7th transistor and the 8th transistor
It is identical.
8. current mirroring circuit described according to claim 1~any one of 6, which is characterized in that the transistor is field
Effect transistor or bipolar transistor.
9. a kind of display driver circuit, which is characterized in that including the current mirror electricity as described in any one of claim 1~8
Road.
10. a kind of display device characterized by comprising
Display panel, including array substrate and for the multiple data lines to array substrate transmission data-signal；
Data driver, for providing data-signal to the multiple data lines；
Multiple display driver circuits as claimed in claim 9, are electrically connected the data driver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710735702.8A CN107390770B (en) | 2017-08-24 | 2017-08-24 | Current mirroring circuit, display driver circuit, display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710735702.8A CN107390770B (en) | 2017-08-24 | 2017-08-24 | Current mirroring circuit, display driver circuit, display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107390770A CN107390770A (en) | 2017-11-24 |
| CN107390770B true CN107390770B (en) | 2019-02-12 |
Family
ID=60345732
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710735702.8A Active CN107390770B (en) | 2017-08-24 | 2017-08-24 | Current mirroring circuit, display driver circuit, display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107390770B (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060055465A1 (en) * | 2004-09-15 | 2006-03-16 | Shui-Mu Lin | Low voltage output current mirror method and apparatus thereof |
| CN1913736A (en) * | 2006-08-30 | 2007-02-14 | 启攀微电子（上海）有限公司 | Current source circuit of multiplex parallel LED driven by one reference current |
| CN101572481B (en) * | 2009-06-11 | 2014-03-26 | 四川和芯微电子股份有限公司 | Charge pump circuit |
| CN103941792B (en) * | 2013-01-21 | 2016-06-01 | 西安电子科技大学 | Bandgap voltage reference circuit |
| CN104410395B (en) * | 2014-12-01 | 2018-03-06 | 成都芯源系统有限公司 | Overvoltage protection circuit and method for transistor switch |
-
2017
- 2017-08-24 CN CN201710735702.8A patent/CN107390770B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN107390770A (en) | 2017-11-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4761458B2 (en) | Cascode circuit and semiconductor device | |
| US7825720B2 (en) | Circuit for a low power mode | |
| US7453318B2 (en) | Operational amplifier for outputting high voltage output signal | |
| US20110018520A1 (en) | Reference voltage circuit and electronic device | |
| CN103326681A (en) | Amplifier for output buffer, signal processing apparatus and amplifier circuit | |
| US9246479B2 (en) | Low-offset bandgap circuit and offset-cancelling circuit therein | |
| CN110196397A (en) | Voltage detection circuit, semiconductor device and electronic equipment | |
| US9608617B2 (en) | Short circuit protection circuit, semiconductor device and electronic machine | |
| CN102788647A (en) | Temperature sensing device | |
| US20200395897A1 (en) | Differential input circuit, amplification circuit, and display apparatus | |
| JP4117780B2 (en) | Reference voltage circuit and electronic equipment | |
| CN104253589A (en) | Static current balance method, output stage circuit, AB type amplifier and electronic equipment | |
| CN106549639A (en) | A kind of gain-adaptive error amplifier | |
| CN109617533B (en) | High response rate amplifier circuit and related clamping method | |
| WO2012083781A1 (en) | Voltage comparator | |
| EP2824835B1 (en) | Impedance component having low sensitivity to power supply variations | |
| US9246459B2 (en) | Variable gain amplifier | |
| CN203491978U (en) | Output stage circuit, class AB amplifier and electronic device | |
| CN107390770B (en) | Current mirroring circuit, display driver circuit, display device | |
| CN102832956B (en) | Envelope detector and correlation technique | |
| CN111580437B (en) | Enabling control circuit and electronic equipment | |
| CN108319324A (en) | A kind of current mirroring circuit that power supply noise is non-sensitive, chip and communication terminal | |
| CN104035466A (en) | Fixed voltage generating circuit | |
| JP2015019160A (en) | Driver circuit, differential transmitter using the same, electronic apparatus, and industrial apparatus | |
| CN110022138B (en) | Latch and isolation circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |