CN107369628A - A kind of system-in-a-package method and its encapsulating structure of the programmable array of element - Google Patents
A kind of system-in-a-package method and its encapsulating structure of the programmable array of element Download PDFInfo
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- CN107369628A CN107369628A CN201610312644.3A CN201610312644A CN107369628A CN 107369628 A CN107369628 A CN 107369628A CN 201610312644 A CN201610312644 A CN 201610312644A CN 107369628 A CN107369628 A CN 107369628A
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- electric resistance
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 238000005516 engineering process Methods 0.000 claims abstract description 16
- 238000003491 array Methods 0.000 claims abstract description 3
- 239000000463 material Substances 0.000 claims description 28
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 24
- 239000004642 Polyimide Substances 0.000 claims description 11
- 229920001721 polyimide Polymers 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 9
- 238000003486 chemical etching Methods 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 229910001385 heavy metal Inorganic materials 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 11
- 238000005538 encapsulation Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 2
- 102100026936 2-oxoglutarate dehydrogenase, mitochondrial Human genes 0.000 description 1
- 102100031920 Dihydrolipoyllysine-residue succinyltransferase component of 2-oxoglutarate dehydrogenase complex, mitochondrial Human genes 0.000 description 1
- 101000982656 Homo sapiens 2-oxoglutarate dehydrogenase, mitochondrial Proteins 0.000 description 1
- 101000992065 Homo sapiens Dihydrolipoyllysine-residue succinyltransferase component of 2-oxoglutarate dehydrogenase complex, mitochondrial Proteins 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 235000015110 jellies Nutrition 0.000 description 1
- 239000008274 jelly Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/647—Resistive arrangements
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of system-in-a-package method and its encapsulating structure of the programmable array of element.Wherein, the system-in-a-package method includes：Several programmable arrays are respectively set to stand-alone assembly, and the nude film of the stand-alone assembly is manufactured by low temperature assembly technology；By the nude film according to default processing procedure, system in package is carried out；The programmable array includes electric resistance array；The electric resistance array is connected with a difference amplifier, there is provided some pressure drop options.Due to by original resistance to being arranged to independent resistance to array, as a single component, it is possible thereby to produce a variety of different pressure drop options in the case of using only a core or mask set, overall production cost can be preferably reduced, it is easy to design to use, improves reliability.
Description
Technical field
The present invention relates to IC package technical field, more particularly to a kind of system-in-a-package method of the programmable array of element
And its encapsulating structure.
Background technology
With the progress of encapsulation/measuring technology, high low pressure IC combination now, discrete active/passive element can
It is easily integrated in a single encapsulation, i.e. SIP (system in package) encapsulation.
At present, advanced encapsulating structure is that (generally acknowledged is good by the thin moulds of 25UM, panel (mould bases), RDL (redistributing layer) and KGD
Good chip).And state-of-the-art encapsulation technology can stack 16 nude films in a package.
Wherein, for low dropout voltage regulator (LDO), its main element includes：One power fet, a difference are put
Big device and a pair of resistors.As shown in figure 1, the resistance for being connected to difference amplifier determines pressure drop to R1 and R2 ratio.
In existing structure design, above-mentioned all devices all design on the same chip.
In addition, currently advanced RF chip layouts include the antenna (inductance coil) on metal level, in order to prevent electromagnetism
Interference, it forbids working region overlapping.Thus the movable chip more than 20% can be wasted.
Some such structure settings occupy the die area of a large amount of preciousnesses, it is also contemplated that design and processing factors, from
And it have impact on addible die count in every wafer.This design and technology also increase the burden of IC productions, so as to increase
Final production cost is added.
Therefore, prior art is also to be developed.
The content of the invention
In view of in place of above-mentioned the deficiencies in the prior art, it is an object of the invention to provide a kind of programmable array of element
System-in-a-package method and its encapsulating structure, it is intended to which die area utilization rate is limited in the prior art for solution, and production cost is high
Problem.
In order to achieve the above object, this invention takes following technical scheme：
A kind of system-in-a-package method of the programmable array of element, wherein, the system-in-a-package method includes：If will
A dry programmable array is respectively set to stand-alone assembly, and the nude film of the stand-alone assembly is manufactured by low temperature assembly technology；
By the nude film according to default processing procedure, system in package is carried out；
The programmable array includes electric resistance array；The electric resistance array is connected with a difference amplifier, there is provided if dry-pressing
Option drops.
Described system-in-a-package method, wherein, the low temperature assembly technology includes：It is heavy to put anti-light material in substrate top
Portion, by electric resistance layout pattern printing to the anti-light material；Expose and remove non-exposed part, electric resistance layout corresponding to formation
Pattern；It is heavy to put resistance material on the electric resistance layout pattern；The anti-light material forms pre- fixed gap between resistance material；
By method for chemially etching, anti-light material and resistance material attached to it are removed, the Resistor Array Projector is formed at the top of substrate
Row.
Described system-in-a-package method, wherein, the resistance material is more than 10K Ω/m2Resistance material.
Described system-in-a-package method, wherein, the programmable array also includes inductor or aerial array；The electricity
Sensor or aerial array are independent array die.
Described system-in-a-package method, wherein, the low temperature assembly method includes：Polyimides is sunk and is placed in substrate
At the top of metal level, the first predetermined connection end and first through hole are formed by mask；It is heavy to put metal, fill the first through hole simultaneously
With the metal level good contact；By chemical etching, unnecessary deposited metal and polyimides are removed, forms predetermined second
Metal level；Sunk in the second metal layer and put polyimides, and form the second predetermined through hole；Use RDL and chemical etching
Another layer of metal wiring layer is formed, as second connection end.
A kind of system-in-package structure, wherein, the system-in-package structure includes the naked of stand-alone assembly as described above
Piece.
Beneficial effect：The system-in-a-package method and its encapsulation knot of a kind of programmable array of element provided by the invention
Structure, due to by original resistance to being arranged to independent resistance to array, as a single component, it is possible thereby to only make
With a variety of different pressure drop options are produced in the case of a core or mask set, overall be produced into can be preferably reduced
This, be easy to design use, improve reliability, system in package it is more efficient.
Brief description of the drawings
Fig. 1 is LDO of the prior art schematic diagram.
Fig. 2 is the method flow diagram of the system-in-a-package method of the specific embodiment of the invention.
Fig. 3 is the schematic flow sheet of the low temperature assembly technology of the system-in-a-package method of the specific embodiment of the invention.
Fig. 4 is the inductor of the specific embodiment of the invention and/or the structural representation of aerial array.
Fig. 5 be the specific embodiment of the invention inductor and/or aerial array low temperature assembly technology schematic flow sheet.
Fig. 6 is the schematic flow sheet of the system-in-a-package method of the specific embodiment of the invention.
Embodiment
The present invention provides a kind of system-in-a-package method and its encapsulating structure of the programmable array of element.To make the present invention
Purpose, technical scheme and effect it is clearer, clear and definite, the embodiment that develops simultaneously referring to the drawings to the present invention further specifically
It is bright.It should be appreciated that specific embodiment described herein is not intended to limit the present invention only to explain the present invention.
As shown in Fig. 2 the system-in-a-package method of the programmable array for a kind of element of the specific embodiment of the invention.
The system-in-a-package method includes：
S1, several programmable arrays are respectively set to stand-alone assembly.Wherein, the programmable array is included by some
Electric resistance array of the resistance to composition.The electric resistance array interconnects with difference amplifier in an assembling process.Due in electric resistance array
Include multiple resistance pair, by selecting to use different R1 and R2, adjust different ratio so as to provide a variety of different pressures
Option drops.
S2, the nude film by the low temperature assembly technology manufacture stand-alone assembly.The process technology of the electric resistance array can be with
Using IC process technologies commonly used in the prior art, ripe, cost during reducing actual production, system in package is improved
(SIP) efficiency.
In the assembling of in general semiconductor fabrication, typically carry out at a higher temperature.The low temperature assembly technology
Refer to, when performing each installation step process, carry out under relatively low temperature environment.
S3, by the nude film according to default processing procedure, carry out system in package.
As shown in figure 3, the low temperature assembly technology includes：
S21, sink and put anti-light material behind substrate top, by electric resistance layout pattern printing to the anti-light material.Then,
Light stiffening simultaneously removes part that is non-exposed, feeling like jelly, electric resistance layout pattern corresponding to formation.
S22, sink and put resistance material on the electric resistance layout pattern.After hardening, the anti-light material step that remains with
A certain size gap is formed between resistance material.
Specifically, the resistance material is more than 10K Ω/m2Resistance material.
S23, by method for chemially etching, remove anti-light material and resistance material attached to it.Thus, remaining electricity
Resistance material part forms required resistance.
The resistance can be attached from outside by different connected modes, such as simply by the gold on array
Category piece is attached with outside, or step and external connection by oxide/contact/RDL/ metallization.
S24, deposited polymer etc., the connection being then simple to manufacture successively can be continued in the structure that above-mentioned steps are formed
Contact and metal interconnection layer.It can be connected up and be laid out for example, by RDL softwares (IC layout tools).
It by the above method, can manufacture corresponding to acquisition, there is the array (square drop) of multiple resistance pair, and pass through change
Tie point obtains different pressure drop options.
In the another specific embodiment of the present invention, the programmable array is inductor or aerial array.With Resistor Array Projector
Arrange similar, the inductor or aerial array are independent array die.As shown in figure 4, the electricity for the specific embodiment of the invention
The schematic diagram of sensor/aerial array, multiple inductors (antenna device) L1 ... Ln are provided with array die, one of those
Or the RDL for the connecting through metal interconnecting layer programmings between multiple element are completed.
Specifically, as shown in figure 5, the low temperature assembly method of the inductor or aerial array can include：
A21, it is placed in polyimides is heavy at the top of the metal level of substrate, the first predetermined connection end and the is formed by mask
One through hole (VIA1).The heavy polyimides put is exposed, hardening region corresponding to formation is simultaneously gone unless hardening region.This
Some hardening regions left of sample are the first predetermined connection end.
Electromagnetic interference can be shielded using polyimides, naturally it is also possible to which there is the oxidation of similar function using other
Thing/polymer.
A22, it is heavy put aluminium/metal, fill the first through hole VIA1 and with the metal level good contact.That is, form good
Good connecting terminal.
A23, by chemical etching, remove unnecessary deposited metal and polyimides, form predetermined second metal layer.Also
I.e. it is remaining those be the default position of the second through hole and corresponding layout of metallic layer in next step.
A23, sunk in the second metal layer and put polyimides, and form the second predetermined through hole.
A24, another layer of metal wiring layer (there is corresponding metal wiring pattern) is formed using RDL and chemical etching, made
For the second connection end of inductance/antenna.
In above-mentioned assembling process, using the assembling of lower temperature, so as to establish so some outer members, (resistance is to, electricity
Sense/antenna device), it can avoid using more step and extra mask in IC manufacturing processes, cause unnecessary EM
Waveform interference problem.
The component of high interference type either active device, and technique corresponding to use are assembled using the array being independently arranged
SIP encapsulation is carried out, footprints can be reduced.It is additionally, since element to be independently arranged in an array manner, can designs and carry for IC
For more preferable flexibility and reliability, moreover it is possible to the further time cost for reducing assembling and manufacture.
Present invention also offers a kind of system-in-package structure.The system-in-package structure includes as described above independent
The nude film of component.As shown in fig. 6, the assemble flow for the system-in-package structure.It includes the KGD of a variety of encapsulated types
(KGD1, KGD2, KGD3 etc.), and be encapsulated in a system-in-package structure.Then, it is fixed on substrate and is formed most
Whole product.
It is understood that for those of ordinary skills, can be with technique according to the invention scheme and this hair
Bright design is subject to equivalent substitution or change, and all these changes or replacement should all belong to the guarantor of appended claims of the invention
Protect scope.
Claims (6)
1. a kind of system-in-a-package method of the programmable array of element, it is characterised in that the system-in-a-package method includes：
Several programmable arrays are respectively set to stand-alone assembly, and the stand-alone assembly is manufactured by low temperature assembly technology
Nude film；
By the nude film according to default processing procedure, system in package is carried out；
The programmable array includes electric resistance array；The electric resistance array is connected with a difference amplifier, there is provided some pressure drop choosings
.
2. system-in-a-package method according to claim 1, it is characterised in that the low temperature assembly technology includes：
It is heavy to put anti-light material at the top of substrate, by electric resistance layout pattern printing to the anti-light material；
Expose and remove non-exposed part, electric resistance layout pattern corresponding to formation；
It is heavy to put resistance material on the electric resistance layout pattern；The anti-light material forms pre- fixed gap between resistance material；
By method for chemially etching, anti-light material and resistance material attached to it are removed, the electricity is formed at the top of substrate
Hinder array.
3. system-in-a-package method according to claim 2, it is characterised in that the resistance material is more than 10K Ω/m2
Resistance material.
4. system-in-a-package method according to claim 1, it is characterised in that the programmable array also includes inductor
Or aerial array；
The inductor or aerial array are independent array die.
5. system-in-a-package method according to claim 4, it is characterised in that the low temperature assembly method includes：
By the heavy metal level top for being placed in substrate of polyimides, the first predetermined connection end and first through hole are formed by mask；
It is heavy to put metal, fill the first through hole and with the metal level good contact；
By chemical etching, unnecessary deposited metal and polyimides are removed, forms predetermined second metal layer；
Sunk in the second metal layer and put polyimides, and form the second predetermined through hole；
Another layer of metal wiring layer is formed using RDL and chemical etching, as second connection end.
6. a kind of system-in-package structure, it is characterised in that the system-in-package structure includes as claimed in claim 1 only
The nude film of vertical component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610312644.3A CN107369628A (en) | 2016-05-13 | 2016-05-13 | A kind of system-in-a-package method and its encapsulating structure of the programmable array of element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610312644.3A CN107369628A (en) | 2016-05-13 | 2016-05-13 | A kind of system-in-a-package method and its encapsulating structure of the programmable array of element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107369628A true CN107369628A (en) | 2017-11-21 |
Family
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610312644.3A Pending CN107369628A (en) | 2016-05-13 | 2016-05-13 | A kind of system-in-a-package method and its encapsulating structure of the programmable array of element |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101315914A (en) * | 2007-05-29 | 2008-12-03 | 台湾积体电路制造股份有限公司 | Semiconductor interposer and its application in electronic package |
| US20140042627A1 (en) * | 2012-08-09 | 2014-02-13 | International Business Machines Corporation | Electronic structure containing a via array as a physical unclonable function |
| CN103872012A (en) * | 2012-12-13 | 2014-06-18 | 台湾积体电路制造股份有限公司 | Antenna Apparatus and Method |
-
2016
- 2016-05-13 CN CN201610312644.3A patent/CN107369628A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101315914A (en) * | 2007-05-29 | 2008-12-03 | 台湾积体电路制造股份有限公司 | Semiconductor interposer and its application in electronic package |
| US20140042627A1 (en) * | 2012-08-09 | 2014-02-13 | International Business Machines Corporation | Electronic structure containing a via array as a physical unclonable function |
| CN103872012A (en) * | 2012-12-13 | 2014-06-18 | 台湾积体电路制造股份有限公司 | Antenna Apparatus and Method |
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Application publication date: 20171121 |