CN107359946B - Circuit delay self-detection method, device and system - Google Patents
Circuit delay self-detection method, device and system Download PDFInfo
- Publication number
- CN107359946B CN107359946B CN201610977256.7A CN201610977256A CN107359946B CN 107359946 B CN107359946 B CN 107359946B CN 201610977256 A CN201610977256 A CN 201610977256A CN 107359946 B CN107359946 B CN 107359946B
- Authority
- CN
- China
- Prior art keywords
- analog signal
- digital signal
- processing
- time
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/30—Monitoring; Testing of propagation channels
- H04B17/309—Measuring or estimating channel quality parameters
- H04B17/364—Delay profiles
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/14—Network architectures or network communication protocols for network security for detecting or protecting against malicious traffic
- H04L63/1441—Countermeasures against malicious traffic
- H04L63/1466—Active attacks involving interception, injection, modification, spoofing of data unit addresses, e.g. hijacking, packet injection or TCP sequence number attacks
Abstract
The invention provides a circuit delay self-detection method, a device and a system, wherein the circuit delay self-detection method comprises the following steps: receiving a first analog signal, and performing first processing on the first analog signal to generate a first digital signal; acquiring a first digital signal, performing second processing on the first digital signal to generate a second analog signal, and transmitting the second analog signal; receiving a second analog signal, and performing first processing on the second analog signal to generate a second digital signal, wherein the second digital signal is the same as the first digital signal; acquiring a second digital signal; a first processing time T1 is obtained, the first processing time T1 is a difference between a time at which the second digital signal is obtained and a time at which the second analog signal is transmitted, and the circuit delay is determined to be the first processing time T1.
Description
Technical Field
The invention relates to the field of circuit delay detection, in particular to a circuit delay self-detection method, a device and a system.
Background
At present, a near field communication method is applied to various fields (for example, payment), and a device a and a device B that communicate by using the near field communication method (for example, RFID, NFC, infrared, or bluetooth, etc.) may have a safety hazard, for example, as shown in fig. 1, a data channel established by the device a and the device B is intervened by a third party, so that data in the whole communication process reaches a device at the other end only through the third party without being known by both parties legally, which finally results in data leakage.
Currently, whether the communication data between the device a and the device B is hijacked or not can be judged by the following methods: after the device A sends the instruction signal to the device B, the device A waits for receiving the response signal of the device B, the time from the sending of the instruction signal to the receiving of the response signal of the device B by the device A is the waiting time, and as long as the waiting time is within the preset time, the communication data between the device A and the device B are considered not hijacked by a third party.
However, the response signal of the device B received by the device a is an analog signal, that is, the analog signal received by the device a is a response signal modulated by response data, and after the device a receives the response signal, as shown in fig. 2, the received response signal is firstly demodulated by the receiving circuit to generate response data, but the receiving circuit has a low-pass filter for filtering out a high-frequency signal component, and the low-pass filter has a circuit delay which is not negligible with respect to the waiting time. Because the device a acquires the response data and is processed by the main control chip in the device a, the device a can accurately acquire the time of the response data through the main control chip, and under the condition that the receiving circuit has circuit delay, the time of the device a acquiring the response data and the time of receiving the response signal cannot be considered to be the same, and the device a cannot accurately acquire the time of receiving the response signal. To accurately measure the latency of the device a, a method for measuring the circuit delay of the receiving circuit is needed.
Disclosure of Invention
The present invention aims to solve one of the above problems.
The invention mainly aims to provide a circuit delay self-detection method;
another object of the present invention is to provide a circuit delay self-test device;
it is another object of the present invention to provide a circuit delay self-test system.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
the invention provides a circuit delay self-detection method on one hand, which comprises the following steps: receiving a first analog signal, and performing first processing on the first analog signal to generate a first digital signal; acquiring a first digital signal, performing second processing on the first digital signal to generate a second analog signal, and transmitting the second analog signal; receiving a second analog signal, and performing first processing on the second analog signal to generate a second digital signal, wherein the second digital signal is the same as the first digital signal; acquiring a second digital signal; a first processing time T1 is obtained, the first processing time T1 is a difference between a time at which the second digital signal is obtained and a time at which the second analog signal is transmitted, and the circuit delay is determined to be the first processing time T1.
Further, prior to receiving the first analog signal, the method further comprises: and sending a third analog signal outwards, wherein the first analog signal is generated after the response device receiving the third analog signal performs third processing on the third analog signal.
In addition, the method further comprises the following steps: acquiring a second processing time T2, wherein the second processing time T2 is the difference between the moment of acquiring the first digital signal and the moment of sending the third analog signal outwards; and calculating the time difference between the second processing time T2 and the first processing time T1, and judging whether the time difference is smaller than a preset value, if so, determining that the communication data is not hijacked.
Further, the first processing the first analog signal to generate a first digital signal includes: demodulating the first analog signal to generate a first digital signal; performing a second process on the first digital signal to generate a second analog signal comprises: performing first modulation on the first digital signal to generate a second analog signal; performing a first process on the second analog signal to generate a second digital signal comprises: the second analog signal is demodulated to generate a second digital signal.
In addition, the responding device which receives the third analog signal performs the third processing on the third analog signal, and the third processing at least comprises the following steps: and the response device demodulates the third analog signal to generate a third digital signal, generates a first digital signal according to the third digital signal response, and performs second modulation on the first digital signal to generate a first analog signal, wherein the modulation mode of the first modulation is the same as that of the second modulation.
Another aspect of the present invention provides a circuit delay self-detecting device, including: the receiving module is used for receiving a first analog signal; the first processing module is used for performing first processing on the first analog signal to generate a first digital signal; the digital signal acquisition module is used for acquiring a first digital signal; the second processing module is used for carrying out second processing on the first digital signal to generate a second analog signal; the sending module is used for sending the second analog signal; the receiving module is also used for receiving a second analog signal; the first processing module is further used for performing first processing on the second analog signal to generate a second digital signal, and the second digital signal is the same as the first digital signal; the digital signal acquisition module is also used for acquiring a second digital signal; a processing time obtaining module, configured to obtain a first processing time T1, where the first processing time T1 is a difference between a time when the second digital signal is obtained and a time when the second analog signal is sent; and the determining module is used for determining the circuit delay of the first processing module as the first processing time T1.
In addition, the method further comprises the following steps: and the sending module is used for sending a third analog signal to the outside, wherein the first analog signal received by the receiving module is generated after the third analog signal is subjected to third processing by the response device which receives the third analog signal.
In addition, the method further comprises the following steps: a calculation module and a judgment module; the processing time acquiring module is further configured to acquire a second processing time T2, where the second processing time T2 is a difference between a time when the first digital signal is acquired and a time when the third analog signal is sent outwards; a calculating module for calculating a time difference between the second processing time T2 and the first processing time T1; the judging module is used for judging whether the time difference value is smaller than a preset value or not; and the determining module is also used for determining that the communication data between the circuit delay self-detection device and the response device is not hijacked when the time difference value is judged to be smaller than the preset value.
Furthermore, the first processing module comprises at least: a demodulation module; the demodulation module is used for demodulating the first analog signal to generate a first digital signal; and the demodulation module is also used for demodulating the second analog signal to generate a second digital signal.
Another aspect of the invention provides a circuit delay self-test system comprising the circuit delay self-test apparatus and a response apparatus as claimed above; the response device is also used for receiving the third analog signal and carrying out third processing on the third analog signal to generate a first analog signal; the response device is used for sending a first analog signal to the circuit delay self-detection device; the answering device is further used for acquiring a third processing time T3, wherein the third processing time T3 is the difference value between the moment when the answering device sends the first analog signal to the circuit delay self-detection device and the moment when the answering device receives the third analog signal; the preset value is greater than the third processing time T3.
According to the technical scheme provided by the invention, the invention provides the circuit delay self-detection method, on one hand, the circuit delay of the receiving circuit in the circuit delay self-detection device can be detected; on the other hand, whether the communication data is hijacked or not in the process of communication between the circuit delay self-detection device and the answering device can be determined.
The invention also provides a circuit delay self-detection device, which can detect the circuit delay of the first processing module for realizing the demodulation function in the circuit delay self-detection device on one hand, and can also determine whether the communication data is hijacked or not in the communication process of the circuit delay self-detection device and the response device on the other hand.
The invention also provides a circuit delay self-detection system which can detect the circuit delay of the first processing module for realizing the demodulation function in the circuit delay self-detection device on one hand and can determine whether the communication data is hijacked or not in the communication process of the circuit delay self-detection device and the response device on the other hand.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
FIG. 1 is a diagram illustrating a system for hijacking communication data between a device A and a device B by a third party according to the background art of the present invention;
fig. 2 is a schematic diagram of a system structure in the background art of the present invention when communication data between a circuit delay apparatus a and a circuit delay apparatus B is hijacked by a third party;
fig. 3 is a flowchart of a circuit delay self-detection method according to embodiment 1 of the present invention;
fig. 4 is a flowchart of a circuit delay self-detection method according to embodiment 2 of the present invention;
fig. 5 is a flowchart of a circuit delay self-detection method according to embodiment 3 of the present invention;
fig. 6 is a schematic structural diagram of a circuit delay self-detection apparatus according to embodiment 4 of the present invention;
fig. 7 is a schematic structural diagram of another circuit delay self-detection apparatus according to embodiment 4 of the present invention;
fig. 8 is a schematic structural diagram of a circuit delay self-detection system according to embodiment 5 of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or quantity or location.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
Example 1
Fig. 3 is a flowchart of the circuit delay self-detection method provided in embodiment 1, and as shown in fig. 3, the method includes the following steps (S101 to S105):
step S101: receiving a first analog signal, and performing first processing on the first analog signal to generate a first digital signal;
the execution main body of the embodiment of the present invention may be a circuit delay self-detection device, for example, a card reader, a smart card, or the like, and the circuit delay self-detection device in the embodiment includes a receiving circuit for implementing a demodulation function, where the receiving circuit causes a circuit delay when demodulating a received modulated signal.
The circuit delay self-detection device in this embodiment receives the first analog signal, and the first analog signal received by the circuit delay self-detection device is sent by the answering device, where a communication mode between the circuit delay self-detection device and the answering device may be RFID, NFC, infrared, or bluetooth, and the circuit delay self-detection device may receive the first analog signal sent by the answering device through a communication interface (e.g., an antenna).
In this embodiment, a receiving circuit in the circuit delay self-detection apparatus performs a first process on a first analog signal to generate a first digital signal, where the performing the first process on the first analog signal to generate the first digital signal includes: the first analog signal is demodulated to generate a first digital signal. It can be seen that the receiving circuit is a circuit for realizing the demodulation function, a low-pass filter is arranged in the receiving circuit for realizing the demodulation function, and when a signal passes through the low-pass filter, circuit delay is not negligible.
Step S102: acquiring a first digital signal, performing second processing on the first digital signal to generate a second analog signal, and transmitting the second analog signal;
in this embodiment, it is understood that the circuit delay of the circuit delay self-detection apparatus is a circuit delay caused by the receiving circuit in the process of demodulating the first analog signal to generate the first digital signal, but since the circuit delay self-detection apparatus cannot accurately determine the time of receiving the first analog signal, the circuit delay caused by the receiving circuit in the process of demodulating the first analog signal to generate the first digital signal cannot be accurately detected. In order to determine the time for receiving the analog signal by the receiving circuit, the circuit delay self-detection device performs second processing on the acquired first digital signal to generate a second analog signal and sends the second analog signal to the receiving circuit.
In this embodiment, the second processing the first digital signal to generate the second analog signal includes: the first digital signal is first modulated to generate a second analog signal. Specifically, after the circuit delay self-detection device demodulates the first analog signal to generate the first digital signal, the circuit delay self-detection device obtains the first digital signal, and performs the first modulation on the first digital signal to generate the second analog signal. The modulation method of the first modulation is not specifically limited in this embodiment, and may be amplitude modulation, phase modulation, or frequency modulation, for example.
In this embodiment, the circuit delay self-detection device modulates and generates a second analog signal, and then transmits the second analog signal, where a manner of transmitting the second analog signal by the circuit delay self-detection device is not particularly limited, for example, the second analog signal may be transmitted through a physical connection line (e.g., a wire), or the second analog signal may be transmitted to the outside through a communication interface (e.g., an antenna).
Step S103: receiving a second analog signal, and performing first processing on the second analog signal to generate a second digital signal, wherein the second digital signal is the same as the first digital signal;
in this embodiment, the first processing the second analog signal to generate a second digital signal includes: and demodulating the second analog signal to generate a second digital signal. Specifically, the circuit delay self-detection device receives a second analog signal sent by the circuit delay self-detection device, a receiving circuit in the circuit delay self-detection device demodulates the second analog signal to generate a second digital signal, and since the second analog signal is generated by performing first modulation on the first digital signal, the second digital signal generated by demodulating the second analog signal is the same as the first digital signal, the time for the circuit delay self-detection device to perform the first processing on the second analog signal to generate the second digital signal is the same as the time for the circuit delay self-detection device to perform the first processing on the first analog signal to generate the first digital signal, the circuit delay self-detection device sends the second analog signal by itself, and performing a first processing on the received second analog signal to generate a second digital signal may determine a circuit delay of the circuit delay self-detection device performing the first processing on the first analog signal to generate the first digital signal.
Step S104: acquiring a second digital signal;
in this embodiment, after the circuit delay self-detection device demodulates the second analog signal to generate the second digital signal, the circuit delay self-detection device obtains the second digital signal.
Step S105: a first processing time T1 is obtained, the first processing time T1 is a difference between a time at which the second digital signal is obtained and a time at which the second analog signal is transmitted, and the circuit delay is determined to be the first processing time T1.
In this embodiment, the first processing time T1 is a difference between a time when the circuit delay self-checking device obtains the second digital signal and a time when the circuit delay self-checking device sends the second analog signal, a circuit delay caused by a receiving circuit in the circuit delay self-checking device is the first processing time T1, and the circuit delay self-checking device obtains the first processing time T1 and determines that the circuit delay is the first processing time T1.
As an alternative embodiment, the first processing time T1 in this embodiment may be a difference between a time when the acquisition of the second digital signal is started and a time when the transmission of the second analog signal is started, a difference between a time when the acquisition of the second digital signal is started and a time when the transmission of the second analog signal is completed, a difference between a time when the acquisition of the second digital signal is completed and a time when the transmission of the second analog signal is started, or a difference between a time when the acquisition of the second digital signal is completed and a time when the transmission of the second analog signal is completed, and the above embodiments are all within the protection scope of the present invention.
In this embodiment, the manner in which the circuit delay self-detection device obtains the first processing time T1 is not specifically limited in this embodiment, and an embodiment in which the circuit delay self-detection device obtains the first processing time T1 is given as an example below: the circuit delay self-detection device starts to time at the moment of sending the second analog signal, and obtains a value reached by the time of obtaining the second digital signal at the moment of obtaining the second digital signal by the circuit delay self-detection device, wherein the value is the first processing time T1.
The circuit delay self-detection method provided by the embodiment can detect the circuit delay of the receiving circuit in the circuit delay self-detection device.
Example 2
Fig. 4 is a flowchart of the circuit delay self-detection method provided in this embodiment 2, and as shown in fig. 4, the method includes the following steps (S301 to S306):
step S301: and sending a third analog signal outwards, wherein the first analog signal is generated after the response device receiving the third analog signal performs third processing on the third analog signal.
In this embodiment, the circuit delays the sending of the third analog signal from the detection device and the response device receives the third analog signal. The embodiment of the method for sending the third analog signal to the outside by the circuit delay self-detection device is not particularly limited, for example, the circuit delay self-detection device may send the third analog signal to the outside by RFID, NFC, infrared, bluetooth, or other methods. In this embodiment, the circuit delay self-detection device sends the third analog signal to the response device, and the circuit delay self-detection device and the response device form a communication system, so as to detect whether communication data between the circuit delay self-detection device and the response device is hijacked.
In this embodiment, the response device that receives the third analog signal performs a third process on the third analog signal, which at least includes: and the response device demodulates the third analog signal to generate a third digital signal, generates a first digital signal according to the third digital signal response, and performs second modulation on the first digital signal to generate a first analog signal, wherein the modulation mode of the first modulation is the same as that of the second modulation. And after the response device carries out third processing on the third analog signal to generate a first analog signal, the response device sends the first analog signal outwards as a response signal for the third analog signal.
Steps S302 to S306 are the same as steps S101 to S105, and are not described again here.
In the circuit delay self-detection method provided in this embodiment, in addition to detecting the circuit delay of the receiving circuit in the circuit delay self-detection device, the circuit delay self-detection device and the answering device form a communication system, so as to detect whether communication data between the circuit delay self-detection device and the answering device is hijacked.
Example 3
The present embodiment provides a circuit delay self-detection method, and fig. 5 is a flowchart of the circuit delay self-detection method provided in embodiment 3, as shown in fig. 5, including the following steps (S201 to S208):
step S201: and sending a third analog signal outwards, wherein the first analog signal is generated after the response device receiving the third analog signal performs third processing on the third analog signal.
The circuit delay self-detection method provided in this embodiment may detect a circuit delay of a receiving circuit in the circuit delay self-detection device, and may determine whether communication data is hijacked in a communication process between the circuit delay self-detection device and the response device.
In this embodiment, to detect whether the communication data between the circuit delay self-detection device and the responder is hijacked, the circuit delay self-detection device first sends a third analog signal to the outside, and the responder receives the third analog signal. The embodiment of the method for sending the third analog signal to the outside by the circuit delay self-detection device is not particularly limited, for example, the circuit delay self-detection device may send the third analog signal to the outside by RFID, NFC, infrared, bluetooth, or other methods.
In this embodiment, the response device that receives the third analog signal performs a third process on the third analog signal, which at least includes: and the response device demodulates the third analog signal to generate a third digital signal, generates a first digital signal according to the third digital signal response, and performs second modulation on the first digital signal to generate a first analog signal, wherein the modulation mode of the first modulation is the same as that of the second modulation. And after the response device carries out third processing on the third analog signal to generate a first analog signal, the response device sends the first analog signal outwards as a response signal for the third analog signal.
Step S202 is the same as step S101 in embodiment 1, and is not described again here.
Step S203 is the same as step S102 in embodiment 1, and is not described again here.
Step S204: acquiring a second processing time T2, wherein the second processing time T2 is the difference between the moment of acquiring the first digital signal and the moment of sending the third analog signal outwards;
in this embodiment, the second processing time T2 is a difference between a time when the circuit delay self-detection device obtains the first digital signal and a time when the circuit delay self-detection device sends the third analog signal to the outside, and a total time from the circuit delay self-detection device sending the third analog signal to the receiving of the first digital signal is the second processing time T2.
In this embodiment, the second processing time T2 may be a difference between a time when the first digital signal starts to be acquired and a time when the third analog signal starts to be sent out, a difference between a time when the first digital signal is acquired and a time when the third analog signal starts to be sent out, a difference between a time when the first digital signal starts to be acquired and a time when the third analog signal starts to be sent out, or a difference between a time when the first digital signal is acquired and a time when the third analog signal is sent out, and of course, this embodiment is not particularly limited.
Further, since the first analog signal is generated by first modulating the first digital signal and the second analog signal is generated by second modulating the first digital signal, when the modulation scheme of the first modulation is the same as the modulation scheme of the second modulation, the circuit delay of the receiving circuit in the circuit delay self-detection apparatus for demodulating the first analog signal is the same as the circuit delay of the second analog signal.
It should be noted that it is within the scope of the present invention that step S204 is executed after step S203 and before step S208.
Steps S205 to S207 are the same as steps S103 to S105 in embodiment 1, and are not described again here.
Step S208: and calculating the time difference between the second processing time T2 and the first processing time T1, and judging whether the time difference is smaller than a preset value, if so, determining that the communication data is not hijacked.
In this embodiment, the total time from the sending of the third analog signal to the receiving of the first digital signal by the circuit delay self-test device is the second processing time T2, the circuit delay caused by the receiving circuit in the circuit delay self-test device is the first processing time T1, and the time from the sending of the third analog signal to the receiving of the first analog signal by the circuit delay self-test device is the time difference between the second processing time T2 and the first processing time T1. The circuit delay self-detection device judges whether the time difference is smaller than a preset value, namely the circuit delay self-detection device judges whether the time from sending the instruction signal to receiving the response signal is smaller than the preset value, and if the time difference is smaller than the preset value, the circuit delay self-detection device determines that the communication data between the circuit delay self-detection device and the answering device is not hijacked.
By the circuit delay self-detection method provided by the embodiment, on one hand, the circuit delay of the receiving circuit in the circuit delay self-detection device can be detected, and on the other hand, whether the communication data between the circuit delay self-detection device and the response device is hijacked or not can be determined.
Example 4
The present embodiment provides a circuit delay self-detection device 30, as shown in fig. 6, the device includes: a receiving module 301, configured to receive a first analog signal; a first processing module 302, configured to perform a first processing on the first analog signal to generate a first digital signal; a digital signal obtaining module 303, configured to obtain a first digital signal; a second processing module 304, configured to perform a second processing on the first digital signal to generate a second analog signal; a transmitting module 305, configured to transmit a second analog signal; the receiving module 301 is further configured to receive a second analog signal; the first processing module 302 is further configured to perform a first processing on the second analog signal to generate a second digital signal, where the second digital signal is the same as the first digital signal; the digital signal acquisition module 303 is further configured to acquire a second digital signal; a processing time obtaining module 306, configured to obtain a first processing time T1, where the first processing time T1 is a difference between a time when the second digital signal is obtained and a time when the second analog signal is sent; a determining module 307, configured to determine a circuit delay of the first processing module 302 as the first processing time T1.
In this embodiment, the first analog signal received by the receiving module 301 is sent by a response device, the communication mode between the circuit delay self-detection device 30 and the response device may be RFID, NFC, infrared, or bluetooth, and the receiving module 301 may be a communication interface (e.g., an antenna), and of course, the receiving module 301 may also be a physical connection line (e.g., a wire), which is not limited in this embodiment.
In this embodiment, the first processing module 302 performs a first processing on the first analog signal to generate a first digital signal, where the first processing module 302 at least includes: a demodulation module; the demodulation module demodulates the first analog signal to generate a first digital signal. It can be seen that the first processing module 302 is a module for implementing a demodulation function, a low-pass filter is present in the first processing module 302 for implementing the demodulation function, and when a signal passes through the low-pass filter, a circuit delay is present and is not negligible, and the circuit delay detected in the present invention is the circuit delay of the first processing module 302 for implementing the demodulation function.
In this embodiment, although it can be understood that the circuit delay of the circuit delay self-detection apparatus 30 is the circuit delay caused by the first processing module 302 in the process of demodulating the first analog signal to generate the first digital signal, the processing time obtaining module 306 cannot accurately determine the time for receiving the first analog signal, and therefore cannot accurately detect the circuit delay caused by the first processing module 302 in the process of demodulating the first analog signal to generate the first digital signal. In order to determine the time for receiving the analog signal by the receiving circuit, the second processing module 304 in the circuit delay self-detection apparatus 30 performs the second processing on the first digital signal acquired by the digital signal acquisition module 303 to generate the second analog signal, and sends the second analog signal to the receiving module 301, so that since the second analog signal is sent by the sending module 305 of the second processing module, the processing time acquisition module 306 can determine the time for sending the second analog signal, that is, can determine the circuit delay caused by the first processing module 302 in the circuit delay self-detection apparatus 30. In this embodiment, the second processing module 304 performs a second processing on the first digital signal to generate a second analog signal. Specifically, after the first processing module 302 demodulates the first analog signal to generate a first digital signal, the digital signal obtaining module 303 obtains the first digital signal, and the second processing module 304 performs the first modulation on the first digital signal obtained by the digital signal obtaining module 303 to generate a second analog signal. The modulation method of the first modulation is not specifically limited in this embodiment, and may be amplitude modulation, phase modulation, or frequency modulation, for example.
In this embodiment, after the second processing module 304 generates the second analog signal through modulation, the sending module 305 sends the second analog signal to the receiving circuit, where a manner of sending the second analog signal by the sending module 305 is not particularly limited, for example, the second analog signal may be directly sent to the receiving module 301 through a physical connection line (e.g., a wire), or the second analog signal may be sent to the outside through a communication interface (e.g., an antenna), and the receiving module 301 receives the second analog signal again.
In this embodiment, the demodulation module in the first processing module 302 further demodulates the second analog signal to generate a second digital signal. Specifically, the receiving module 301 receives a second analog signal sent by itself, the first processing module 302 demodulates the second analog signal to generate a second digital signal, and the second analog signal is generated by performing the first modulation on the first digital signal, so that the second digital signal generated by demodulating the second analog signal is the same as the first digital signal.
In this embodiment, after the first processing module 302 performs the second processing on the second analog signal to generate the second digital signal, the digital signal obtaining module 303 obtains the second digital signal. The first processing time T1 is a difference between a time when the digital signal obtaining module 303 obtains the second digital signal and a time when the sending module 305 sends the second analog signal, a circuit delay caused by the first processing module 302 in the circuit delay self-detection apparatus 30 is the first processing time T1, the processing time obtaining module 306 obtains the first processing time T1, and the determining module 307 determines that the circuit delay is the first processing time T1.
As an alternative embodiment, the first processing time T1 in this embodiment may be a difference between a time when the digital signal acquiring module 303 starts acquiring the second digital signal and a time when the transmitting module 305 starts transmitting the second analog signal, a difference between a time when the digital signal acquiring module 303 starts acquiring the second digital signal and a time when the transmitting module 305 completes transmitting the second analog signal, a difference between a time when the digital signal acquiring module 303 finishes acquiring the second digital signal and a time when the transmitting module 305 starts transmitting the second analog signal, or a difference between a time when the digital signal acquiring module 303 finishes acquiring the second digital signal and a time when the transmitting module 305 completes transmitting the second analog signal, and the above embodiments are all within the protection scope of the present invention.
In this embodiment, the manner in which the processing time obtaining module 306 obtains the first processing time T1 is not specifically limited in this embodiment, and an embodiment in which the processing time obtaining module 306 obtains the first processing time T1 is given as follows: the processing time obtaining module 306 starts to count at the time when the sending module 305 sends the second analog signal, and obtains a value reached by the counting at the time when the digital signal obtaining module 303 obtains the second digital signal, where the value is the first processing time T1.
In addition, as an optional implementation manner of this embodiment, as shown in fig. 7, the circuit delay self-detection apparatus 30 further includes a calculating module 308 and a determining module. The sending module 305 is further configured to send a third analog signal to the outside, where the first analog signal received by the receiving module 301 is generated after the third analog signal is subjected to third processing by the responding apparatus that receives the third analog signal. The processing time obtaining module 306 is further configured to obtain a second processing time T2, where the second processing time T2 is a difference between a time when the first digital signal is obtained and a time when the third analog signal is sent outwards; a calculating module 308 for calculating a time difference between the second processing time T2 and the first processing time T1; the judging module is used for judging whether the time difference value is smaller than a preset value or not; the determining module 307 is further configured to determine that the communication data between the self-detection device 30 and the responding device is not hijacked when the time difference is determined to be smaller than the preset value.
As an optional implementation manner of this embodiment, in order to detect whether the communication data between the circuit delay self-detection device 30 and the responding device is hijacked, the sending module 305 first sends a third analog signal to the outside, and the responding device receives the third analog signal. The embodiment of the method for sending the third analog signal to the outside by the sending module 305 is not particularly limited, for example, the sending module 305 may send the third analog signal to the outside by using RFID, NFC, infrared, or bluetooth.
As an optional implementation manner of this embodiment, the second processing time T2 may be a difference between a time when the digital signal acquiring module 303 starts acquiring the first digital signal and a time when the sending module 305 starts sending the third analog signal to the outside, a difference between a time when the digital signal acquiring module 303 starts acquiring the first digital signal and a time when the sending module 305 sends the third analog signal to the outside, a difference between a time when the digital signal acquiring module 303 finishes acquiring the first digital signal and a time when the sending module 305 starts sending the third analog signal to the outside, or a difference between a time when the digital signal acquiring module 303 finishes acquiring the first digital signal and a time when the sending module 305 sends the third analog signal to the outside. The total time for sending the third analog signal from the sending module 305 in the circuit delay self-detection apparatus 30 to the digital signal obtaining module 303 to obtain the first digital signal is the second processing time T2. In addition, since the first analog signal is generated by performing the first modulation on the first digital signal, and the second analog signal is generated by performing the second modulation on the first digital signal, when the modulation scheme of the first modulation is the same as the modulation scheme of the second modulation, the circuit delay of the first processing module 302 for processing the first analog signal is the same as the circuit delay of the second processing module 302 for processing the second analog signal, the circuit delay caused by the first processing module 302 for processing the first analog signal to obtain the first digital signal is the first processing time T1, and the time difference between the second processing time T2 and the first processing time T1 is the time from the time when the transmitting module 305 transmits the third analog signal to the time when the first analog signal is received. The judging module in the circuit delay self-detection device 30 judges whether the time difference is smaller than the preset value, that is, the judging module in the circuit delay self-detection device 30 judges whether the time from sending the command signal to receiving the response signal is smaller than the preset value, if the judging module judges that the time difference is smaller than the preset value, the determining module 307 determines that the communication data between the circuit delay self-detection device 30 and the answering machine is not hijacked.
Through the circuit delay self-detection device 30 provided in this embodiment, on one hand, the circuit delay of the first processing module 302 that implements the demodulation function in the circuit delay self-detection device 30 can be detected, and on the other hand, it can be determined whether the communication data between the circuit delay self-detection device 30 and the responder is hijacked.
Example 5
The present embodiment provides a circuit delay self-detection system, as shown in fig. 8, the system includes: the circuit delays the self-detection means 30 and the response means 40.
The circuit delay self-detecting device 30 in this embodiment is the same as the circuit delay self-detecting device 30 in embodiment 3, and is not described herein again.
In this embodiment, after the circuit delays the sending module in the self-detection device 30 to send the third analog signal to the outside, the response device 40 receives the third analog signal and performs the third processing on the third analog signal to generate the first analog signal. Wherein, the third processing of the third analog signal by the responder 40 at least includes: the responder device 40 demodulates the third analog signal to generate a third digital signal, responds to the third digital signal to generate a first digital signal, and performs second modulation on the first digital signal to generate a first analog signal, wherein the modulation mode of the first modulation is the same as that of the second modulation.
In the present embodiment, the responder device 40 generates the first analog signal and then transmits the first analog signal to the circuit delay self-tester 30. The embodiment of the method for the answering device 40 to send the first analog signal to the circuit delay self-detection device 30 is not limited in particular, for example, the answering device 40 can send the first analog signal to the circuit delay self-detection device 30 by RFID, NFC, infrared or bluetooth.
In this embodiment, the responder device 40 is further configured to obtain a third processing time T3, where the third processing time T3 is the difference between the time when the responder device 40 sends the first analog signal to the circuit delay self-detection device 30 and the time when the responder device 40 receives the third analog signal. Specifically, the third processing time T3 represents the time required by the responder device 40 to transmit the first analog signal from receiving the third analog signal, and in the case where the responder device 40 and the circuit delay self-test device 30 are close to each other, the transmission time of the signal between the responder device 40 and the circuit delay self-test device 30 can be ignored, and the time required by the circuit delay self-test device 30 to transmit the third analog signal to receive the first analog signal (i.e., the time difference between the second processing time T2 and the first processing time T1) is the same as the third processing time T3. The circuit delay self-detection device 30 determines whether the time difference between the second processing time T2 and the first processing time T1 is smaller than a preset value, wherein the preset value is larger than the third processing time T3, and if the time difference is smaller than the preset value, it is determined that the communication data between the circuit delay self-detection device 30 and the answering device 40 is not hijacked.
It should be noted that, in order to ensure the accuracy of determining whether the communication data is hijacked, the preset value should be greater than the third processing time T3 and the difference between the preset value and the third processing time T3 should not be too large.
Through the circuit delay self-detection system provided in this embodiment, on one hand, the circuit delay of the first processing module that implements the demodulation function in the circuit delay self-detection device 30 can be detected, and on the other hand, it can also be determined whether the communication data between the circuit delay self-detection device 30 and the answering device 40 is hijacked.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made in the above embodiments by those of ordinary skill in the art without departing from the principle and spirit of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (8)
1. A method for self-detecting circuit delay, the method comprising:
receiving a first analog signal, and performing first processing on the first analog signal to generate a first digital signal;
acquiring the first digital signal, performing second processing on the first digital signal to generate a second analog signal, and sending the second analog signal;
receiving the second analog signal, and performing first processing on the second analog signal to generate a second digital signal, wherein the second digital signal is the same as the first digital signal;
acquiring the second digital signal;
acquiring a first processing time T1, wherein the first processing time T1 is a difference value between the time of acquiring the second digital signal and the time of transmitting the second analog signal, and determining a circuit delay as the first processing time T1;
wherein the first processing the first analog signal to generate a first digital signal comprises: demodulating the first analog signal to generate a first digital signal;
the second processing the first digital signal to generate a second analog signal comprises: performing first modulation on the first digital signal to generate a second analog signal;
the first processing the second analog signal to generate a second digital signal comprises: and demodulating the second analog signal to generate a second digital signal.
2. The method of claim 1, wherein prior to receiving the first analog signal, the method further comprises:
and sending a third analog signal to the outside, wherein the first analog signal is generated after the third analog signal is subjected to third processing by a response device which receives the third analog signal.
3. The method of claim 2, further comprising:
acquiring a second processing time T2, wherein the second processing time T2 is the difference between the time of acquiring the first digital signal and the time of sending a third analog signal outwards;
and calculating a time difference value between the second processing time T2 and the first processing time T1, judging whether the time difference value is smaller than a preset value, and if so, determining that the communication data is not hijacked.
4. The method according to any one of claims 2 to 3,
the answering device receiving the third analog signal performs third processing on the third analog signal, and the third processing at least comprises:
and the response device demodulates the third analog signal to generate a third digital signal, generates the first digital signal according to the third digital signal response, and performs second modulation on the first digital signal to generate a first analog signal, wherein the modulation mode of the first modulation is the same as that of the second modulation.
5. A circuit delay self-test apparatus, the apparatus comprising:
the receiving module is used for receiving a first analog signal;
the first processing module is used for performing first processing on the first analog signal to generate a first digital signal;
the digital signal acquisition module is used for acquiring the first digital signal;
the second processing module is used for carrying out second processing on the first digital signal to generate a second analog signal;
a sending module, configured to send the second analog signal;
the receiving module is further configured to receive the second analog signal;
the first processing module is further configured to perform first processing on the second analog signal to generate a second digital signal, where the second digital signal is the same as the first digital signal;
the digital signal acquisition module is further configured to acquire the second digital signal;
a processing time obtaining module, configured to obtain a first processing time T1, where the first processing time T1 is a difference between a time when the second digital signal is obtained and a time when the second analog signal is sent;
a determining module, configured to determine that a circuit delay of the first processing module is the first processing time T1;
wherein the first processing module at least comprises: a demodulation module; the demodulation module is used for demodulating the first analog signal to generate a first digital signal; the demodulation module is further configured to demodulate the second analog signal to generate a second digital signal; the second processing module is configured to perform second processing on the first digital signal to generate a second analog signal, and includes: the first digital signal is first modulated to generate a second analog signal.
6. The apparatus of claim 5,
the sending module is further configured to send a third analog signal to the outside, where the first analog signal received by the receiving module is generated after the third analog signal is subjected to third processing by the response device that receives the third analog signal.
7. The apparatus of claim 6, further comprising: a calculation module and a judgment module;
the processing time obtaining module is further configured to obtain a second processing time T2, where the second processing time T2 is a difference between a time when the first digital signal is obtained and a time when a third analog signal is sent outwards;
the calculation module is used for calculating a time difference value between the second processing time T2 and the first processing time T1;
the judging module is used for judging whether the time difference value is smaller than a preset value or not;
and the determining module is further used for determining that the communication data between the circuit delay self-detection device and the answering device is not hijacked when the time difference value is judged to be smaller than the preset value.
8. A circuit delay self-detection system is characterized in that,
the system comprises the circuit delay self-detection device of claim 7 and a response device;
the response device is further configured to receive the third analog signal, and perform third processing on the third analog signal to generate a first analog signal;
the response device is used for sending the first analog signal to the circuit delay self-detection device;
the answering device is further configured to obtain a third processing time T3, where the third processing time T3 is a difference between a time when the answering device sends the first analog signal to the circuit delay self-detection device and a time when the answering device receives the third analog signal;
the preset value is greater than the third processing time T3.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610977256.7A CN107359946B (en) | 2016-11-07 | 2016-11-07 | Circuit delay self-detection method, device and system |
| EP17867642.5A EP3537631B1 (en) | 2016-11-07 | 2017-09-01 | Circuit delay self-measurement method, device, and system |
| US16/346,530 US10659180B2 (en) | 2016-11-07 | 2017-09-01 | Circuit delay self-measurement method, device and system |
| PCT/CN2017/100212 WO2018082391A1 (en) | 2016-11-07 | 2017-09-01 | Circuit delay self-measurement method, device, and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610977256.7A CN107359946B (en) | 2016-11-07 | 2016-11-07 | Circuit delay self-detection method, device and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107359946A CN107359946A (en) | 2017-11-17 |
| CN107359946B true CN107359946B (en) | 2020-09-15 |
Family
ID=60271459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610977256.7A Active CN107359946B (en) | 2016-11-07 | 2016-11-07 | Circuit delay self-detection method, device and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107359946B (en) |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06244881A (en) * | 1993-02-16 | 1994-09-02 | N T T Idou Tsuushinmou Kk | Line quality measuring instrument |
| US6961541B2 (en) * | 2002-05-24 | 2005-11-01 | Aeroscout, Inc. | Method and apparatus for enhancing security in a wireless network using distance measurement techniques |
| DE10255880A1 (en) * | 2002-11-29 | 2004-06-09 | Philips Intellectual Property & Standards Gmbh | Electronic communication system and method for detecting a relay attack on the same |
| CN101251575A (en) * | 2008-03-28 | 2008-08-27 | 湖南大学 | Switching current circuit test device and method based on pseudo-random signal invigoration |
| DE102011081689B4 (en) * | 2011-08-26 | 2020-07-02 | Intel Deutschland Gmbh | SIGNAL PROCESSING DEVICE AND METHOD FOR PROVIDING A FIRST ANALOG SIGNAL AND A SECOND ANALOG SIGNAL |
| CN104660330A (en) * | 2014-12-31 | 2015-05-27 | 武汉盛华微系统技术股份有限公司 | Optical fiber access timing device with time delay measurement system |
| CN105307172B (en) * | 2015-11-13 | 2018-11-23 | 四川虹信软件有限公司 | Bluetooth base. station legality identification method based on dynamic time |
| CN105610434B (en) * | 2016-02-26 | 2018-08-10 | 西安紫光国芯半导体有限公司 | A kind of adaptive delay phase-locked loop |
-
2016
- 2016-11-07 CN CN201610977256.7A patent/CN107359946B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN107359946A (en) | 2017-11-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101531006B1 (en) | Detecting a communication tap via signal monitoring | |
| US8693949B2 (en) | Near-field RF communicators having a low-energy pre-polling process | |
| WO2018132237A3 (en) | Systems and methods to select or transmitting frequency domain patterns for phase tracking reference signals | |
| US8391905B2 (en) | Mobile communication method and mobile station | |
| CN104202729A (en) | Method, device and system for adding contact persons | |
| CN108199785B (en) | Transmission power testing method, device and system and electronic equipment | |
| CN104244289A (en) | Method and device for identifying pseudo base station | |
| CN107359946B (en) | Circuit delay self-detection method, device and system | |
| CN110662191B (en) | Communication mode selection method and device and electronic equipment | |
| CN107359947B (en) | Circuit time delay self-detection device and system | |
| US20170208430A1 (en) | Car entertainment control system | |
| CN111342866B (en) | Low power mode card detection | |
| US10931519B2 (en) | Configuration of NFC routers for P2P communication | |
| WO2011022894A1 (en) | Method for controlling communication distance and radio frequency reading device | |
| JP2011087212A5 (en) | ||
| CN114828076B (en) | Wireless perception measurement process management method, device, equipment and storage medium | |
| CN108199788B (en) | Transmission power testing method, device and system and electronic equipment | |
| CN108123762B (en) | Transmission power testing method, device and system and electronic equipment | |
| CN108039928B (en) | Received signal strength testing method, device and system and electronic equipment | |
| JP2018179773A5 (en) | ||
| CN107025781B (en) | Data acquisition system and method | |
| US10862719B1 (en) | Method and apparatus for determining data of ASK signal, and wireless power transmitter using the same | |
| US10659180B2 (en) | Circuit delay self-measurement method, device and system | |
| CN110969820B (en) | Measuring device, corresponding method and system | |
| CN109151160B (en) | Communication method, communication device, mobile terminal and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |