CN107357752B - Control interface expansion circuit - Google Patents
Control interface expansion circuit Download PDFInfo
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- CN107357752B CN107357752B CN201710565632.6A CN201710565632A CN107357752B CN 107357752 B CN107357752 B CN 107357752B CN 201710565632 A CN201710565632 A CN 201710565632A CN 107357752 B CN107357752 B CN 107357752B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4081—Live connection to bus, e.g. hot-plugging
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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Abstract
The invention discloses a control interface extension circuit, which is used for electrically connecting a plurality of storage devices and a control circuit, wherein the control circuit comprises a first control pin and a second control pin, and the control interface extension circuit comprises: a memory module, including a plurality of memory areas, each memory area corresponding to one of the plurality of storage devices, each memory area electrically connected to the corresponding at least one storage device through at least one storage output pin; each memory area is provided with a first pin and a second pin, the first pins of the memory areas are electrically connected with the first control pin of the control circuit, and the second pins of the memory areas are electrically connected with the second control pin of the control circuit.
Description
Technical Field
The present invention relates to a control interface expansion circuit, and more particularly, to a control interface expansion circuit capable of connecting a plurality of memory devices.
Background
The server is often used in the environment of data fast storage, so the hardware requirement for high access speed is higher than that of a general computer. Even though the solid-state storage device is more expensive than a general storage device, since the read/write speed of a Non-Volatile Memory express (NVMe) transport Interface is several times higher than that of an Advanced Host Controller Interface (AHCI), many manufacturers gradually introduce the Controller Interface of the Non-Volatile Memory express specification into a server system. However, in the current Intel architecture, in order to support hot plug and light control of the high-speed specification solid-state memory device with non-volatile memory, an expansion IC using an I2C interface is used to decode the I2C signal at the CPU. The expansion IC of an I2C interface can only realize hot plug and lamp control of at most two high-speed specification solid-state storage devices of the nonvolatile memory. To control hot-plug and lamp-number control of a Non-volatile memory (NVMe) solid-state storage device with more nonvolatile memory (Non-volatile memory) specifications, the number of expansion ICs needs to be increased.
Therefore, it is an important subject of the present industry to provide a control interface expansion circuit capable of controlling hot plug and lamp control of two or more non-volatile memory high-speed specification solid-state storage devices.
Disclosure of Invention
The embodiment of the invention discloses a control interface expansion circuit, which is used for electrically connecting a plurality of storage devices and a control circuit, wherein the control circuit comprises a first control pin and a second control pin, and is characterized in that the control interface expansion circuit comprises: a memory module, including a plurality of memory areas, each memory area corresponding to one of the plurality of storage devices, each memory area electrically connected to the corresponding at least one storage device through at least one storage output pin; each memory area is provided with a first pin and a second pin, the first pins of the memory areas are electrically connected with the first control pin of the control circuit, and the second pins of the memory areas are electrically connected with the second control pin of the control circuit.
Preferably, each of the memory areas has a corresponding area address.
Preferably, the control circuit sends at least one control command to control the plurality of storage devices through the plurality of memory areas according to a plurality of the area addresses.
The invention discloses a control interface expansion circuit, which is used for electrically connecting a plurality of storage devices and is characterized by comprising: an interface module, comprising: a first input control pin; a second input control pin; a first output control pin; the first output control pin is electrically connected with the first input control pin, and the second output control pin is electrically connected with the second input control pin; the memory module comprises a plurality of memory areas, each memory area corresponds to one of the plurality of storage devices, and each memory area is electrically connected with at least one corresponding storage device through at least one storage output pin; the memory module comprises a first memory area, the first memory area comprises a first pin and a second pin, the first output control pin is electrically connected with the first pin of the first memory area, and the second output control pin is electrically connected with the second pin of the first memory area.
Preferably, the interface module further comprises: a third output control pin; a fourth output control pin; a fifth output control pin; a sixth output control pin; a seventh output control pin; and an eighth output control pin; wherein the memory module further comprises a second memory region, a third memory region and a fourth memory region, the second memory region, the third memory region and the fourth memory region respectively comprise a first pin and a second pin, the third output control pin is electrically connected with the first pin of the second memory area, the fourth output control pin is electrically connected with the second pin of the second memory area, the fifth output control pin is electrically connected to the first pin of the third memory area, the sixth output control pin is electrically connected to the second pin of the third memory area, the seventh output control pin is electrically connected to the first pin of the fourth memory area, and the eighth output control pin is electrically connected to the second pin of the fourth memory area.
Preferably, the control interface expansion circuit is electrically connected to a control circuit, the control circuit includes a first control pin and a second control pin, the first control pin of the control circuit is electrically connected to the first input control pin of the interface module, and the second control pin of the control circuit is electrically connected to the second input control pin of the interface module.
Preferably, each of the plurality of memory regions has a corresponding region address.
Preferably, the control circuit sends at least one control command to control the plurality of storage devices through the plurality of memory areas according to a plurality of the area addresses.
In summary, the control interface expansion circuit according to the embodiment of the present invention utilizes a plurality of memory areas and corresponding area addresses thereof as control interfaces of the storage devices, so that the cost is greatly reduced, the number of connected storage devices can be greatly increased, and in addition, the interface modules can be integrated, so as to effectively improve the modularization degree of the control interface expansion circuit, thereby being applicable to different fields.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic diagram of a control interface expansion circuit according to an embodiment of the invention.
Fig. 2 is another schematic diagram of the control interface expansion circuit according to the embodiment of the invention.
FIG. 3 is another schematic diagram of the control interface expansion circuit according to the embodiment of the invention.
Detailed Description
Various exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some exemplary embodiments are shown. The inventive concept may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first component discussed below could be termed a second component without departing from the teachings of the present concepts. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The control interface expansion circuit will be described in at least one embodiment with reference to the drawings, however, the following embodiments are not intended to limit the disclosure.
[ embodiment of the control interface expansion Circuit of the present invention ]
Referring to fig. 1, fig. 1 is a schematic diagram of a control interface expansion circuit according to an embodiment of the invention.
In the present embodiment, the control interface expansion circuit 2 is electrically connected to a control circuit 1, a first storage device 3, a second storage device 4, a third storage device 5 and a fourth storage device 6. In the present embodiment, the control circuit 1 is disposed on a motherboard (not shown) of a server system (not shown), and the control interface expansion circuit 2 is disposed on a backplane (not shown) of the server system (not shown).
The control circuit 1 includes a control module 11 including a first control pin C1 and a second control pin C2. The control interface expansion circuit 2 includes at least one memory module 20. The memory module 20 includes a plurality of memory areas, and in the present embodiment, the memory module 20 includes a first memory area 21, a second memory area 22, a third memory area 23, and a fourth memory area 24. In the present embodiment, the first memory region 21, the second memory region 22, the third memory region 23 and the fourth memory region 24 have different region addresses, and each memory region has a first pin P1 and a second pin P2. In the present embodiment, the control module 11 is a Central Processing Unit (CPU). The plurality of memory regions 21-24 of the memory module 20 may be independent memories, or may be different regions located in the same memory, and the number and design manner thereof are not limited in the present invention.
That is, the control circuit 1 can perform sending of the control command and receiving of the query result through the first pin C1, the second pin C2, and the first pin P1 and the second pin P2 of the first memory area 21, the second memory area 22, the third memory area 23, and the fourth memory area 24 according to different address codes to query or obtain the status information of the first storage device 3, the second storage device 4, the third storage device 5, and the fourth storage device 6 to determine whether the first storage device 3, the second storage device 4, the third storage device 5, and the fourth storage device 6 are powered off, removed, or normally operating currently.
In addition, the first memory region 21, the second memory region 22, the third memory region 23 and the fourth memory region 24 respectively include a first storage output pin S1, a second storage output pin S2, a third storage output pin S3 and a fourth storage output pin S4. Further, the first memory area 21 of the memory module 20 is electrically connected to the first storage device 3 through the first storage output pin S1. The second memory region 22 is electrically connected to the second memory device 4 through a second memory output pin S2. The third memory area 23 is electrically connected to the third memory device 5 through a third memory output pin S3. The fourth memory region 24 is electrically connected to the fourth memory device 6' through a fourth memory output pin S4. That is, the control module 1 can perform the sending of the control command and the receiving of the query result with the first storage device 3, the second storage device 4, the third storage device 5 and the fourth storage device 6 through the first pin P1 and the second pin P2, the first storage output pin S1, the second storage output pin S2, the third storage output pin S3 and the fourth storage output pin S4 of each memory area of the memory module 20.
In the present embodiment, the first STORAGE device 3, the second STORAGE device 4, the third STORAGE device 5, and the fourth STORAGE device 6 are each a Solid State STORAGE (Solid State STORAGE).
In the present embodiment, the status information of the first storage device 3, the second storage device 4, the third storage device 5 and the fourth storage device 6 can be temporarily stored in the first memory area 21, the second memory area 22, the third memory area 23 and the fourth memory area 24, respectively.
In the embodiment, the first control pin C1 of the control module 11 is electrically connected to the first pin P1 of the first memory region 21, the first pin P1 of the second memory region 22, the first pin P1 of the third memory region 23, and the first pin P1 of the fourth memory region 24. The second control pin C2 of the control module 11 is electrically connected to the second pin P2 of the first memory region 21, the second pin P2 of the second memory region 22, the second pin P2 of the third memory region 23, and the second pin P2 of the fourth memory region 24.
In this embodiment, the control module 11 of the control circuit 1 may send at least one control command to the first storage device 3, the second storage device 4, the third storage device 5, and the fourth storage device 6 according to a communication protocol and a corresponding area address of each memory area, so as to control the first storage device 3, the second storage device 4, the third storage device 5, and the fourth storage device 6. In this embodiment, the control instruction may be: the query instruction for querying the status information of the first storage device 3 may be designed and adjusted according to actual requirements, and is not limited in the present invention.
In the present embodiment, the number of the memory areas included in the memory module 20 is four, and correspondingly, the number of the storage devices that can be connected to the control interface expansion circuit 2 is also four. In other embodiments, the number of the memory areas in the control interface expansion circuit 2 may be adjusted according to actual requirements, which is not limited in the present invention. That is, the number of storage devices that can be connected to the control interface expansion circuit 2 is determined by the number of memory regions of the memory module 20.
[ Another embodiment of the control interface expansion circuit of the present invention ]
Referring to fig. 2, fig. 2 is another schematic diagram of a control interface expansion circuit according to an embodiment of the invention.
In the present embodiment, the control interface expansion circuit 2 'is electrically connected to a control circuit 1', a first storage device 3 ', a second storage device 4', a third storage device 5 'and a fourth storage device 6'. In this embodiment, the control circuit 1 'is disposed on a motherboard (not shown) of a server system (not shown), and the control interface expansion circuit 2' is disposed on a backplane (not shown) of the server system (not shown).
The control circuit 1 'includes a control module 11' including a first control pin C1 and a second control pin C2.
The control interface expansion circuit 2 ' includes a memory module 20 ' and an interface module 40 '. In this embodiment, the memory module 20 ' includes a first memory area 21 ', a second memory area 22 ', a third memory area 23 ', and a fourth memory area 24 '. In the embodiment, the first memory region 21 ', the second memory region 22', the third memory region 23 'and the fourth memory region 24' have different addresses, and each memory region has a first pin P1 and a second pin P2. In the present embodiment, the control module 11' is a central processing unit. The plurality of memory regions 21 ' -24 ' of the memory module 20 ' may be independent memories, or may be different regions located in the same memory, and the number and design manner thereof are not limited in the present invention.
That is, the control circuit 1 ' may transmit the control command and receive the query result through the first control pin C1, the second control pin C2, the first memory region 21 ', the second memory region 22 ', the third memory region 23 ', and the fourth memory region 24 ' according to different address codes via the first pin P1 and the second pin P2, respectively.
In addition, the first memory region 21 ', the second memory region 22', the third memory region 23 'and the fourth memory region 24' further include a first storage output pin S1, a second storage output pin S2, a third storage output pin S3 and a fourth storage output pin S4, respectively. Further, the first memory region 21 ' of the memory module 20 ' is electrically connected to the first memory device 3 ' through the first memory output pin S1. The second memory region 22 'is electrically connected to the second memory device 4' through a second memory output pin S2. The third memory region 23 'is electrically connected to the third memory device 5' through a third memory output pin S3. The fourth memory area 24' is electrically connected to the fourth memory device 6 through a fourth memory output pin S4. That is, the control module 1 'may perform the sending of the control command and the receiving of the query result with the first storage device 3', the second storage device 4 ', the third storage device 5' and the fourth storage device 6 'through the first pin P1 and the second pin P2, the first storage output pin S1, the second storage output pin S2, the third storage output pin S3 and the fourth storage output pin S4 of each memory region of the memory module 2'.
In the present embodiment, the status information of the first storage device 3 ', the second storage device 4', the third storage device 5 'and the fourth storage device 6' can be temporarily stored in the first memory area 21 ', the second memory area 22', the third memory area 23 'and the fourth memory area 24', respectively.
In the embodiment, the first control pin C1 and the second control pin C2 of the control module 11 'are electrically connected to the interface module 40'.
The interface module 40' includes a first input control pin IP1, a second input control pin IP2, a first output control pin OP1, a second output control pin OP2, a third output control pin OP3, a fourth output control pin OP4, a fifth output control pin OP5, a sixth output control pin OP6, a seventh output control pin OP7, and an eighth output control pin OP 8.
The first control pin C1 and the second control pin C2 of the control module 11 'are electrically connected to the first input control pin IP1 and the second input control pin IP2 of the interface module 40', respectively.
The first output control pin OP1 and the second output control pin OP2 of the interface module 40 'are electrically connected to the first pin P1 and the second pin P2 of the first memory area 21', respectively. The third output control pin OP3 and the fourth output control pin OP4 of the interface module 40 'are electrically connected to the first pin P1 and the second pin P2 of the second memory region 22', respectively. The fifth output control pin OP5 and the sixth output control pin OP6 of the interface module 40 'are electrically connected to the first pin P1 and the second pin P2 of the third memory region 23', respectively. The seventh output control pin OP7 and the eighth output control pin OP8 of the interface module 40 'are electrically connected to the first pin P1 and the second pin P2 of the fourth memory area 24', respectively.
In this embodiment, the control module 11 'of the control circuit 1' can send at least one control command to the first storage device 3 ', the second storage device 4', the third storage device 5 'and the fourth storage device 6' according to a communication protocol and the corresponding area address of each memory area 21 '-24' to control the first storage device 3 ', the second storage device 4', the third storage device 5 'and the fourth storage device 6'.
In the present embodiment, the first storage device 3 ', the second storage device 4', the third storage device 5 'and the fourth storage device 6' are solid-state storage devices of a nonvolatile memory controller interface, respectively.
In the present embodiment, the number of the memory areas included in the memory module 20 'is four, and correspondingly, the number of the storage devices that can be connected to the control interface expansion circuit 2' is also four. In other embodiments, the number of the memory areas in the control interface expansion circuit 2' may be adjusted according to actual requirements, and is not limited in the present invention. That is, the number of storage devices that can be connected to the control interface expansion circuit 2 'is determined by the number of memory regions of the memory module 20'.
[ Another embodiment of the control interface expansion circuit of the present invention ]
Referring to fig. 3, fig. 3 is another schematic diagram of a control interface expansion circuit according to an embodiment of the invention.
In the present embodiment, the control interface expansion circuit 2 "is electrically connected to a control circuit 1", a first storage device 3 ", a second storage device 4", a third storage device 5 ", a fourth storage device 6", a fifth storage device 7 ", a sixth storage device 8", a seventh storage device 9 ", and an eighth storage device 10". In the present embodiment, the control circuit 1 ″ is disposed on a motherboard (not shown) of a server system (not shown), and the control interface expansion circuit 2' is disposed on a backplane (not shown) of the server system (not shown).
The control circuit 1 "includes a control module 11" including a first control pin C1 and a second control pin C2.
The control interface expansion circuit 2 "includes a memory module 20" and an interface module 40 ". In this embodiment, the memory module 20 "includes a first memory area 21", a second memory area 22 ", a third memory area 23", and a fourth memory area 24 ". In the embodiment, the first memory area 21 ", the second memory area 22", the third memory area 23 "and the fourth memory area 24" have different addresses, and each memory area has a first pin P1 and a second pin P2. In the present embodiment, the control module 11 ″ is a central processing unit. The plurality of memory areas 21 "-24" of the memory module 20 "may be independent memories, or may be different areas located in the same memory, and the number and design manner thereof are not limited in the present invention.
That is, the control circuit 1 ″ can perform the sending of the control command and the receiving of the query result through the first pin P1 and the second pin P2 of the first control pin C1, the second control pin C2, and the first memory region 21 ", the second memory region 22", the third memory region 23 ", and the fourth memory region 24", respectively, according to different address codes.
In addition, the first memory region 21 ", the second memory region 22", the third memory region 23 "and the fourth memory region 24" respectively include a first storage output pin S1, a second storage output pin S2, a third storage output pin S3, a fourth storage output pin S4, a fifth storage output pin S5, a sixth storage output pin S6, a seventh storage output pin S7 and an eighth storage output pin S8. In particular, the first memory region 21 "of the memory module 20" is electrically connected to the first storage device 3 "and the second storage device 4" through the first storage output pin S1 and the second storage output pin S2, respectively. The second memory region 22 "is electrically connected to the third storage device 5" and the fourth storage device 6 "through the third storage output pin S3 and the fourth storage output pin S4, respectively. The third memory region 23 "is electrically connected to the fifth storage device 7" and the sixth storage device 8 "through the fifth storage output pin S5 and the sixth storage output pin S6, respectively. The fourth memory region 24 "is electrically connected to the seventh memory device 9" and the eighth memory device 10 "respectively through the seventh memory output pin S7 and the eighth memory output pin S8. That is, the control module 1 "may perform the sending of the control command and the receiving of the query result with the first storage device 3", the second storage device 4 ", the third storage device 5", the fourth storage device 6 ", the fifth storage device 7", the sixth storage device 8 ", the seventh storage device 9" and the eighth storage device 10 "respectively through the first pin P1 and the second pin P2, the first storage output pin S1, the second storage output pin S2, the third storage output pin S3, the fourth storage output pin S4, the fifth storage output pin S5, the sixth storage output pin S6, the seventh storage output pin S7 and the eighth storage output pin S8 of each memory region of the memory module 2". In this embodiment, each memory area may be connected to two storage devices, and in other embodiments, each memory area may be connected to three or more storage devices, which is not limited in the present invention.
In this embodiment, the status information of the first storage means 3 ", the second storage means 4" may be temporarily stored in the first memory area 21 ". While the status information of the third storage means 5 ", the fourth storage means 6" may be temporarily stored in the second memory area 22 ". The status information of the fifth storage device 7 "and the sixth storage device 8" may be temporarily stored in the third memory area 23 ", respectively. The status information of the seventh memory means 9 "and the eighth memory means 10" may be temporarily stored in the fourth memory area 24 ".
In the embodiment, the first control pin C1 and the second control pin C2 of the control module 11 ″ are electrically connected to the interface module 40 ″.
The interface module 40 ″ includes a first input control pin IP1, a second input control pin IP2, a first output control pin OP1, a second output control pin OP2, a third output control pin OP3, a fourth output control pin OP4, a fifth output control pin OP5, a sixth output control pin OP6, a seventh output control pin OP7, and an eighth output control pin OP 8.
The first control pin C1 and the second control pin C2 of the control module 11 "are electrically connected to the first input control pin IP1 and the second input control pin IP2 of the interface module 40", respectively.
The first output control pin OP1 and the second output control pin OP2 of the interface module 40 ″ are electrically connected to the first pin P1 and the second pin P2 of the first memory area 21 ″ respectively. The third output control pin OP3 and the fourth output control pin OP4 of the interface module 40 ″ are electrically connected to the first pin P1 and the second pin P2 of the second memory region 22 ", respectively. The fifth output control pin OP5 and the sixth output control pin OP6 of the interface module 40 "are electrically connected to the first pin P1 and the second pin P2 of the third memory region 23", respectively. The seventh output control pin OP7 and the eighth output control pin OP8 of the interface module 40 ″ are electrically connected to the first pin P1 and the second pin P2 of the fourth memory area 24 ″ respectively.
In this embodiment, the control module 11 "of the control circuit 1" may send at least one control command to the first storage device 3 ", the second storage device 4", the third storage device 5 ", the fourth storage device 6", the fifth storage device 7 ", the sixth storage device 8", the seventh storage device 9 "and the eighth storage device 10" according to a communication protocol and corresponding area addresses of the respective memory areas 21 "-24" to control the first storage device 3 ", the second storage device 4", the third storage device 5 ", the fourth storage device 6", the fifth storage device 7 ", the sixth storage device 8", the seventh storage device 9 "and the eighth storage device 10".
In the present embodiment, the first storage device 3 ", the second storage device 4", the third storage device 5 ", the fourth storage device 6", the fifth storage device 7 ", the sixth storage device 8", the seventh storage device 9 ", and the eighth storage device 10" are solid-state storage devices of a nonvolatile memory controller interface, respectively.
In the present embodiment, the number of the memory areas included in the memory module 20 ″ is four, and the number of the storage devices that can be connected to the control interface expansion circuit 2 ″ is eight. In other embodiments, the number of the memory areas in the control interface expansion circuit 2 ″ may be adjusted according to actual requirements, and is not limited in the present invention. That is, the number of storage devices that can be connected to the control interface expansion circuit 2 "is determined by the number of memory regions of the memory module 20".
[ possible technical effects of the embodiment ]
In summary, the control interface expansion circuit according to the embodiment of the present invention utilizes a plurality of memory areas and corresponding area addresses thereof as control interfaces of the storage devices, so that the cost is greatly reduced, the number of connected storage devices can be greatly increased, and in addition, the interface modules can be integrated, so as to effectively improve the modularization degree of the control interface expansion circuit, thereby being applicable to different fields.
The above description is only an example of the present invention, and is not intended to limit the scope of the present invention.
Claims (4)
1. A control interface extension circuit for electrically connecting a plurality of memory devices and a control circuit, wherein the control circuit includes a first control pin and a second control pin, the control interface extension circuit comprising:
a memory module, including a plurality of memory areas, each memory area having a corresponding area address, each memory area corresponding to one of the plurality of storage devices, each memory area electrically connected to a corresponding at least one storage device through at least one storage output pin;
each memory area is provided with a first pin and a second pin, the first pins of the memory areas are electrically connected with the first control pin of the control circuit, the second pins of the memory areas are electrically connected with the second control pin of the control circuit, and the control circuit sends at least one control instruction to control the storage devices through the memory areas according to the area addresses.
2. A control interface expansion circuit for electrically connecting a plurality of memory devices, the control interface expansion circuit comprising:
an interface module, comprising:
a first input control pin;
a second input control pin;
a first output control pin; and
a second output control pin, wherein the first output control pin is electrically connected to the first input control pin, and the second output control pin is electrically connected to the second input control pin; and
a memory module, including a plurality of memory areas, each memory area having a corresponding area address, each memory area corresponding to one of the plurality of storage devices, each memory area electrically connected to a corresponding at least one storage device through at least one storage output pin;
the memory module comprises a first memory area, the first memory area comprises a first pin and a second pin, the first output control pin is electrically connected with the first pin of the first memory area, the second output control pin is electrically connected with the second pin of the first memory area, the control interface expansion circuit is electrically connected with a control circuit, and the control circuit sends at least one control instruction to control the plurality of storage devices through the plurality of memory areas according to a plurality of area addresses.
3. The control interface expansion circuit of claim 2, wherein the interface module further comprises:
a third output control pin;
a fourth output control pin;
a fifth output control pin;
a sixth output control pin;
a seventh output control pin; and
an eighth output control pin;
wherein the memory module further comprises a second memory region, a third memory region and a fourth memory region, the second memory region, the third memory region and the fourth memory region respectively comprise a first pin and a second pin, the third output control pin is electrically connected with the first pin of the second memory area, the fourth output control pin is electrically connected with the second pin of the second memory area, the fifth output control pin is electrically connected to the first pin of the third memory area, the sixth output control pin is electrically connected to the second pin of the third memory area, the seventh output control pin is electrically connected to the first pin of the fourth memory area, and the eighth output control pin is electrically connected to the second pin of the fourth memory area.
4. The control interface expansion circuit of claim 2, wherein the control circuit comprises a first control pin and a second control pin, the first control pin of the control circuit is electrically connected to the first input control pin of the interface module, and the second control pin of the control circuit is electrically connected to the second input control pin of the interface module.
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