CN107357205B - A kind of controlled device and chain type control system - Google Patents
A kind of controlled device and chain type control system Download PDFInfo
- Publication number
- CN107357205B CN107357205B CN201710585832.8A CN201710585832A CN107357205B CN 107357205 B CN107357205 B CN 107357205B CN 201710585832 A CN201710585832 A CN 201710585832A CN 107357205 B CN107357205 B CN 107357205B
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- control
- pin
- controlled device
- predetermined level
- address
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/21—Pc I-O input output
- G05B2219/21119—Circuit for signal adaption, voltage level shift, filter noise
Abstract
The embodiment of the invention discloses a kind of chain type control systems, it includes a main control device and multiple controlled devices with main control device series connection, each controlled device receives the address that main control device is sent and generates instruction, and when the first control pin of itself detects the first predetermined level, positive by the amplifier unit of itself disconnects reverse-conducting；The device address that instruction generates and saves itself is generated according to address；The the second control pin of itself is exported into the first predetermined level；The the first control pin of itself is exported into the first predetermined level；The device address of itself is sent respectively to main control device and next controlled device；When the second control pin of itself detects the first predetermined level, positive by the amplifier unit of itself disconnects reverse-conducting.In chain type control system proposed by the present invention, the quantity of controlled device is unrestricted, and address generating process is simple and efficient low to the processing requirement of chip, and the signal of main control device will not decay.
Description
Technical field
The present invention relates to electronic information technical field more particularly to a kind of controlled device and chain type control systems.
Background technique
With the rise of technology of Internet of things, number of devices that is more and more important, and needing to control is required for equipment control
It measures more and more.Existing apparatus control system is usually that a control equipment controls the either control of a controlled device
Equipment controls multiple controlled devices.The control system that one control equipment controls a controlled device is very common, the disadvantage is that control
Range processed is small, inefficiency.Although the control system control range that a control equipment controls multiple controlled devices is big, exist
Following problems:
(1) controlled device Limited Number: it is limited to control the interface number of equipment, the controlled device that control equipment can control
Number it is limited.
(2) address configuration process of controlled device is complex: being all to pass through number of addresses by control equipment under normal conditions
Address date is sent to controlled device according to line, and then controlled device intercepts corresponding address from the data flow that control equipment is sent
Data simultaneously decode the address date of interception, finally according to decoded address date generating device address, such device address
Generating mode not only requires height to the MCU of controlled device, but also process is complicated.
(3) signal loss problem: using between controlled device and be connected in parallel, the line loss of data when data line is too long
Can it is very big, it is difficult to ensure that the integrality of data, in some instances it may even be possible to can there is a phenomenon where loss of data, in addition to this, transmission side data
To single, the application environment of equipment is significantly limited.
As it can be seen that how improving the quantity for the controlled device that control equipment can control, reducing controlled device address configuration mistake
The complexity of journey and the line loss for controlling the hardware requirement of MCU and reduction signal transmission between equipment and controlled device
The technical problem urgently to be resolved as those skilled in the art.
Summary of the invention
The technical problem to be solved is that how to solve controlled device Limited Number, quilt in control system for the embodiment of the present invention
The problem of address configuration process of control equipment is complex and transmits loss of signal.
In a first aspect, the embodiment of the present invention provides a kind of controlled device comprising the first data pin, the second data are drawn
Foot, first control pin, second control pin, amplifier unit and control chip, the amplifier unit respectively with it is described
First data pin, second data pin and control chip connection, the control chip is respectively with described first
Data pin, second data pin, the first control pin and the second control pin connection, first control
Pin processed is used to connect with the second control pin of higher level equipment and is predisposed to the second predetermined level, or is predisposed to first and presets
Level, the second control pin are used to connect with the first control pin of subordinate equipment and are predisposed to the described second default electricity
It is flat, or it is predisposed to first predetermined level, first data pin is used to draw with the second data of the higher level equipment
Foot connection, or connect with the data pin of main control device, second data pin is for first with the subordinate equipment
Data pin connection, the control chip are used for:
Instruction is generated receiving the address that the main control device is sent, and first in the controlled device controls pin
When detecting first predetermined level, positive by the amplifier unit disconnects reverse-conducting；It is generated according to the address
Instruction generates and saves the device address of the controlled device；Second control pin of the controlled device is adjusted to control shape
State simultaneously exports first predetermined level；First control pin of the controlled device is adjusted to described in state of a control and output
First predetermined level；The device address of the controlled device is sent respectively to the main control device and the subordinate equipment；
Second control pin of the controlled device is adjusted to detecting state, and in the second control pin detection of the controlled device
When to second predetermined level, the forward conduction of the amplifier unit is reversely disconnected, the second of the controlled device
When control pin detects first predetermined level, positive by the amplifier unit disconnects reverse-conducting；
Wherein, the forward direction of the amplifier unit is from first data pin to the signal of second data pin
Transmission direction；Being reversed for the amplifier unit is transmitted from second data pin to the signal of first data pin
Direction；The higher level equipment is another controlled device, and the subordinate equipment is another controlled device.
Its further technical solution is that the amplifier unit includes the first controllable amplifier and the second controllable amplification
Device, in which:
The input interface of first controllable amplifier is connect with first data pin, first controllable amplifier
Output interface connect with second data pin, the control interface of first controllable amplifier and the control chip company
It connects；
The input interface of second controllable amplifier is connect with second data pin, second controllable amplifier
Output interface connect with first data pin, the control interface of second controllable amplifier and the control chip company
It connects.
Its further technical solution is that the control chip includes that judging unit, Logical processing unit and address are raw
At output unit, in which:
The judging unit is used for when receiving the control instruction of the main control device, whether judges the control instruction
It generates and instructs for the address；
If it is the address that the Logical processing unit, which is the control instruction for the judging result of the judging unit,
Instruction is generated, and when the first control pin of the controlled device detects first predetermined level, it can by described first
It controls amplifier to disconnect, the second controllable amplifier conducting；And the second control pin of the controlled device is adjusted to control
State processed simultaneously exports first predetermined level；First control pin of the controlled device is adjusted to state of a control and is exported
First predetermined level；Second control pin of the controlled device is adjusted to detecting state, and in the controlled device
The second control pin when detecting second predetermined level, first controllable amplifier is connected, described second controllably
Amplifier disconnects, can by described first when the second control pin of the controlled device detects first predetermined level
It controls amplifier to disconnect, the second controllable amplifier conducting；
The address generates output unit and is used to be the control instruction in the judging result of the judging unit to be described
Address generates instruction, and when the first control pin of the controlled device detects first predetermined level, according to described
Address generates the device address that instruction generates and saves the controlled device；And it described will be controlled in the Logical processing unit
Second control pin of equipment is adjusted to state of a control and exports first predetermined level, by the first control of the controlled device
After pin processed is adjusted to state of a control and exports first predetermined level, the device address of the controlled device is sent respectively
To the main control device and the subordinate equipment.
Its further technical solution is that the control chip is also used to:
When the second control pin of the controlled device detects second predetermined level, by the controlled device
First control pin is adjusted to detecting state, so that the second control pin of the higher level equipment detects the described second default electricity
It is flat.
Its further technical solution is that the control chip is single-chip microcontroller, first data pin and the monolithic
One data-interface of machine connects, and second data pin is connect with another data-interface of the single-chip microcontroller, first control
Pin processed is connect with an I/O interface of the single-chip microcontroller, and another I/O interface of the second control pin and the single-chip microcontroller connects
It connects.
Second aspect, the embodiment of the present invention provide a kind of chain type control system comprising a main control device and multiple quilts
Equipment is controlled, each controlled device draws including the first data pin, the second data pin, the first control pin, the second control
Foot, amplifier unit and control chip, the amplifier unit draw with first data pin, second data respectively
Foot and the control chip connection, the control chip respectively with first data pin, second data pin, institute
State the first control pin and the second control pin connection, wherein the first data pin of first controlled device and institute
The data pin connection of main control device is stated, the first control pin of first controlled device is predisposed to the first predetermined level,
And the of the second data pin of previous controlled device and the latter controlled device since first controlled device
The connection of one data pin, the second control pin of previous controlled device are connect with the first control pin of the latter controlled device
And be predisposed to the second predetermined level, and so on be connected to the last one controlled device step by step, it is described that the last one is controlled
Second control pin of equipment is predisposed to first predetermined level, in which:
Each controlled device is used to generate instruction receiving the address that the main control device is sent, and itself the
When one control pin detects first predetermined level, positive by the amplifier unit of itself disconnects reverse-conducting；According to
The address generates the device address that instruction generates and saves itself；The the second control pin of itself is adjusted to state of a control simultaneously
Export first predetermined level；The the first control pin of itself is adjusted to state of a control and exports the described first default electricity
It is flat；The device address of itself is sent respectively to the main control device and next controlled device；By the second control of itself
Pin is adjusted to detecting state, and when the second control pin of itself detects second predetermined level, by putting for itself
The forward conduction of big device unit reversely disconnects, will be certainly when the second control pin of itself detects first predetermined level
The positive of the amplifier unit of body disconnects reverse-conducting；
The forward direction of the amplifier unit is to transmit from first data pin to the signal of second data pin
Direction；The signal transmission side of the amplifier unit being reversed from second data pin to first data pin
To.
Its further technical solution is that the amplifier unit includes the first controllable amplifier and the second controllable amplification
Device, in which:
The input interface of first controllable amplifier is connect with first data pin, first controllable amplifier
Output interface connect with second data pin, the control interface of first controllable amplifier and the control chip company
It connects；
The input interface of second controllable amplifier is connect with second data pin, second controllable amplifier
Output interface connect with first data pin, the control interface of second controllable amplifier and the control chip company
It connects.
Its further technical solution is that the control chip includes that judging unit, Logical processing unit and address are raw
At output unit, in which:
The judging unit is used for when receiving the control instruction of the main control device, whether judges the control instruction
It generates and instructs for the address；
The Logical processing unit is used to be the control instruction in the judging result of the judging unit to be the address
Instruction is generated, and when the first control pin of the controlled device detects first predetermined level, it can by described first
It controls amplifier to disconnect, the second controllable amplifier conducting；And the second control pin of the controlled device is adjusted to control
State processed simultaneously exports first predetermined level；First control pin of the controlled device is adjusted to state of a control and is exported
First predetermined level；Second control pin of the controlled device is adjusted to detecting state, and in the controlled device
The second control pin when detecting second predetermined level, first controllable amplifier is connected, described second controllably
Amplifier disconnects, can by described first when the second control pin of the controlled device detects first predetermined level
It controls amplifier to disconnect, the second controllable amplifier conducting；
The address generates output unit and is used to be the control signal in the judging result of the judging unit to be described
Address generates instruction, and when the first control pin of the controlled device detects first predetermined level, according to described
Address generates the device address that instruction generates and saves the controlled device；And it described will be controlled in the Logical processing unit
Second control pin of equipment is adjusted to state of a control and exports first predetermined level, by the first control of the controlled device
After pin processed is adjusted to state of a control and exports first predetermined level, the device address of the controlled device is sent respectively
To the main control device and next controlled device.
Its further technical solution is that the last one described controlled device is also used to its device address being sent to master
After controlling equipment, the first control pin of itself is adjusted to detecting state, so that the second control of a controlled device is drawn thereon
Foot detects second predetermined level；
Other controlled devices other than the last one described controlled device are also used to the second control pin detection at itself
When to second predetermined level, the first control pin of itself is adjusted to detecting state, so that a controlled device thereon
Second control pin detect second predetermined level.
Its further technical solution is that the control chip is single-chip microcontroller, first data pin and the monolithic
One data-interface of machine connects, and second data pin is connect with another data-interface of the single-chip microcontroller, first control
Pin processed is connect with an I/O interface of the single-chip microcontroller, and another I/O interface of the second control pin and the single-chip microcontroller connects
It connects.
By applying the technical scheme of the present invention, chain type is connected between main control device and controlled device, the number of controlled device
Amount is not limited by master control equipment interface number, and the quantity of controlled device can be expanded arbitrarily；Controlled device controls pin according to it
The potential change detected, Lai Zidong generating device address, address generating process are simple and efficient and low to the processing requirement of chip；
Each controlled device includes that amplifier unit ensure that the signal from main control device will not decay in transmission process.
Detailed description of the invention
Technical solution in order to illustrate the embodiments of the present invention more clearly, below will be to needed in embodiment description
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, general for this field
For logical technical staff, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is a kind of schematic block diagram of controlled device provided in an embodiment of the present invention；
The schematic flow diagram for the address configuration process that Fig. 2 controlled device shown in Fig. 1 is realized；
Fig. 3 is the schematic block diagram of amplifier unit in Fig. 1；
Fig. 4 be another embodiment of the present invention provides a kind of controlled device schematic block diagram；
Fig. 5 is the schematic block diagram that chip is controlled in Fig. 1；
Fig. 6 is a kind of schematic block diagram of chain type control system provided in an embodiment of the present invention；And
The schematic flow diagram of Fig. 7 address configuration process that chain type control system is realized shown in Fig. 5.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, is clearly and completely retouched to the technical solution in embodiment
It states, similar reference numerals represent similar component in attached drawing.Obviously, will be described below embodiment is only the present invention one
Divide embodiment, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not making
Every other embodiment obtained, shall fall within the protection scope of the present invention under the premise of creative work.
It should be appreciated that ought use in this specification and in the appended claims, term " includes " and "comprising" instruction
Described feature, entirety, step, operation, the presence of element and/or component, but one or more of the other feature, whole is not precluded
Body, step, operation, the presence or addition of element, component and/or its set.
It is also understood that mesh of the term used in this description of the invention merely for the sake of description specific embodiment
And be not intended to limit the present invention.As description of the invention and it is used in the attached claims, unless on
Other situations are hereafter clearly indicated, otherwise " one " of singular, "one" and "the" are intended to include plural form.
It will be further appreciated that the term "and/or" used in description of the invention and the appended claims is
Refer to any combination and all possible combinations of one or more of associated item listed, and including these combinations.
As used in this specification and in the appended claims, term " if " can be according to context quilt
Be construed to " when ... " or " once " or " in response to determination " or " in response to detecting ".Similarly, phrase " if it is determined that " or
" if detecting [described condition or event] " can be interpreted to mean according to context " once it is determined that " or " in response to true
It is fixed " or " once detecting [described condition or event] " or " in response to detecting [described condition or event] ".
Fig. 1 is please referred to, is a kind of schematic block diagram of controlled device 10 provided in an embodiment of the present invention, as shown, should
Controlled device 10 includes the first data pin 11, the second data pin 12, first control control of pin 13, second pin 14, puts
Big device unit 15 and control chip 16, the amplifier unit 15 are counted with first data pin 11, described second respectively
Connected according to pin 12 and the control chip 16, the control chip 16 respectively with first data pin 11, described the
Two data pins 12, the first control pin 13 and the second control pin 14 connect, the first control pin 13
It is connect and is predisposed to the second predetermined level for controlling pin 14 with the second of higher level equipment, or in other feasible embodiments
Described in the first control pin 13 be predisposed to the first predetermined level, the second control pin 14 is for first with subordinate equipment
Control pin 13 connects and is predisposed to second predetermined level, or the second control pin 14 in other feasible embodiments
It is predisposed to first predetermined level, first data pin 11 is used to connect with the second data pin 12 of the higher level equipment
It connects, or the first data pin 11 described in other feasible embodiments is used to connect with the data pin of main control device, institute
The second data pin 12 is stated for connecting with the first data pin 11 of the subordinate equipment.
Fig. 2 is referred to, the control chip 16 is for executing following steps:
S11 generates instruction receiving the address that the main control device is sent, and in the first control of the controlled device 10
When pin 13 processed detects first predetermined level, positive by the amplifier unit 15 disconnects reverse-conducting.
When the address for receiving main control device transmission generates instruction, if controlled device 10 has higher level equipment, controlled device
10 the first control pin 13 detects the current potential of the second control pin 14 of its higher level equipment as detection foot, if detecting first
Predetermined level, then the positive of its amplifier unit 15 is disconnected reverse-conducting by controlled device 10.If controlled device 10 does not have higher level
Equipment, controlled device 10 are first controlled device 10, and the first control pin 13 is predisposed to the first predetermined level, therefore quilt
First control pin 13 of control equipment 10 will detect that the first predetermined level as detection foot detection, and controlled device 10 will at this time
The positive of its amplifier unit 15 disconnects reverse-conducting.
It should be noted that the forward direction of the amplifier unit 15 is from first data pin 11 to second number
According to the signal transmission direction of pin 12；The amplifier unit 15 is reversed from second data pin 12 to described first
The signal transmission direction of data pin 11.Amplifier unit 15 is transmitted further to subordinate equipment after capable of amplifying signal, to protect
The intensity of signal is demonstrate,proved.
In addition, higher level equipment is another controlled device 10, subordinate equipment is another controlled device 10.
S12 generates the device address that instruction generates and saves the controlled device 10 according to the address.
After the positive disconnection reverse-conducting by the amplifier unit 15, control chip 16 will be raw according to the address
The device address of the controlled device 10 is generated and saved at instruction.
It should be noted that if controlled device 10 is first controlled device, address is preset by main control device, therefore its
Parsing in instruction, which is generated, from address acquires device address；If controlled device 10 is not first controlled device, equipment
Location is generated according to the device address of its higher level equipment, to guarantee that the device address between the superior and the subordinate's equipment is continuous.
Second control pin 14 of the controlled device 10 is adjusted to state of a control and exports described first to preset by S13
First control pin 13 of the controlled device 10 is adjusted to state of a control and exports first predetermined level by level.
Second control pin 14 of controlled device 10 is adjusted to state of a control and exports described first in advance by control chip 16
If level, so that the first control pin 13 of subordinate equipment detects the first predetermined level and triggers generating device address, and
The device address that subordinate equipment generates is what the device address based on its higher level equipment generated, to guarantee the superior and the subordinate's equipment room address
It is continuous.First control pin 13 of controlled device 10 is adjusted to state of a control and exports described first to preset by control chip 16
Level, so that the second control pin 14 of higher level equipment detects the first predetermined level.
It should be noted that control chip 16 will be constantly by the first of controlled device 10 after generating device address
Control pin 13 is adjusted to state of a control and exports first predetermined level, so that the second control pin of its higher level equipment
14 are continuously detected the first predetermined level and keep its amplifier unit 15 is positive to disconnect reverse-conducting.The purpose for the arrangement is that being
Allow the device address of subsequent subordinate equipment can be successfully transmitted to main control device.
The device address of the controlled device 10 is sent respectively to the main control device and the subordinate equipment by S14.
The device address of controlled device 10 is sent to the main control device and subordinate equipment respectively by control chip 16, and one
Aspect feeds back its device address to main control device, so that the address of main control device confirmation controlled device 10 generates successfully, another party
Face can allow subordinate equipment to automatically generate device address on the basis of its device address, so that the address between the superior and the subordinate's equipment
Continuously.
Second control pin 14 of the controlled device 10 is adjusted to detecting state by S15, and in the controlled device 10
The second control pin 14 when detecting second predetermined level, the forward conduction of the amplifier unit 15 is reversely broken
It opens, when the second control pin 14 of the controlled device 10 detects first predetermined level, by the amplifier unit
15 positive disconnection reverse-conducting.
It should be noted that controlling chip 16 for controlled device after the device address to controlled device 10 is sent
10 the second control pin 14 is adjusted to detecting state, if controlled device 10 has subordinate equipment, the second control pin 14 will be examined
Second predetermined level (because the second control pin 14 is predisposed to the second predetermined level) is measured, control chip 16 is set controlled
The forward conduction of standby 10 amplifier unit 15 reversely disconnects.The second control pin 14 of controlled device 10 is as detection foot later
The current potential of the first control pin 13 of its subordinate equipment is detected, if detecting the first predetermined level, controlling chip 16 will be controlled
The positive of the amplifier unit 15 of equipment 10 disconnects reverse-conducting.If controlled device 10 does not have subordinate equipment, controlled device 10 is
The last one controlled device 10, the second control pin 14 are predisposed to the first predetermined level, therefore will detect that first is pre-
If level, chip 16 is controlled at this time by the positive of the amplifier unit 15 of controlled device 10 and disconnects reverse-conducting.
Referring to figure 3. and combine Fig. 4, in certain feasible embodiments, such as in the present embodiment, the amplifier unit 15
Including the first controllable amplifier 151 and the second controllable amplifier 152, in which:
The input interface of first controllable amplifier 151 is connect with first data pin 11, and described first is controllable
The output interface of amplifier 151 is connect with second data pin 12, the control interface of first controllable amplifier 151 with
The control chip 16 connects；
The input interface of second controllable amplifier 152 is connect with second data pin 12, and described second is controllable
The output interface of amplifier 152 is connect with first data pin 11, the control interface of second controllable amplifier 152 with
The control chip 16 connects.
It should be noted that in controllable amplifier (including the first controllable amplifier 151 and second controllable amplifier 152)
Comprising switch, controllable amplifier conducting is referred into closing the switch controllable amplifier, controllable amplifier disconnection is referred to can
The switch for controlling amplifier disconnects.
It referring to figure 5., is the schematic block diagram of the control chip 16 in Fig. 1, in certain feasible embodiments, such as this reality
It applies in example, the control chip 16 includes that judging unit 161, Logical processing unit 162 and address generate output unit 163,
Wherein:
The judging unit 161 is used for when receiving the control instruction of the main control device, judges the control instruction
It whether is that the address generates instruction.
Specifically, judging unit 161 judges instruction type belonging to the control instruction of main control device, generates and refer to if address
It enables, then notification logic processing unit 162 executes the instruction that address generates；If the control instruction of other types, then notice is patrolled
It collects processing unit 162 and executes corresponding movement or logical process.
If it is institute that the Logical processing unit 162, which is the control signal for the judging result of the judging unit 161,
It states address and generates instruction, and when the first control pin 13 of the controlled device 10 detects first predetermined level, it will
First controllable amplifier 151 disconnects, and second controllable amplifier 152 is connected；And by the of the controlled device 10
Two control pins 14 are adjusted to state of a control and export first predetermined level；First control of the controlled device 10 is drawn
Foot 13 is adjusted to state of a control and exports first predetermined level；Second control pin 14 of the controlled device is adjusted to
Detecting state, and when the second control pin 14 of the controlled device 10 detects second predetermined level, by described the
The conducting of one controllable amplifier 151, second controllable amplifier 152 disconnect, and second in the controlled device 10 controls pin
14 when detecting first predetermined level, first controllable amplifier 151 is disconnected, second controllable amplifier 152
Conducting.
It should be noted that in the initial state, the first control pin 13 of controlled device 10 and the second control pin 14
It is detecting state, after the address of controlled device 10 generates, Logical processing unit 162 is controlled the second of controlled device 10
Pin 14 processed is adjusted to state of a control and exports the first predetermined level, so that the first control pin 13 of subordinate equipment detects the
One predetermined level.First control pin 13 of controlled device 10 is adjusted to state of a control and exports the first predetermined level, so that
Second control pin 14 of higher level equipment detects the first predetermined level.
Later, the second control pin 14 of the controlled device 10 is adjusted to detecting state by Logical processing unit 162, this
If when controlled device 10 have a subordinate equipment, the second control pin 14 will test second predetermined level (because of the second control
Pin 14 processed is predisposed to the second predetermined level), Logical processing unit 162 is by the positive guide of the amplifier unit 15 of controlled device 10
Logical reversed disconnection.The first control that the second control pin 14 of controlled device 10 detects its subordinate equipment as detection foot later is drawn
The current potential of foot 13, if detecting the first predetermined level, Logical processing unit 162 is by the amplifier unit 15 of controlled device 10
Forward direction disconnects reverse-conducting.If controlled device 10 does not have subordinate equipment, controlled device 10 is the last one controlled device 10, the
Two control pins 14 are predisposed to the first predetermined level, therefore will detect that the first predetermined level, at this time Logical processing unit
The positive of the amplifier unit 15 of controlled device 10 is disconnected reverse-conducting by 162.
The address generates output unit 163 and is used in the judging result of the judging unit 161 be the control signal
It generates and instructs for the address, and detect first predetermined level in the first control pin 13 of the controlled device 10
When, the device address that instruction generates and saves the controlled device 10 is generated according to the address；And in the logical process
Second control pin 14 of the controlled device 10 is adjusted to state of a control and exports first predetermined level by unit 162,
It, will be described after being adjusted to state of a control by the first control pin 13 of the controlled device 10 and export first predetermined level
The device address of controlled device 10 is sent respectively to the main control device and the subordinate equipment.
It should be noted that if controlled device 10 is first controlled device, address is preset by main control device, does not need
Address generates output unit 163 and generates；If controlled device 10 is not first controlled device, address generates output unit 163
It is generated according to the device address of its higher level equipment, to guarantee that the device address between the superior and the subordinate's equipment is continuous.
In certain feasible embodiments, such as in the present embodiment, the control chip 16 is also used to execute following steps:
When the second control pin 14 of the controlled device 10 detects the second predetermined level, by the controlled device 10
The first control pin 13 be adjusted to detecting state so that the second control pin of the higher level equipment detects that described second is pre-
If level.
By executing above step, after address configuration completion, controlled device 10 is realized its amplifier unit 15
Forward conduction reversely disconnects, and the control signal that main control device 20 is sent later can normally transmit between each controlled device 10.
In certain feasible embodiments, such as in the present embodiment, the control chip 16 is single-chip microcontroller, first data
Pin 11 is connect with a data-interface of the single-chip microcontroller, and second data pin 12 and another data of the single-chip microcontroller connect
Mouthful connection, it is described first control pin 13 is connect with an I/O interface of the single-chip microcontroller, it is described second control pin 14 with it is described
Another I/O interface of single-chip microcontroller connects, and first predetermined level is low level, and second predetermined level is high level.Or
For person in other feasible embodiments, first predetermined level is high level, and second predetermined level is low level.
Fig. 6 is please referred to, is a kind of schematic block diagram of chain type control system provided in an embodiment of the present invention, as shown,
The chain type control system includes a main control device 20 and multiple controlled devices 10, and each controlled device 10 includes the first number
Pin 14, amplifier unit 15 and control core are controlled according to pin 11, the second data pin 12, first control pin 13, second
Piece 16, the amplifier unit 15 respectively with first data pin 11, second data pin 12 and the control
Chip 16 connect, the control chip 16 respectively with first data pin 11, second data pin 12, described first
Control pin 13 and the second control pin 14 connect, wherein the first data pin 11 of first controlled device 10 with
The data pin of the main control device 20 connects, and it is pre- that the first control pin 13 of first controlled device 10 is predisposed to first
If level, and since first controlled device 10 previous controlled device 10 the second data pin 12 and the latter
First data pin 11 of controlled device 10 connects, and the second control pin 14 of previous controlled device 10 is controlled with the latter to be set
Standby 10 the first control pin 13 connection and be predisposed to the second predetermined level, and so on be connected to the last one quilt step by step
Equipment 10 is controlled, the second control pin 14 of the last one controlled device 10 is predisposed to first predetermined level.It needs
Bright, the first control pin in chain type control system in addition to first controlled device is predisposed to the other institutes of the first predetermined level
There is the first control pin of controlled device to be predisposed to the second predetermined level；In addition to the last one controlled device in chain type control system
The second control pin be predisposed to the second control pin of the other all controlled devices of the first predetermined level to be predisposed to second default
Level.
Fig. 7 is referred to, each controlled device 10 is for executing following steps:
S21 generates instruction receiving the address that the main control device 20 is sent, and first at itself controls pin 13
When detecting first predetermined level, positive by the amplifier unit 15 of itself disconnects reverse-conducting.
If controlled device 10 is first controlled device 10 in chain type control system, the first control pin 13 is preset
For the first predetermined level, therefore controlled device 10 is when receiving the address that the main control device 20 is sent and generating instruction, the
One control pin 13 will detect that the first predetermined level as detection foot, and controlled device 10 is by its amplifier unit 15 at this time
Forward direction disconnects reverse-conducting.
If controlled device 10 is not first controlled device 10 in chain type control system, the first control pin 13 will be held
The level of continuous detection the second control pin 14 of controlled device 10 thereon second controls it to a controlled device 10 thereon
When pin 14 processed is adjusted to state of a control and exports the first predetermined level, the first control pin 13 of controlled device 10 be will test
First predetermined level, the positive of its amplifier unit 15 is disconnected reverse-conducting by controlled device 10 at this time.
It should be noted that the forward direction of the amplifier unit 15 is from first data pin 11 to second number
According to the signal transmission direction of pin 12；The amplifier unit 15 is reversed from second data pin 12 to described first
The signal transmission direction of data pin 11.Amplifier unit 15 is transmitted further to subordinate equipment after capable of amplifying signal, to protect
The intensity of signal is demonstrate,proved.
S22 generates the device address that instruction generates and saves itself according to the address.
After the positive disconnection reverse-conducting by the amplifier unit 15, controlled device 10 will be raw according to the address
The device address of the controlled device 10 is generated and saved at instruction.
It should be noted that if controlled device 10 is first controlled device, address is preset by main control device, if controlled
Equipment 10 is not first controlled device, and device address is generated according to the device address of its higher level equipment, to guarantee the superior and the subordinate
Device address between equipment is continuous.
The the second control pin 14 of itself is adjusted to state of a control and exports first predetermined level, by itself by S23
First control pin 13 be adjusted to state of a control and export first predetermined level.
Its second control pin 14 is adjusted to state of a control and exports first predetermined level by controlled device 10, so that
First control pin 13 of its next controlled device 10 detects the first predetermined level and starts to execute generating device address
Operation, specifically, the positive of its amplifier unit 15 is disconnected reverse-conducting by next controlled device 10, and then it controls chip
16 prepare to receive the device address data of higher level equipment, then the address date based on higher level equipment generates its equipment according to certain rules
Address.
Its first control pin 13 is adjusted to state of a control and exports first predetermined level by controlled device 10, so that
The second control pin 14 of a controlled device 10 detects the first predetermined level thereon.
It should be noted that controlled device 10 will be constantly by its first control pin 13 after generating device address
It is adjusted to the first predetermined level, so as to be continuously detected first default for the second control pin 14 of controlled device 10 thereon
Level and keep its amplifier unit 15 is positive to disconnect reverse-conducting.The purpose for the arrangement is that in order to allow subsequent each control equipment
Device address can be successfully transmitted to main control device 20.
The device address of itself is sent respectively to the main control device 20 and next controlled device 10 by S24.
Its device address is sent to the main control device 20 and its next controlled device 10, a side by controlled device 10
Its device address is fed back towards main control device 20, so that main control device 20 confirms that the address of itself generates successfully, it on the other hand, can
Next controlled device 10 is allowed to automatically generate device address on the basis of its device address, so that the address between the equipment of front and back
Continuously.
The the second control pin of itself is adjusted to detecting state, and detected in the second control pin 14 of itself by S25
When second predetermined level, the forward conduction of the amplifier unit 15 of itself is reversely disconnected, the second control at itself is drawn
When foot 14 detects first predetermined level, positive by the amplifier unit 15 of itself disconnects reverse-conducting.
Specifically, after the device address to controlled device 10 is sent, control chip 16 is by the of controlled device 10
Two control pins 14 are adjusted to detecting state, at this point, if controlled device 10 is the last one controlled device 10 in system, the
Two control pins 14 will detect that the first predetermined level, and controlled device 10 disconnects the positive of its amplifier unit 15 instead at this time
To conducting.If controlled device 10 is not the last one controlled device 10 in system, the second control pin 14 be will test to the
The forward conduction of two predetermined levels, the amplifier unit 15 of controlled device 10 reversely disconnects；Then to its next controlled device
10 by its first control pin 13 be adjusted to state of a control and export the first predetermined level when, controlled device 10 second control pin
14 will test to the first predetermined level, and the positive of its amplifier unit 15 is disconnected reverse-conducting by controlled device 10, so that thereafter
The device address that the controlled device 10 in face is sent can smoothly reach main control device 20；The finally equipment to all controlled devices 10
After address is sent to main control device 20, since the last one controlled device 10, each controlled device 10 one by one first controls it
Pin 13 processed is adjusted to detecting state, and the second control pin 14 of controlled device 10 will detect the second default electricity again at this time
It is flat, controlled device 10 by the forward conduction of amplifier unit 15 reversely disconnect.
The chain type control system that the present embodiment proposes, chain type connects between main control device 20 and controlled device 10, controlled to set
Standby 10 quantity is not limited by 20 interface number of main control device, and the quantity of controlled device 10 can be expanded arbitrarily；Controlled device 10
The potential change that pin detects, Lai Zidong generating device address are controlled according to it, address generating process is simple and efficient and to core
The processing requirement of piece is low；Each controlled device 10 ensure that the signal of main control device 20 will not decay comprising amplifier unit 15.
Referring to figure 3., and Fig. 4 is combined, in certain feasible embodiments, such as in the present embodiment, 10 ground of controlled device is put
Big device unit 15 includes the first controllable amplifier 151 and the second controllable amplifier 152, in which:
The input interface of first controllable amplifier 151 is connect with first data pin 11, and described first is controllable
The output interface of amplifier 151 is connect with second data pin 12, the control interface of first controllable amplifier 151 with
The control chip 16 connects；
The input interface of second controllable amplifier 152 is connect with second data pin 12, and described second is controllable
The output interface of amplifier 152 is connect with first data pin 11, the control interface of second controllable amplifier 152 with
The control chip 16 connects.
Referring to figure 5., in certain feasible embodiments, such as in the present embodiment, the control chip 16 of controlled device 10 is wrapped
It includes judging unit 161, Logical processing unit 162 and address and generates output unit 163, in which:
The judging unit 161 is used for when receiving the control instruction of the main control device, judges the control instruction
It whether is that the address generates instruction.
Specifically, judging unit 161 judges instruction type belonging to the control instruction of main control device, generates and refer to if address
It enables, then notification logic processing unit 162 executes the instruction that address generates；If the control instruction of other types, then notice is patrolled
It collects processing unit 162 and executes corresponding movement or logical process.
If it is institute that the Logical processing unit 162, which is the control signal for the judging result of the judging unit 161,
It states address and generates instruction, and when the first control pin 13 of the controlled device 10 detects first predetermined level, it will
First controllable amplifier 151 disconnects, and second controllable amplifier 152 is connected；And by the of the controlled device 10
Two control pins 14 are adjusted to state of a control and export first predetermined level；First control of the controlled device 10 is drawn
Foot 13 is adjusted to state of a control and exports first predetermined level；Second control pin 14 of the controlled device is adjusted to
Detecting state, and when the second control pin 14 of the controlled device 10 detects second predetermined level, by described the
The conducting of one controllable amplifier 151, second controllable amplifier 152 disconnect, and second in the controlled device 10 controls pin
14 when detecting first predetermined level, first controllable amplifier 151 is disconnected, second controllable amplifier 152
Conducting.
It should be noted that the first control pin 13 of controlled device 10 and the second control pin 14 are equal when original state
For detecting state, after the address of controlled device 10 generates, Logical processing unit 162 is controlled the second of controlled device 10
Pin 14 is adjusted to state of a control and exports the first predetermined level, so that the first control pin 13 of next controlled device 10 is examined
Measure the first predetermined level.First control pin 13 of controlled device 10 is adjusted to state of a control and exports the first default electricity
It is flat, so that the second control pin 14 of a upper controlled device 10 detects the first predetermined level.
Later, the second control pin 14 of the controlled device 10 is adjusted to detecting state by Logical processing unit 162, this
If when controlled device 10 be not the last one controlled device 10, the second control pin 14 will test second predetermined level
(because second control pin 14 be predisposed to the second predetermined level), Logical processing unit 162 is by the amplifier list of controlled device 10
The forward conduction of member 15 reversely disconnects.The second control pin 14 of controlled device 10 detects its subordinate equipment as detection foot later
First control pin 13 current potential, if detecting the first predetermined level, Logical processing unit 162 is put controlled device 10
Big the positive of device unit 15 disconnects reverse-conducting.If controlled device 10 is the last one controlled device 10, the second control pin
14 are predisposed to the first predetermined level, therefore will detect that the first predetermined level, and Logical processing unit 162 is set controlled at this time
The positive of standby 10 amplifier unit 15 disconnects reverse-conducting.
The address generates output unit 163 and is used in the judging result of the judging unit 161 be the control signal
It generates and instructs for the address, and detect first predetermined level in the first control pin 13 of the controlled device 10
When, the device address that instruction generates and saves the controlled device 10 is generated according to the address；And in the logical process
Second control pin 14 of the controlled device 10 is adjusted to state of a control and exports first predetermined level by unit 162,
It, will be described after being adjusted to state of a control by the first control pin 13 of the controlled device 10 and export first predetermined level
The device address of controlled device 10 is sent respectively to the main control device 20 and next controlled device 10.
It should be noted that if controlled device 10 is first controlled device, address is preset by main control device, does not need
Address generates output unit 163 and generates；If controlled device 10 is not first controlled device, address generates output unit 163
Its own device address is generated according to the device address of its higher level equipment, to guarantee that the device address between the superior and the subordinate's equipment is continuous.
In certain feasible embodiments, such as in the present embodiment, the last one described controlled device 10 be also used to by its
After device address is sent to main control device 20, the first control pin 13 of itself is adjusted to detecting state, so that one thereon
Second control pin 14 of controlled device detects second predetermined level；
Other controlled devices 10 other than the last one described controlled device 10 are also used to control pin itself second
14 when detecting second predetermined level, and the first control pin 13 of the controlled device 10 is adjusted to detecting state, with
Make the second of the higher level equipment to control pin 14 and detects second predetermined level.
By executing above step, after its device address is sent to main control device 20 by the last one controlled device 10,
Since the last one controlled device 10, its first control pin 13 is adjusted to detecting state one by one by each controlled device 10, this
When each controlled device 10 the second control pin 14 will detect the second predetermined level again, and by the amplification of controlled device 10
The forward conduction of device unit 15 reversely disconnects, so that the control signal that ensure that main control device 20 is sent can be in controlled device 10
Between normally transmit.
In certain feasible embodiments, such as in the present embodiment, the control chip 16 is single-chip microcontroller, first data
Pin 11 is connect with a data-interface of the single-chip microcontroller, and second data pin 12 and another data of the single-chip microcontroller connect
Mouthful connection, it is described first control pin 13 is connect with an I/O interface of the single-chip microcontroller, it is described second control pin 14 with it is described
Another I/O interface of single-chip microcontroller connects, and first predetermined level is low level, and second predetermined level is high level.
Or in other feasible embodiments, first predetermined level is high level, and second predetermined level is
Low level.
In certain feasible embodiments, such as in the present embodiment, the first control pin of first controlled device 10
13 are grounded, and the first control pin 13 and pull-up resistor of other controlled devices 10 other than first controlled device 10 connect
It connects, the second control pin 14 of the last one controlled device 10 is grounded, its other than the last one described controlled device 10
The second control pin 14 of its controlled device 10 is connect with pull-up resistor.
Or in other feasible embodiments, the first control pin 13 and pull-up electricity of first controlled device 10
Resistance connects, and the first control pin 13 and pull down resistor of other controlled devices 10 other than first controlled device 10 connect
It connects, the second control pin 14 of the last one controlled device 10 is connect with pull-up resistor, the last one described controlled device
Second control pin 14 of other controlled devices 10 other than 10 is connect with pull down resistor.
It should be noted that in the initial state, the current potential of the first control pin 13 of first controlled device 10 and its
The current potential of the first control pin 13 of its controlled device 10 is different；The electricity of second control pin 14 of the last one controlled device 10
Position is different from the second control current potential of pin 14 of other controlled devices 10, and it is of the invention naturally to be given above two kinds of connection types
The preferred connection type provided is based on core concept of the present invention, and those skilled in the art can also use other connection types,
This will not influence protection scope of the present invention.
It should be appreciated that the realization about above-mentioned 16 function of control chip, is by the way that software journey is written to control chip 16
Sequence and the configuration for realizing corresponding function.
Those of ordinary skill in the art may be aware that list described in conjunction with the examples disclosed in the embodiments of the present disclosure
Member and algorithm steps, can be realized with electronic hardware, computer software, or a combination of the two, in order to clearly demonstrate hardware
With the interchangeability of software, each exemplary composition and step are generally described according to function in the above description.This
A little functions are implemented in hardware or software actually, the specific application and design constraint depending on technical solution.Specially
Industry technical staff can use different methods to achieve the described function each specific application, but this realization is not
It is considered as beyond the scope of this invention.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in various equivalent modifications or replace
It changes, these modifications or substitutions should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with right
It is required that protection scope subject to.
Claims (10)
1. a kind of controlled device, it is characterised in that: including the first data pin, the second data pin, the first control pin, second
Control pin, amplifier unit and control chip, the amplifier unit respectively with first data pin, described second
Data pin and the control chip connection, the control chip respectively with first data pin, second data
Pin, the first control pin and the second control pin connection, the first control pin is used for and higher level equipment
The second control pin connection and be predisposed to the second predetermined level, or be predisposed to the first predetermined level, second control is drawn
Foot is used to connect with the first control pin of subordinate equipment and is predisposed to second predetermined level, or is predisposed to described first
Predetermined level, first data pin is used to connect with the second data pin of the higher level equipment, or and main control device
Data pin connection, second data pin with the first data pin of the subordinate equipment for connecting, the control
Chip is used for:
Instruction is generated receiving the address that the main control device is sent, and in the first control pin detection of the controlled device
When to first predetermined level, positive by the amplifier unit disconnects reverse-conducting；It is generated and is instructed according to the address
Generate and save the device address of the controlled device；Second control pin of the controlled device is adjusted to state of a control simultaneously
Export first predetermined level；First control pin of the controlled device is adjusted to state of a control and exports described first
Predetermined level；The device address of the controlled device is sent respectively to the main control device and the subordinate equipment；By institute
The the second control pin for stating controlled device is adjusted to detecting state, and detects institute in the second control pin of the controlled device
When stating the second predetermined level, the forward conduction of the amplifier unit is reversely disconnected, in the second control of the controlled device
When pin detects first predetermined level, positive by the amplifier unit disconnects reverse-conducting；
Wherein, the forward direction of the amplifier unit is to transmit from first data pin to the signal of second data pin
Direction；The signal transmission side of the amplifier unit being reversed from second data pin to first data pin
To；The higher level equipment is another controlled device, and the subordinate equipment is another controlled device.
2. controlled device as described in claim 1, which is characterized in that the amplifier unit include the first controllable amplifier with
And second controllable amplifier, in which:
The input interface of first controllable amplifier is connect with first data pin, first controllable amplifier it is defeated
Outgoing interface is connect with second data pin, and the control interface of first controllable amplifier is connect with the control chip；
The input interface of second controllable amplifier is connect with second data pin, second controllable amplifier it is defeated
Outgoing interface is connect with first data pin, and the control interface of second controllable amplifier is connect with the control chip.
3. controlled device as claimed in claim 2, which is characterized in that the control chip includes judging unit, logical process
Unit and address generate output unit, in which:
The judging unit is used for when receiving the control instruction of the main control device, judges whether the control instruction is institute
It states address and generates instruction；
If it is that the address generates that the Logical processing unit, which is the control instruction for the judging result of the judging unit,
Instruction, and when the first control pin of the controlled device detects first predetermined level, described first is controllably put
Big device disconnects, the second controllable amplifier conducting；And the second control pin of the controlled device is adjusted to control shape
State simultaneously exports first predetermined level；First control pin of the controlled device is adjusted to described in state of a control and output
First predetermined level；The second of controlled device control pin is adjusted to detecting state, and the of the controlled device
When two control pins detect second predetermined level, first controllable amplifier is connected, the described second controllable amplification
Device disconnects, and when the second control pin of the controlled device detects first predetermined level, described first is controllably put
Big device disconnects, the second controllable amplifier conducting；
The address generates output unit and is used to be the control instruction in the judging result of the judging unit to be the address
Instruction is generated, and when the first control pin of the controlled device detects first predetermined level, according to the address
Generate the device address that instruction generates and saves the controlled device；And in the Logical processing unit by the controlled device
The second control pin be adjusted to state of a control and export first predetermined level, the first of the controlled device the control is drawn
After foot is adjusted to state of a control and exports first predetermined level, the device address of the controlled device is sent respectively to institute
State main control device and the subordinate equipment.
4. controlled device as described in claim 1, which is characterized in that the control chip is also used to:
When the second control pin of the controlled device detects second predetermined level, by the first of the controlled device
Control pin is adjusted to detecting state, so that the second control pin of the higher level equipment detects second predetermined level.
5. controlled device according to any one of claims 1-4, it is characterised in that: the control chip is single-chip microcontroller, described
First data pin is connect with a data-interface of the single-chip microcontroller, another number of second data pin and the single-chip microcontroller
Connected according to interface, it is described first control pin is connect with an I/O interface of the single-chip microcontroller, it is described second control pin with it is described
Another I/O interface of single-chip microcontroller connects.
6. a kind of chain type control system, which is characterized in that each described controlled including a main control device and multiple controlled devices
Equipment includes the first data pin, the second data pin, the first control pin, the second control pin, amplifier unit and control
Coremaking piece, the amplifier unit respectively with first data pin, second data pin and the control chip
Connection, the control chip respectively with first data pin, second data pin, it is described first control pin and
The second control pin connection, wherein the first data pin of first controlled device and the data of the main control device are drawn
First control pin of foot connection, first controlled device is predisposed to the first predetermined level, and from first quilt
Control equipment starts, and the second data pin of previous controlled device is connect with the first data pin of the latter controlled device, preceding
Second control pin of one controlled device connect with the first control pin of the latter controlled device and is predisposed to second and presets
Level, and so on be connected to the last one controlled device step by step, the second control of the last one controlled device is drawn
Foot is predisposed to first predetermined level, in which:
Each controlled device is used to generate instruction in the address for receiving the main control device transmission, and in the first control of itself
When pin processed detects first predetermined level, positive by the amplifier unit of itself disconnects reverse-conducting；According to described
Address generates the device address that instruction generates and saves itself；The the second control pin of itself is adjusted to state of a control and is exported
First predetermined level；The the first control pin of itself is adjusted to state of a control and exports first predetermined level；It will
The device address of itself is sent respectively to the main control device and next controlled device；Pin tune is controlled by itself second
Whole is detecting state, and when the second control pin of itself detects second predetermined level, by the amplifier list of itself
The forward conduction of member reversely disconnects, when the second control pin of itself detects first predetermined level, by putting for itself
The positive of big device unit disconnects reverse-conducting；
The forward direction of the amplifier unit is from first data pin to the signal transmission direction of second data pin；
The signal transmission direction of the amplifier unit being reversed from second data pin to first data pin.
7. chain type control system as claimed in claim 6, it is characterised in that: the amplifier unit includes the first controllable amplification
Device and the second controllable amplifier, in which:
The input interface of first controllable amplifier is connect with first data pin, first controllable amplifier it is defeated
Outgoing interface is connect with second data pin, and the control interface of first controllable amplifier is connect with the control chip；
The input interface of second controllable amplifier is connect with second data pin, second controllable amplifier it is defeated
Outgoing interface is connect with first data pin, and the control interface of second controllable amplifier is connect with the control chip.
8. chain type control system as claimed in claim 7, it is characterised in that: the control chip includes judging unit, logic
Processing unit and address generate output unit, in which:
The judging unit is used for when receiving the control instruction of the main control device, judges whether the control instruction is institute
It states address and generates instruction；
The Logical processing unit is used to be the control instruction in the judging result of the judging unit to be that the address generates
Instruction, and when the first control pin of the controlled device detects first predetermined level, described first is controllably put
Big device disconnects, the second controllable amplifier conducting；And the second control pin of the controlled device is adjusted to control shape
State simultaneously exports first predetermined level；First control pin of the controlled device is adjusted to described in state of a control and output
First predetermined level；The second of controlled device control pin is adjusted to detecting state, and the of the controlled device
When two control pins detect second predetermined level, first controllable amplifier is connected, the described second controllable amplification
Device disconnects, and when the second control pin of the controlled device detects first predetermined level, described first is controllably put
Big device disconnects, the second controllable amplifier conducting；
The address generates output unit and is used to be the control instruction in the judging result of the judging unit to be the address
Instruction is generated, and when the first control pin of the controlled device detects first predetermined level, according to the address
Generate the device address that instruction generates and saves the controlled device；And in the Logical processing unit by the controlled device
The second control pin be adjusted to state of a control and export first predetermined level, the first of the controlled device the control is drawn
After foot is adjusted to state of a control and exports first predetermined level, the device address of the controlled device is sent respectively to institute
State main control device and next controlled device.
9. chain type control system as claimed in claim 6, it is characterised in that:
The last one described controlled device is also used to after its device address is sent to main control device, by the first control of itself
Pin is adjusted to detecting state, so that the second control pin of a controlled device detects second predetermined level thereon；
Other controlled devices other than the last one described controlled device are also used to detect institute in the second control pin of itself
When stating the second predetermined level, the itself first control pin is adjusted to detecting state, so that the of controlled device thereon
Two control pins detect second predetermined level.
10. chain type control system as claim in any one of claims 6-9, it is characterised in that:
The control chip is single-chip microcontroller, and first data pin connect with a data-interface of the single-chip microcontroller, described the
Two data pins are connect with another data-interface of the single-chip microcontroller, an I/O of the first control pin and the single-chip microcontroller
Interface connection, the second control pin are connect with another I/O interface of the single-chip microcontroller.
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| CN109947555A (en) * | 2017-12-21 | 2019-06-28 | 北京比特大陆科技有限公司 | Data processing equipment, data transmission method for uplink and calculating equipment |
| CN114913806A (en) * | 2021-01-29 | 2022-08-16 | 东莞市欧思科光电科技有限公司 | Drive chip, LED device and serial address writing method thereof |
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| EP0671833B1 (en) * | 1994-03-09 | 2003-05-21 | Sharp Kabushiki Kaisha | A microcomputer control optical fiber transmission system |
| CN101013316A (en) * | 2007-01-15 | 2007-08-08 | 大连光洋科技工程有限公司 | Bus-type numerical control system and control method thereof |
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