CN107346786A - GGNMOS transistors, refer to GGNMOS devices and circuit more - Google Patents
GGNMOS transistors, refer to GGNMOS devices and circuit more Download PDFInfo
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- CN107346786A CN107346786A CN201610293401.XA CN201610293401A CN107346786A CN 107346786 A CN107346786 A CN 107346786A CN 201610293401 A CN201610293401 A CN 201610293401A CN 107346786 A CN107346786 A CN 107346786A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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Abstract
The present invention provides a kind of ggnmos transistor, refers to GGNMOS devices and circuit more, is suspended with p-type ion implantation region in the drain region of the ggnmos transistor, the p-type ion implantation region at least its all sides and bottom surface are wrapped in the drain region.In more finger GGNMOS devices of the present invention, p-type ion implantation region is suspended with the drain terminal of each ggnmos transistor.The p-type ion implantation region of suspension forms the drain region Zener auxiliary breakdown area horizontal with P type substrate; breakdown voltage is lower; and in the intersection at drain region and P type substrate interface without PN junction; so as to while the trigger voltage of ESD protections is reduced; the electric leakage that traditional ESD ion implantings introduce is reduced, improves the reliability of esd protection circuit.
Description
Technical field
The present invention relates to the electro-static discharge protection design technical field of integrated circuit, more particularly to one kind
Ggnmos transistor, refer to GGNMOS devices and electrostatic discharge protective circuit more.
Background technology
In integrated circuit (Integrated Circuits, IC), static discharge (Electrostatic discharge,
ESD) reliability effect of chip can not be ignored, especially deep-submicron, nanometer technology it is commonly used work as
The static discharge such as the present, external environment condition, human body, machinery, radiation field is more aobvious to IC chip destructive influences
Write.Substantial amounts of research and practice have been done in protection of the industry to ESD in IC design and manufacturing process, generally,
The problem of design of ESD protective device on chip needs to consider two aspects：First, ESD protective device will
Can be released high current；Second, ESD protective device will can be when chip be by ESD impact by chip pin end
Low voltage level of the voltage clamping in safety.And considered based on above-mentioned design, the device master as ESD protections
There are diode, GGNMOS (NMOS of Gate Ground NMOS, i.e. grid ground connection), controllable silicon
(SiliconControlledRectifier, SCR) etc..Wherein GGNMOS is simultaneous to CMOS technology processing procedure
Capacitive, the quickly innate advantage such as switch response and low on-resistance, turn into most normal in CMOS technology processing procedure
Be elected to be as one of device of ESD protection device, its mainly using its parasitic horizontal NPN triode work come
Release ESD high currents, the cut-in voltage of the parasitic triode depends on the horizontal NPN triode of the parasitism
In the avalanche breakdown voltage of the reverse PN junction of colelctor electrode, i.e. GGNMOS drain electrode (Drain) and its substrate
Avalanche breakdown voltage between p-well (P-well).Needed when from GGNMOS as ESD protective device
The width to be designed is very big, to guarantee by enough leakage currents, and due to the limitation and electric current of domain
The requirement of uniformity, GGNMOS structures are usually designed to that refer to (multi-finger) ties more in the prior art
Structure, in parallel equivalent to the finger of multiple N-type MOS structures, existing one kind as shown in Figure 1A is typical
The domain structure schematic diagram of GGNMOS structures, including：P type substrate (P-well) 10, N+ have source area
11st, grid 16, the source area 14 of comb teeth-shaped and drain region 17, the source area 14 of comb teeth-shaped and drain region 17
Being arranged at N+ has in source area 11, and grid 16 is arranged at the upper surface of P type substrate 10 and is arranged at
Between the source area 14 and drain region 17, the source S that is formed on source area 14, formed on drain region 17
Drain D, and the NPN knots formed between each pair source S and drain D referred to as refer to (finger), it is each
The source electrode of ggnmos transistor and drain electrode are carried out by the way that contact hole 16 and metal interconnection structure are (not shown)
Corresponding connection, it is respectively connecting to earth terminal or electrostatic end etc..The cross-section structure of the GGNMOS structures
Schematic diagram is shown in Figure 1B and Fig. 1 C with circuit structure schematic diagram, when the GGNMOS structures are used for ESD protections,
Its each source S and grid 16 are grounded, and pick-up area (Pickup, also referred to as bonding pad) 12 is also grounded, leakage
Pole D connection electrostatic end, and each pair source S and drain D and P type substrate 10 below form one and posted
Raw NPN pipes.It can be seen that adjacent related NMOS tube shares a drain electrode from Figure 1B, and it is two neighboring
Distance of the NMOS tube apart from pick-up area 12 is different, therefore the base stage of adjacent parasitic NPN pipe and pick-up area
The internal resistance R-sub of P type substrate 10 between 12 is also differed, therefore this how interdigital GGNMOS structures,
Because in-between interdigital bulk resistor is maximum, prior to other interdigital unlatchings, and each interdigital can not uniformly open
Open, so cause the decline of the antistatic capacity of integrated circuit, and this GGNMOS structures
Breakdown voltage between NMOS drain terminal and P-well is of a relatively high, is unfavorable for ESD protections.
In the prior art, in order to optimize and reduce the cut-in voltage of common GGNMOS ESD protective devices,
Conventional scheme is exactly to increase an ESD injection, U.S. Patent application US as shown in figure iD
It is a kind of disclosed in 2003/0089951 A1 to be used for the deep sub- of high voltage tolerance ESD protective device (ESDPD)
Micrometre CMOS process ESD injection techniques, its each GGNMOS pipe is by its corresponding SOURCE end
(i.e. source), DRAIN ends (i.e. drain terminal) and GATE structure (the i.e. grid above P-WELL
Pole structure) formed, and the N+ injection regions at SOURCE ends, the N+ notes at P-WELL and DRAIN ends
Enter area and form parasitic NPN triode, the N+ injection regions at SOURCE ends are the hair of parasitic NPN triode
Area is penetrated, P-WELL is the base of parasitic NPN triode, and the N+ injection regions at DRAIN ends are parasitic NPN
The collecting zone of triode, the technical scheme (refer to the void in Fig. 1 D in the collecting zone of parasitic NPN triode
The region that wire frame is marked, i.e., the collecting zone of two adjacent parasitic NPN triodes), implanting p-type ion is (in detail
See the ESD IMPLANT shown in Fig. 1 D), N+ of the depth at NMOS DRAIN ends injects
The intersection in area and P-WELL interfaces, so as to introduce Zener to reach the purpose of reduction avalanche breakdown voltage.
Although this ESD injection techniques can play a part of reducing GGNMOS ESD protective device cut-in voltages,
But one layer of photoetching and injection technology must be increased, increase manufacturing cost, meanwhile, the introducing of ESD injections is given
Device brings bigger PN junction electric leakage.
Therefore, it is necessary to a kind of ggnmos transistor, more finger GGNMOS devices and electrostatic discharge protective circuit,
Trigger voltage can be reduced, while ESD can also be reduced and inject introduced electric leakage.
The content of the invention
It is an object of the invention to provide a kind of ggnmos transistor, refer to GGNMOS devices and circuit more,
Trigger voltage can be reduced, while ESD can also be reduced and inject introduced electric leakage.
To solve the above problems, the present invention proposes a kind of ggnmos transistor, including：
P type substrate；
N-type has source area, is formed in the P type substrate, the N-type have source area include source area,
Drain region and the channel region between the source area, drain region, p-type is suspended with the drain region
Ion implantation region, the p-type ion implantation region at least its all sides and bottom surface are wrapped in the drain region
In；
Grid structure, it is covered in above the channel region.
Further, the P type substrate and N-type, which have, is also formed with p-well between source area, the source area,
Drain region and channel region are both formed in the p-well.
Further, all surface of the p-type ion implantation region be wrapped in the drain region or
The upper surface of the p-type ion implantation region and the drain region upper surface flush.
Further, the p-type ion implantation region is in the center of the drain region.
Further, the drain region junction depth above the p-type ion implantation region is less than the drain region in remaining region
Junction depth.
Further, the source area, drain region are in bar shaped.
Further, grid is grounded in the source area and grid structure, and the drain region connects external circuit.
The present invention also proposes a kind of GGNMOS devices of finger more, including：
P type substrate；
N-type has source area, is formed in the P type substrate；
Being formed at N-type has at least two in source area above-mentioned ggnmos transistors.
Further, the source area of all ggnmos transistors connects as one, and is arranged in comb teeth-shaped；
The drain region of all ggnmos transistors connects as one, and is arranged in comb teeth-shaped.
Further, two neighboring ggnmos transistor is common drain area transistor；It is or two neighboring
The drain region of ggnmos transistor is separate, and positioned at adjacent ggnmos transistor drain region it
Between P type substrate in be provided with N-type connection trap, and the N-type connection trap be connected with the drain region of its both sides.
Further, it is provided with pickup in the N-type of all ggnmos transistors periphery has source area
Area.
Further, the grid of all ggnmos transistors, source area are grounded, the pick-up area ground connection,
The drain region of all ggnmos transistors connects external circuit.
Further, the specification of the p-type ion implantation region to be suspended in the drain region of all ggnmos transistors
It is identical.
Further, the specification of all ggnmos transistors is identical.
The present invention also provides a kind of electrostatic discharge protective circuit, including input, earth terminal and at least one above-mentioned
Ggnmos transistor, the P type substrate of each ggnmos transistor, source area, grid structure are equal
The earth terminal is connected to, the drain region of each ggnmos transistor is connected to by corresponding dead resistance
The input；Or including above-mentioned more finger GGNMOS devices, it is described to refer to GGNMOS devices more
Grid, the source area of all ggnmos transistors are connected to the earth terminal, described to refer to GGNMOS more
The drain region of all ggnmos transistors of device is connected to the input by corresponding dead resistance
End.
Compared with prior art, technical scheme has the advantages that：
1st, the present invention inserts the p-type ion implantation region to suspend, shape by the drain terminal in ggnmos transistor
The Zener horizontal into drain region and P type substrate aids in breakdown area, and breakdown voltage is lower, and the p-type to suspend
Ion implantation region drain region and P type substrate interface intersection without PN junction, so as to reduce ESD
While the trigger voltage of protection, the electric leakage that traditional ESD ion implantings introduce is reduced, improves ESD guarantors
The reliability of protection circuit.
2nd, the formation for the p-type ion implantation region that the drain terminal of ggnmos transistor of the invention suspends can be with
Source and drain injection in PMOS manufacturing process is completed simultaneously, therefore can omit ESD ion implantings light shield and work
Skill, manufacturing cost is low, suitable for 28nm and the CMOS technology processing procedure of the above.
3rd, it is outstanding in the drain terminal of each ggnmos transistor in more finger GGNMOS devices of the invention
It is floating to have p-type ion implantation region, so that each single finger GGNMOS leakage path length is identical, solving
While certainly tradition refers to GGNMOS devices triggering consistency problem more, the length of leakage path is also add,
The parasitic resistance values of leakage path are improved, and then relatively small electrostatic can lead the GGNMOS
It is logical, electrostatic is discharged, so as to solve trigger voltage rise, the antileakaging problem of electrostatic.
Brief description of the drawings
Figure 1A to 1C is a kind of conventional more finger GGNMOS structural representation in the prior art；
Fig. 1 D be in the prior art it is a kind of it is improved refer to GGNMOS structural representation；
Fig. 2A to 2C is the structural representation of the ggnmos transistor of the specific embodiment of the invention；
Fig. 3 A to 3C are the structural representations of more finger GGNMOS devices of the specific embodiment of the invention.
Embodiment
To become apparent the purpose of the present invention, feature, below in conjunction with the accompanying drawings to the specific implementation of the present invention
Mode is further described, however, the present invention can be realized with different forms, should not be to be confined to
Described embodiment.
Fig. 2A to 2C is refer to, the present invention proposes a kind of ggnmos transistor, is protected for ESD,
Including P type substrate 20, p-well (P well) 201, N active areas 21 and grid structure 24, p-well 20
In in the P type substrate 20, N active areas 21 are arranged in the p-well 201, in N active areas 21
On be provided with source area 22, drain region 23 and channel region between source area 22 and drain region 23 (not
Diagram), the grid structure 24 is covered in above the channel region, and p-type is suspended with the drain region 23
Ion implantation region 231, at least all sides of the p-type ion implantation region 231 and bottom surface are wrapped
In the drain region 23.In the present embodiment, the ion injected in p-type ion implantation region 231 is P+ ions,
Such as can be B (boron), In (indium) etc., doping concentration 1012/cm2~1013/cm2.Preferably, source
Polar region 22 and drain region 23 are bar shaped, and the p-type ion implantation region 231 is located at the centre bit of drain region 23
Put, each surface of the p-type ion implantation region 231 can be wrapped in drain region 23, the p-type from
Drain region depth above sub- implantation region is identical with the drain region depth of lower section.In the other embodiment of the present invention
In, the p-type ion implantation region 231 can also be not entirely in the center of drain region 23, for example,
The depth of the drain region 23 of the top of p-type ion implantation region 231 is less than the p-type ion implantation region 231
The depth of the drain region 23 of lower section, and the depth of the left and right drain region 23 in the p-type ion implantation region 231
Spend it is identical, the front of the p-type ion implantation region 231, rear drain region 23 depth it is identical, now institute
State the junction depth that the drain region junction depth above p-type ion implantation region is less than the drain region in remaining region.It is a kind of special
Situation is that the upper surface of the p-type ion implantation region 231 is exposed to the surface of drain region 23 (not shown),
The upper surface of i.e. described p-type ion implantation region 231 and the upper surface flush of the drain region 23.
The p-type ion implantation region 231 of the present invention is different from the p-type ion implantation region shown in Fig. 1 D, its area
Greatly reduced with depth, will not be in the friendship at the drain region 23 of ggnmos transistor and the interface of p-well 201
PN junction electric leakage is produced at boundary, therefore the p-type ion implantation region of the present invention reduces introducing Zener diode
While ggnmos transistor trigger voltage, its electric leakage can also be substantially reduced, improves and is based on being somebody's turn to do
The reliability and ESD protective capabilities of the ESD protective device of ggnmos transistor.
Further.The doping concentration of the N-type active area 21 of the ggnmos transistor, adulterate area
Change with doping thickness with technique, requirement on devices, other doped regions all change with requirement on devices, in embodiment
In be not construed as limiting.
The ggnmos transistor of the present invention is protected for ESD, and grid structure 24 and source area 22 pass through
The grade of contact hole 25 metal interconnection structure is grounded, and drain region 23 is connected by the grade of contact hole 25 metal interconnection structure
To electrostatic end, the electrostatic end for treating the external circuit that ESD is protected is attached to, concrete operating principle is as follows：
Source area 22, p-well 201 and the drain region 23 of ggnmos transistor form the pole of parasitic NPN three
Pipe, the source area 22 of ggnmos transistor are the emitter stage of the NPN triode, and p-well 201 is the NPN
The base stage of triode, drain region 23 is the colelctor electrode of the NPN triode, in (the i.e. N-type region of drain region 23
Domain) in introduce p-type ion implantation region 231 can the NPN triode colelctor electrode and treat ESD protect
External circuit between formed a lateral Zener diode, as shown in Figure 2 C.It is interim when ESD impact,
ESD electric currents flow into the drain region 23 and its p-type ion implantation region 231 by the electrostatic end of external circuit,
And then p-well 201 is flowed into, due to having dead resistance in the p-well 201, so ESD electric currents are in the P
Voltage difference is produced in trap 201, and the Zener diode for now introducing the formation of p-type ion implantation region 231 can make
Obtaining has higher electric field, smaller leakage current and more stable voltage between drain region 23 and p-well 201
Difference, and when voltage difference exceedes threshold voltage, the state of parasitic NPN triode conducting, now electric current is just
Flowed into from the drain region 23, finally flow through the source area 22 and flow out, release electrostatic, this avoid
Electrostatic damage circuit.P-type ion implantation region 231 produces the effect of similar point discharge simultaneously, realizes ESD
Auxiliary breakdown, can obtain the lower excitation voltages of GGNMOS, so as to solve trigger voltage rise, electrostatic
Antileakaging problem, it is capable of the core devices of significantly more efficient protection external circuit.
It refer to Fig. 2A and 2B, Fig. 2A is the top view of the ggnmos transistor of the present invention (to be clear
Represent, eliminate metal level), Fig. 2 B be the stereogram of ggnmos transistor of the invention (to be clear
Represent, eliminate metal level and contact hole), the manufacturing process of ggnmos transistor of the invention include with
Lower step：
Step S1：P type substrate 20 is provided, the P type substrate 20 is the silicon chip or insulation that p-type is lightly doped
The properties such as silicon substrate on body, the resistivity of the P type substrate, impurity concentration meet the electrical requirements of device.
Further, the injection of p-type ion trap, the injection of N-type ion active area are carried out successively in P type substrate 20,
So as to sequentially form p-well 201 and N-type active area 21.
Step S2：The grid including gate oxide and polysilicon gate is sequentially formed on N-type active area 21
Structure 24.Specifically, first, before gate oxide is formed, using devices such as LOCOS or STI
Isolation method, oxide isolation zone is formed in the non-active area of P type substrate 20；Then, cleaning silicon chip,
Contamination and the oxide layer on surface are removed, it is active in N-type by aoxidizing furnace technology or chemical vapor deposition method
A floor silicon oxide film is formed in area 21 as gate oxide；Then, silane and low pressure chemical phase are utilized
Deposition apparatus deposit polycrystalline silicon layer on gate oxide, and to after deposit polysilicon carry out phosphorus doping or
Silicidation；Then carved using deep ultra violet photolithography and the anisotropic plasma etch choice of technology
Lose the polysilicon gate with vertical section, so as to obtain including gate oxide and polysilicon gate
Grid structure 24.Further, using the deposition-etch technique of silicon nitride or silica etc., in grid structure
Side formed surround grid structure 24 side wall
Step S3：Using grid structure as mask, LDD is carried out to the N-type active area 21 of the both sides of grid structure 24
Injection and source drain implant, and source and drain ion implanting annealing is carried out, to form source area 22 and drain region 23.
Wherein so-called LDD injections, i.e. lightly doped drain inject, and refer to forming the source area 22 of GGNMOS pipes
Before drain region 23, first the N-type active area 21 of at least side of grid structure 24 is lightly doped, so
Source/drain region ion implanting is done to the N-type active area 21 of the both sides of grid structure 24 again afterwards, its purpose is to effective
Prevent short-channel effect, and reduce the thermoelectronic effect of channel region between source, leakage.In the present embodiment, with
Grid structure 24 is mask, after the ldd implantation, N is carried out to the N-type active area of the both sides of grid structure 24
Type ion, form source area 22 and drain region 23.It is that mask carries out forming source electrode so with grid structure 24
The mode of the ion implanting of area 22 and drain region 23 is self aligned, only injects the lateral deviation portion of ion
Point have with grid structure 24 overlapping, therefore the parasitic capacitance that gate-drain couples with gate-source is small than grid-channel capacitance
Much.Device after source and drain ion implanting is annealed in Quick annealing device.Quick annealing device can be rapid
Reach 1000 DEG C or so of high temperature, and kept for the several seconds in design temperature.Expansion of this state for prevention structure
Open up and control source area 22, the diffusion of the impurity of drain region 23 all extremely important.Specifically, the implementation of annealing
Mode is：In the inert gas environment such as nitrogen or argon gas, annealing temperature is 900 DEG C~1000 DEG C, during annealing
Between be 10s~60s.
Step S4：The source/drain region ion implanting light shield and technique of PMOS manufacturing process are directly used, to leakage
The center position area of polar region 23 carries out p-type and is ion implanted, and forms p-type ion implantation region 231 to realize Lou
Polar region 23 ESD auxiliary breakdown, therefore the step can on IC chip to be manufactured PMOS
The source/drain region ion implanting step of manufacturing process synchronously completes, it is clear that can omit ESD ion implanting light shields
And technique, reach the purpose for reducing GGNMOS ESD protective device cut-in voltages, and can reach
Outstanding electric leakage control.Specifically, resist coating on device surface after step s 3, after exposure imaging
The light shield of the source/drain region ion implanting for PMOS manufacturing process is formed, can synchronously drained in the step
P-type is formed on the relevant position in area 23 window is ion implanted, such as the center of drain region 23 (drains
The all around symmetrical position of area 23) top.Using the light shield as mask, using boron difluoride, indium phosphide etc.
, can be to the p-type while material carries out B, In ion implanting to the source/drain region of PMOS manufacturing process
The drain region 23 being ion implanted in window carries out the implantation of the P+ type foreign ions such as B, In, so as to form P
Type ion implantation region 231, then removes photoresist.Wherein, p-type ion implantation region 231 can be completely in
The junction depth of the drain region 23 of the center of drain region 23, i.e. p-type ion implantation region 231 top can be with
The junction depth of drain region 23 below is identical；P-type ion implantation region 231 can also be not entirely in drain region
The junction depth of the drain region 23 of 23 center, i.e. p-type ion implantation region 231 top can be than below
The junction depth of drain region 23 is small, but the width of the drain region 23 on its left side can be with the width of the drain region 23 on the right
Spend identical, the width of drain region 23 in front can be identical with the width of the drain region 23 of back.P-type ion
Ggnmos transistor device after implantation can anneal in Quick annealing device.Quick annealing device can
1000 DEG C or so of high temperature is rapidly reached, and is kept for the several seconds in design temperature.This state is for preventing structure
Extension and voltage input/drain impurity diffusion it is all extremely important.Specifically, the embodiment of annealing is：
In the inert gas environment such as nitrogen or argon gas, annealing temperature be 350 DEG C~550 DEG C, annealing time be 5s~
20s.Furthermore it is also possible to the ion plant of regulation p-type can be reached by changing the size of above-mentioned light shield relevant position
Enter the effect of window, so as to what is obtained different be ion implanted by p-type in N+ drain regions 23 and formed
The compressed region area of horizontal Zener, puncture cut-in voltage so as to have the function that to adjust it.Can be with
The technological parameters such as dosage, energy are ion implanted to adjust the p-type ion implantation region of formation by changing p-type
Depth, puncture cut-in voltage so as to have the function that to adjust it.
Step S5：Contact hole 25 is formed in the relevant position of the device surface including p-type ion implantation region 231
And the step such as metal interconnecting layer, that is, foring the present invention has the GGNMOS of good ESD protective effects
Transistor.
Due to, p-type ion implantation region 231 can complete simultaneously with the source and drain injection in PMOS manufacturing process,
Therefore the preparation method of the ggnmos transistor of the present invention can omit ESD ion implantings light shield and technique,
Manufacturing cost is low, suitable for 28nm and the CMOS technology processing procedure of the above.
The top view for more finger GGNMOS devices that Fig. 3 A and 3B, Fig. 3 A are the present invention be refer to (to be clear
Chu represents, eliminates metal level), Fig. 3 B be more finger GGNMOS devices of the invention stereogram (for
Clearly show that, eliminate metal level and contact hole), the present invention also proposes a kind of GGNMOS devices of finger more,
Have source area 31 including P type substrate 30, N-type and be formed at N-type have in source area 31 at least two
Above-mentioned ggnmos transistor, specifically, foring multigroup bar shaped source area in N-type active area 31
32 and bar shaped drain region 33, every group of bar shaped source area 32, bar shaped drain region 33 and its grid structure of top
34 form a GGNMNOS transistors, and every group of bar shaped source area 32, bar shaped drain region 33 and its it
Between P type substrate 30 (be specially P type substrate on p-well 301) form finger GGNMOS devices more
One finger, and it is provided with the p-type ion implantation region 331 to suspend in it, the P in each bar shaped drain region 33
All sides and bottom surface of type ion implantation region 331 are wrapped in the bar shaped drain region 33, or even upper table
Face is also included in the bar shaped drain region 33.
In addition, bar shaped source area 32 all on N-type active area 31 can be separate, can be in N-type
The boundary position of active area 31 connects as one, so as to form comb teeth-shaped arrangement architecture；Similarly, N-type has
All bar shaped drain regions 33 can be separate in source region 31, can be in the boundary bit of N-type active area 31
Put and connect as one, so as to form comb teeth-shaped arrangement architecture.Therefore, in one embodiment of the invention,
Device isolation structure can be provided between all ggnmos transistors of finger GGNMOS devices more,
And the source area 32 of all ggnmos transistors is isolated and separate, drain region 33 by field isolated area
Also isolated and separate by field isolated area, (Fig. 3 C are more finger GGNMOS of the present invention as shown in Figure 3 C
The profile of device, to clearly show that, eliminate metal level and contact hole), positioned at two neighboring GGNMOS
N-type connection trap 303 is provided with P type substrate 30 between the drain region 33 of transistor, and the N-type connects
Connect trap 303 to be connected with the drain region 33 of its both sides, for two independent ggnmos transistors to be electrically connected
Connect.In another embodiment of the present invention, refer to all ggnmos transistors of GGNMOS devices more
Between can be with interrelated, two neighboring ggnmos transistor as shown in Fig. 3 A, 3B shares one
Individual source area 32, or two neighboring ggnmos transistor share a drain region 33, further,
Pick-up area (pick up) is provided with the N-type of all ggnmos transistors periphery has source area 31
302, the ion adulterated in the pick-up area can be N-type ion, or p-type ion.
Preferably, the specification of all p-type ion implantation regions in the GGNMOS devices is identical, i.e., all
The all sames such as the position of p-type ion implantation region, Doped ions, doping concentration.Further, the GGNMOS
The specification of all ggnmos transistors in device is identical.
The GGNMOS devices of the present invention for ESD when protecting, the grid of all ggnmos transistors
Pole structure 34, source area 32 and pick-up area 302 are grounded, the drain region of all ggnmos transistors
33 are all connected with treating the external circuit of ESD protections, i.e., the quilt of drain region 33 of all ggnmos transistors
It is connected to electrostatic end.It is every due to GGNMOS devices when static discharge (i.e. ESD impact) occurs
The p-type ion implantation region of suspension is provided with the pocket of center one of the drain region 33 of individual finger,
The depth of the p-type ion implantation region 331 will not be in the drain region 33 of each finger and the intersection of p-well 301
Produce PN junction electric leakage, at the same in finger NMOS (i.e. ggnmos transistor) drain region 33 and
Horizontal Zener auxiliary breakdown area (i.e. Zener diode) is still formed between P type substrate 30, so that
Each single finger NMOS cut-in voltages of GGNMOS devices are essentially identical and substantially reduce, so as to solve
The problem of non-uniform triggering of certainly traditional more finger GGNMOS devices and high trigger voltage.Further, since
For Fig. 3 A into the GGNMOS devices shown in 3C, the drain region 33 of all ggnmos transistors is equal
Link together, source area 32 is grounded, so equivalent to one width of whole GGNMOS devices is very long
N-type metal-oxide-semiconductor, electrostatic leakage ability is compared to the single ggnmos transistor shown in Fig. 2A to 2C
Greatly improve.Simultaneously as each p-type ion implantation region of whole GGNMOS devices can directly utilize
Source-drain electrode area ion implanting light shield and similar p-type ion in PMOS manufacturing process, i.e., each p-type from
Sub- implantation region can be synchronously completed by the source-drain electrode area ion implantation technology in PMOS manufacturing process, therefore
Without any extra ESD light shields and ESD ion implantings, technique is thereby simplify, has saved cost.
Refer to Fig. 3 A and 3B, a kind of manufacture methods of more finger GGNMOS devices of the invention include with
Lower step：
First, there is provided P type substrate 30, PMOS device region is provided with (not in the P type substrate 30
Diagram) and GGNMOS device areas, sequentially formed in GGNMOS device areas p-well 301 with
And N-type active area 31, and in non-active area (i.e. the periphery of N-type active area 31) shape of P type substrate 30
Into pick-up area 302.Afterwards using device isolation modes such as LOCOS or STI, in P type substrate 30
Oxide isolation zone is formed in the appropriate location of non-active area, PMOS device region and N-type active area 31
(not shown), realize the isolation in two neighboring PMOS device area, PMOS devices in PMOS device region
The isolating of part region and GGNMOS device areas, two neighboring GGNMOS in GGNMOS device areas
The isolation of two neighboring ggnmos transistor in the isolation of device region and each GGNMOS device regions,
N-type active area 31 defines all ggnmos transistor positions for referring to GGNMOS devices more.
Preferably, more finger GGNMOS element layouts structures of the invention and the existing GGNMOS devices of finger more are basic
Unanimously, it is still a uniform square of length and width, is advantageous to the integral layout of ESD protection device in the chips.
Then, a thin oxide layer and polysilicon layer are sequentially formed on the N-type active area 31, and then is etched
Form multiple grid structures 34.The grid structure may also include positioned at the tight of polysilicon layer and oxide layer both sides
Sidewall structure, the sidewall structure can include at least one layer of oxide skin(coating) and/or at least one layer of nitride layer.
The both sides of grid structure 34 have defined source area and the drain region of each finger of more finger GGNMOS devices.
Grid structure can be formed on PMOS device region simultaneously in this step, the grid structure can be same
Formed by etching the thin oxide layer and polysilicon layer.
Then, it is mask with each grid structure 34 on N-type active area 31, implements GGNMOS
The source/drain region of device area is injected and annealed, thus in the N-type of each both sides of grid structure 34
The He of source area 32 for each finger ggnmos transistor for referring to GGNMOS devices more is formed in active area 31
Drain region 33.Wherein, according to the oxide-isolated zone position set in N-type active area 31, refer to more
Adjacent two ggnmos transistor of GGNMOS devices can be the structure of common source polar region or be total to
The structure of drain region, it can also be the structure that source/drain distinguishes.
Then, formed in the source/drain region ion implantation technology for PMOS manufacturing process in each drain electrode
The p-type ion implantation region 231 in area 23, it is possible thereby to ESD ion implantings light shield and technique be omitted, to reach
The purpose of GGNMOS ESD protective device cut-in voltages is reduced, and outstanding electric leakage control can be reached.
Specifically, the resist coating on the device surface comprising GGNMOS device areas and PMOS device region,
The light shield of the source/drain region ion implanting of PMOS area is formed after exposure imaging and in GGNMOS devices
P-type is formed on region light shield is ion implanted, it is, for example, in the centre bit of drain region 23 that light shield, which is ion implanted, in the p-type
Put (i.e. drain region 23 all around symmetrical position) top.With the source/drain in the PMOS device region
It is mask that light shield, which is ion implanted, in p-type on the light shield and GGNMOS device areas of area's ion implanting, is used
The materials such as boron difluoride, indium phosphide carry out the P+ type ions such as B, In to the source/drain region in PMOS device region
While injection, the drain region 23 p-type being ion implanted under light shield carries out the P+ type impurity such as B, In
The implantation of ion, so as to form p-type ion implantation region 331, then remove photoresist.Wherein, p-type ion
Implantation region 331 can be completely in the center of the drain region 33 where it, i.e. p-type ion implantation region 331
The junction depth of the drain region 33 of top can be identical with the junction depth of drain region 33 below；P-type ion implantation region
331 can also be not entirely in the center of its place drain region 33, i.e., on p-type ion implantation region 331
The junction depth of the drain region 33 of side can be smaller than the junction depth of drain region 33 below, but the drain region on its left side
33 width can be identical with the width of the drain region 33 on the right, and the width of drain region 33 in front can be with
The width of the drain region 33 of back is identical.Device after p-type ion implanting can move back in Quick annealing device
Fire.So far, whole processing steps that method according to an exemplary embodiment of the present invention is implemented are completed, with
The GGNMOS devices for electrostatic discharge (ESD) protection are formed while forming PMOS device.Next, can
To complete the making of whole semiconductor devices, the subsequent technique and traditional semiconductor device by subsequent technique
Part processing technology is identical.When static discharge occurs, each finger in GGNMOS can be made while opened
Electrostatic discharge (ESD) protection is opened, is improved horizontal come the electrostatic discharge (ESD) protection weighed with human-body model (HBM).
The present invention also provides a kind of electrostatic discharge protective circuit, including input, earth terminal and at least one Fig. 2A
Shown ggnmos transistor, the P type substrate 20 of each ggnmos transistor, source area 22,
Grid structure 24 is connected to the earth terminal, and the drain region 23 of each ggnmos transistor is by corresponding
Dead resistance be connected to the input；Or including more finger GGNMOS devices shown in Fig. 3 AC,
Grid structure 34, the source area 32 of all ggnmos transistors for referring to GGNMOS devices more are equal
It is connected to the earth terminal, the drain region of all ggnmos transistors for referring to GGNMOS devices more
33 are connected to the input by corresponding dead resistance.
Further, Fig. 3 A and 3C, in one embodiment of the invention, the electrostatic protection be refer to
The N-type of all ggnmos transistor device regions periphery of more finger GGNMOS devices of circuit has source area
Pick-up area 302 is provided with 31, the pick-up area 302 is connected to the earth terminal, and each GGNMOS
Dead resistance corresponding to transistor be the base stage of parasitic NPN triode corresponding to the ggnmos transistor with
Parasitic internal resistance between P type substrate 30.
Further, Fig. 3 A and 3B, more finger GGNMOS devices of the electrostatic discharge protective circuit be refer to
Two neighboring ggnmos transistor can be common source plot structure or common drain plot structure；Or please
With reference to figure 3C, the two neighboring GGNMOS of more finger GGNMOS devices of the electrostatic discharge protective circuit is brilliant
The source area 32 of body pipe is isolated and separate by corresponding isolation structure 36, drain region 33 by accordingly every
Isolate and separate from structure 36, and the P of the lower section of drain region 33 of two neighboring ggnmos transistor
N-type connection trap is provided with trap 301, the drain region 33 of two neighboring ggnmos transistor is electrically connected
Connect.
The electrostatic discharge protective circuit with the ggnmos transistor shown in multiple Fig. 2A of the present invention, it is all
Ggnmos transistor is connected in parallel；And the GGNMOS devices having shown in Fig. 3 A of the present invention
Electrostatic discharge protective circuit, its GGNMOS device have more finger NMOS structures, equivalent to multiple single fingers
NMOS be connected in parallel.The p-type ion implantation region of suspension is set in GGNMOS drain region,
The trigger voltage of the electrostatic discharge protective circuit can be reduced, while will not also be in GGNMOS drain region and P
The intersection of type substrate produces PN junction electric leakage, so as to improve the reliability of electrostatic discharge protective circuit and ESD protections
It is horizontal.In addition, setting the suspension p-type ion implantation region of same size can also solve in electrostatic discharge protective circuit
Triggered in multiple ggnmos transistors in parallel or electrostatic discharge protective circuit between the more fingers of GGNMOS devices
Consistency problem and the rise of solution trigger voltage, the antileakaging problem of electrostatic.
Obviously, those skilled in the art can carry out various changes and modification without departing from the present invention to invention
Spirit and scope.So, if the present invention these modifications and variations belong to the claims in the present invention and its
Within the scope of equivalent technologies, then the present invention is also intended to comprising including these changes and modification.
Claims (16)
- A kind of 1. ggnmos transistor, it is characterised in that including：P type substrate；N-type has source area, is formed in the P type substrate, the N-type have source area include source area, Drain region and the channel region between the source area, drain region, p-type is suspended with the drain region Ion implantation region, the p-type ion implantation region at least its all sides and bottom surface are wrapped in the drain region In；Grid structure, it is covered in above the channel region.
- 2. ggnmos transistor as claimed in claim 1, it is characterised in that the P type substrate and N-type is also formed with p-well between having source area, and the source area, drain region and channel region are both formed in the P In trap.
- 3. ggnmos transistor as claimed in claim 1, it is characterised in that the p-type ion is planted Enter area all surface be wrapped in the drain region or the upper surface of the p-type ion implantation region with The drain region upper surface flush.
- 4. ggnmos transistor as claimed in claim 1, it is characterised in that the p-type ion is planted Enter the center that area is in the drain region.
- 5. ggnmos transistor as claimed in claim 1, it is characterised in that the p-type ion is planted Enter the junction depth that the drain region junction depth above area is less than the drain region in remaining region.
- 6. ggnmos transistor as claimed in claim 1, it is characterised in that the source area, leakage Polar region is in bar shaped.
- 7. ggnmos transistor as claimed in claim 1, it is characterised in that the source area and grid Pole structure is grounded, and the drain region connects external circuit.
- 8. a kind of refer to GGNMOS devices more, it is characterised in that including：P type substrate；N-type has source area, is formed in the P type substrate；It is formed at any one of at least two claims 1 to 7 that N-type has in source area Ggnmos transistor.
- 9. refer to GGNMOS devices as claimed in claim 8, it is characterised in that all GGNMOS more The source area of transistor connects as one, and is arranged in comb teeth-shaped.
- 10. refer to GGNMOS devices as claimed in claim 8, it is characterised in that all GGNMOS more The drain region of transistor connects as one, and is arranged in comb teeth-shaped.
- 11. refer to GGNMOS devices as claimed in claim 8, it is characterised in that two neighboring more Ggnmos transistor is common drain area transistor；Or the drain region of two neighboring ggnmos transistor Independently of each other, and in the P type substrate between the drain region of adjacent ggnmos transistor it is provided with N-type Trap is connected, and N-type connection trap is connected with the drain region of its both sides.
- 12. refer to GGNMOS devices as claimed in claim 8, it is characterised in that in all GGNMOS more The N-type of transistor periphery, which has, is provided with pick-up area in source area.
- 13. refer to GGNMOS devices as claimed in claim 12, it is characterised in that all GGNMOS more Grid structure, the source area of transistor are grounded, the pick-up area ground connection, all ggnmos transistors Drain region connects external circuit.
- 14. refer to GGNMOS devices as claimed in claim 8, it is characterised in that all GGNMOS more The specification of the p-type ion implantation region to be suspended in the drain region of transistor is identical.
- 15. refer to GGNMOS devices as claimed in claim 8, it is characterised in that all GGNMOS more The specification of transistor is identical.
- 16. a kind of electrostatic discharge protective circuit, it is characterised in that including input, earth terminal and at least one Ggnmos transistor any one of claim 1 to 7, the P of each ggnmos transistor Type substrate, source area, grid structure are connected to the earth terminal, the drain electrode of each ggnmos transistor Area is connected to the input by corresponding dead resistance；Or including any one of claim 8 to 15 Described more finger GGNMOS devices, all ggnmos transistors for referring to GGNMOS devices more Grid structure, source area be connected to the earth terminal, it is described to refer to all of GGNMOS devices more The drain region of ggnmos transistor is connected to the input by corresponding dead resistance.
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| WO2020247900A1 (en) | 2019-06-06 | 2020-12-10 | Texas Instruments Incorporated | Zener-triggered transistor with vertically integrated zener diode |
| WO2023098174A1 (en) * | 2021-11-30 | 2023-06-08 | 无锡华润上华科技有限公司 | Electrostatic discharge protection structure |
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| CN105514101A (en) * | 2014-10-14 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | ESD device, manufacturing method of ESD device and EEPROM |
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