CN107346749A - Manufacture of semiconductor and its process apparatus and control device - Google Patents
Manufacture of semiconductor and its process apparatus and control device Download PDFInfo
- Publication number
- CN107346749A CN107346749A CN201610289162.0A CN201610289162A CN107346749A CN 107346749 A CN107346749 A CN 107346749A CN 201610289162 A CN201610289162 A CN 201610289162A CN 107346749 A CN107346749 A CN 107346749A
- Authority
- CN
- China
- Prior art keywords
- wafer
- fabrication steps
- information
- manufacture
- process parameter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Abstract
The present invention provides a kind of manufacture of semiconductor and its process apparatus and control device.Wherein manufacture of semiconductor includes:First fabrication steps are carried out to the first wafer;After first fabrication steps are completed, the actual surface topographical information according to first wafer obtains the first not recoverable error information;And according to described first not recoverable error information adjust the process parameter of first fabrication steps.The present invention more proposes to be applicable the process apparatus and control device of this manufacture of semiconductor.The present invention helps to reduce the follow-up caused not recoverable error of fabrication steps, Real-time Feedback fabrication errors, realizes the on-line real time monitoring of manufacture of semiconductor, effectively improves process rate.
Description
Technical field
The present embodiments relate to a kind of manufacture of semiconductor and its process apparatus and control device, more particularly to
A kind of by feedback, recoverable error does not adjust process parameter, to improve the manufacture of semiconductor of process rate
And its process apparatus and control device.
Background technology
In manufacture of semiconductor, crystal column surface can be caused as the wafer unevenness caused by various possible factors
The defects of pattern.This problem is even more serious in crystal round fringes, and may be in wafer back-end process (Back End
Of Line, BEOL) the step of problem occurs.Such as may be in cmp
Grinding insufficient (under-polish) or grinding occur for (Chemical-Mechanical Polishing, CMP) step
Excessively (over-polish), so as to cause follow-up micro-photographing process that defocus (defocus) occurs the problem of.Therefore,
The process rate for being favorably improved wafer is monitored and improved for the surface topography of crystal round fringes.However,
Existing detection technique exist coverage rate deficiency, sensitivity and sampling efficiency (capture rate) it is low and feedback
The problems such as overlong time.
The content of the invention
The embodiment of the present invention provides a kind of manufacture of semiconductor, including:First processing procedure step is carried out to the first wafer
Suddenly;After first fabrication steps are completed, the actual surface pattern according to first wafer
(topography) not recoverable error (Non-correctable Error, the NCE) information of acquisition of information first;With
And according to described first not recoverable error information adjust the process parameter of first fabrication steps
(recipe)。
The embodiment of the present invention more provides a kind of control device of manufacture of semiconductor, including I/O unit,
Storage element and processor.The I/O unit is configured to receive completes fabrication steps in wafer
The actual surface topographical information of the acquired wafer afterwards.The storage element is configured to described in storage
The process parameter of fabrication steps.In addition, the processor is couple to the I/O unit and described
Storage element.The processor is configured to according to the actual surface topographical information and is obtained from the system
The difference of the expection surface topography information of journey parameter obtains not recoverable error information, and according to described
Recoverable error information does not adjust the process parameter of the fabrication steps.
The embodiment of the present invention provide again a kind of semi-conductor processing equipment, including processing apparatus, detection means with
And control device.The processing apparatus is configured to carry out fabrication steps to wafer.The detection means quilt
It is arranged to after the fabrication steps are completed, obtains the actual surface topographical information of the wafer.The control
Device processed includes I/O unit, storage element and processor.The I/O unit is set
Into the reception actual surface topographical information.The storage element is configured to store the fabrication steps
Process parameter.In addition, the processor couples the I/O unit and the storage element.Institute
Processor is stated to be configured to according to the actual surface topographical information and the expection for being obtained from the process parameter
The difference of surface topography information obtains not recoverable error information, and according to the not recoverable error
Information adjusts the process parameter of the fabrication steps.
Based on above-mentioned, the crystal column surface pattern that the embodiment of the present invention is formed by inspection process step obtains
Take not recoverable error information, and will described in not recoverable error feedback of the information to inspection process, to
The process parameter of adjustment fabrication steps in real time.In this way, help to reduce the fabrication steps subsequently caused
Not recoverable error, Real-time Feedback fabrication errors, realize that online (inline) of manufacture of semiconductor is monitored in real time,
And process rate can be effectively improved.On the other hand, by detection crystal column surface pattern acquired in can not school
Positive error information can cover the crystal column surface of the overwhelming majority, and with good detection coverage rate, sensitive
Degree and sampling efficiency.
For allow the embodiment of the present invention features described above and advantage can become apparent, special embodiment below,
And accompanying drawing is coordinated to be described in detail below.
Brief description of the drawings
Fig. 1 is the block diagram of the semi-conductor processing equipment according to one embodiment of the invention;
Fig. 2 is the block diagram of the control device according to one embodiment of the invention;
Fig. 3 is the flow chart of the manufacture of semiconductor according to one embodiment of the invention;
Fig. 4 displays carry out on-line real time monitoring with returning according to one embodiment of the invention in manufacture of semiconductor
The step of feedback;
Fig. 5 further shows the idiographic flow of Fig. 4 step 420;
The step of manufacture of semiconductor of Fig. 6 display foundation another embodiment of the present invention;
The step of manufacture of semiconductor of Fig. 7 display foundation further embodiment of this invention.
Reference:
100:Semi-conductor processing equipment
110:Processing apparatus
120:Detection means
130:Control device
132:I/O unit
134:Storage element
134a:Process parameter
134b:Actual surface topographical information
136:Processor
138:Bus
310~360,410~430,510~520,610,710~730:Step
Embodiment
The following content of the invention provides many different embodiments of the different characteristic for implementing provided target
Or example.Component discussed below and the instantiation of configuration are to pass on this hair in a simplified manner
For the purpose of bright.Certainly, these are only example and are not used to limit.For example, in following description,
Second feature is formed above fisrt feature or in fisrt feature may include second feature and fisrt feature shape
As the embodiment directly contacted, and also may include can be formed with extra between second feature and fisrt feature
Feature causes the embodiment that second feature and fisrt feature can be not directly contacted with.In addition, the present invention is various
Identical element numbers and/or letter can be used in example to refer to same or similar part.Element numbers
Reuse be for the sake of simple and clear, and be not offered as each embodiment to be discussed and/or
Relation between configuration in itself.
In addition, for ease of describing, a shown component or feature and another component or spy in accompanying drawing
The relation of sign, can be used herein for example " ... under ", " in ... lower section ", " bottom ", " ...
On ", " in ... top ", the space relative terms of " top " and similar terms.Except institute in accompanying drawing
Outside the orientation of display, the space relative terms are intended to cover difference of the component in use or operation and determined
To.Equipment can be otherwise oriented and (be rotated by 90 ° or in other orientations), and space used herein is relative
Term can correspondingly be made explanations.
In addition, embodiments disclosed below and unnecessarily illustrating all components come across in structure or spy
Sign.For example, multiple kenels of single component may be omitted in schema, and the explanation of single component
The different patterns in multiple embodiments will be enough to pass on.In addition, methods discussed herein embodiment can be according to
Carried out according to specific order;However, other embodiment can also be entered according to any logical order
OK.
Fig. 1 is the block diagram of the semi-conductor processing equipment according to one embodiment of the invention.As indicated with 1,
Semi-conductor processing equipment 100 includes processing apparatus 110, detection means 120 and control device 130.Institute
Processing apparatus 110 is stated to be configured to carry out fabrication steps to wafer.The detection means 120 is configured to
After the fabrication steps are completed, the actual surface topographical information of the wafer is obtained.The control device
130 obtain not recoverable error information according to the actual surface topographical information of the wafer, and according to
The process parameter of the fabrication steps is adjusted according to acquired not recoverable error information.
More specifically, the processing apparatus 110 of the present embodiment is, for example, for thin film deposition, chemical machinery
It is at least one in many semiconductor processing steps such as grinding or lithographic (lithography), it is various to perform
Semiconductor structure manufactures and following a lithography step, including coating (coating), calibration, exposure (exposure), baking
The various processing such as roasting (baking), development (developing), patterning (patterning), grinding (polish) or
Measuring equipment.In other words, wafer mentioned here be, for example, have basic semiconductor (for example, crystal silicon,
Polysilicon, non-crystalline silicon, germanium and diamond), compound semiconductor (for example, carborundum and gallium arsenic), alloy half
Conductor (for example, SiGe, gallium arsenide phosphide, indium arsenide aluminium, phosphatization gallium aluminium and InGaP) or its any group
The semiconductor crystal wafer (or wafer) of conjunction.In addition, with the progress of fabrication steps, may be on the wafer
Formed with complete or partial semiconductor assembly structure.
In addition, the not recoverable error information is for example comprising the not recoverable of one or more on the wafer
The position of error and degree.For example, the degree of recoverable error is not, for example, in the same of the wafer
Actual surface topographical information on one position and the expection surface topography information for being obtained from the process parameter
Difference.By taking the exposure actions in cmp step or following a lithography step as an example, the process parameter example
In this way processing apparatus relative to wafer scanning setup parameter, such as carrying wafer microscope carrier relative to grinding
Instrument or exposure light source translated, is rotated or the moving parameter of pitching motion.
In the present embodiment, the wafer can be scanned by detection means 120, to obtain the wafer
Actual surface topographical information.The detection means 120 may include image-forming assembly, for example, LASER Light Source or its
The light source of his wavelength, to project the light beam of specific wavelength to the top of the diverse location of crystal column surface or under
Side.Then, reflect the spent time from the diverse location of crystal column surface according to light beam or reflection is special
Property, such as the intensity of reflected light, height of the wafer on each position can be determined.
Also, in certain embodiments, first position of first light beam to wafer can be launched, to measure crystalline substance
The round height in first position, and the focus of light source is adjusted, focus the beam onto the second on wafer
Put, to measure height of the wafer in the second place.This action can be ongoing, until there is foot on wafer
Untill enough multipoint height are determined.In certain embodiments, more than 20,000 positions may be entered
Row aforementioned activities, to determine the height of each position.Thereby, it can obtain the actual surface pattern letter of wafer
Breath.Also, compare the actual surface topographical information of wafer and be obtained from the expection surface of the process parameter
Topographical information, to obtain the overall not recoverable error information of wafer.
Fig. 2 is the block diagram of the foregoing control device 130 according to one embodiment of the invention.Such as Fig. 2 institutes
Show, control device 130 includes I/O unit 132, storage element 134 and processor 136.
The I/O unit 132 can be received come the reality of self-test device 120 by bus (Bus) 138
Border surface topography information.The storage element 134 connects bus 138, and is configured to described in storage
The process parameter 134a of fabrication steps, such as processing apparatus is relative to the scanning setup parameter of wafer.At certain
In a little embodiments, storage element 134 is also configured to store the reality that I/O unit 132 is received
Border surface topography information 134b.In fact, storage element 134 can be any possible kenel, such as count
Media can be read in calculation machine, including:Floppy disk, hard disk, tape, random magnetism medium, CD-ROM, appoint
Anticipate optical medium, punch card (punch card), paper self-adhesive tape, any physical media with hole, random
Access memory, programmble read only memory PROM, formula of erasing programmble read only memory PROM, the formula of erasing of flashing
Programmble read only memory PROM, any memory chip or cassette tape, carrier wave or other can be by computer
Any media read.
The processor 136 e.g. microprocessor, application specific integrated circuit or other appropriate logic modules,
And I/O unit 132 and the storage element 134 are coupled by bus 138, with according to institute
The difference of expection surface topography information of the actual surface topographical information with being obtained from the process parameter is stated to obtain
Not recoverable error information is taken, and processing procedure is output control signals to according to the not recoverable error information
Device 110, to adjust the process parameter of the fabrication steps.
Fig. 3 is a kind of flow chart of manufacture of semiconductor according to one embodiment of the invention, wherein enumerating crystalline substance
Several common steps in circle back-end process, to illustrate that the embodiment of the present invention realizes on-line real time monitoring
Method.Certainly, the multiple step may be carried out according to other orders in other embodiments, Huo Zheyou
Part steps are omitted, or insert other steps.
As shown in figure 3, wafer back-end process may carry out the thin film deposition of such as copper metal or other materials
310th, 320 (such as cmps), 360 steps of lithographic 330, etching 350 and cleaning are ground.
In addition, for example after lithographic 330, detection 340 can be carried out to wafer, wherein for example by foregoing inspection
The actual surface topographical information surveyed after the measurement wafer completion lithographic 330 of device 120.Also, according to reality
Border surface topography information obtains not recoverable error information, will not recoverable error feedback of the information to elder generation
The preceding step such as grinding 320 or lithographic 330, uses the process parameter for adjusting the fabrication steps.
Now, the processing apparatus 110 shown in Fig. 1 is, for example, the dress for being ground the step such as 320 or lithographic 330
Put, and the process parameter being adjusted is, for example, scanning setup parameter of the processing apparatus relative to wafer,
Such as the microscope carrier of carrying wafer is translated relative to milling tool or exposure light source, rotated or pitching motion
Moving parameter.
By preceding method, the process parameter of processing apparatus can be optimized so that next wafer is being carried out
The actual surface pattern closer to expected surface topography can be obtained after this fabrication steps, and reduction can not school
Positive error.
Fig. 4 is shown by such as semi-conductor processing equipment 100 in the manufacture of semiconductor for example shown in Fig. 3
The step of carrying out on-line real time monitoring and feedback.First, as indicated at step 410, first is carried out to wafer
Fabrication steps.Here, the first fabrication steps are, for example, grinding 320 or the grade of lithographic 330 step shown in Fig. 3
Suddenly.
Then, after first fabrication steps are completed, as shown at step 420, according to the wafer
Actual surface topographical information obtains the first not recoverable error information.Fig. 5 further shows the tool of this step
Body flow.As indicated in step 510, e.g. scanned by the detection means 120 as shown in Figure 1
The wafer, to obtain the actual surface topographical information of the wafer.Now, control as shown in Figure 2
Device 130 can receive the actual surface pattern for carrying out self-test device 120 by I/O unit 132
Information, and be stored in storage element 134.Afterwards, step 520 is carried out, as shown in Figure 2
Processor 136 can join according to the actual surface topographical information with advance be stored in the processing procedure of storage element
The difference between expection surface topography information obtained by number obtains the first not recoverable error information.
Afterwards, as illustrated by step 430 of fig. 4, recoverable error information is not described to adjust for foundation first
The process parameter of first fabrication steps.Now, processor 136 can be according to the first not recoverable error information
Processing apparatus 110 is output control signals to, to adjust the process parameter of first fabrication steps.Such as
It is to adjust scanning setup parameter of the processing apparatus 110 relative to wafer, such as the microscope carrier phase of carrying wafer
Translated, rotated or the moving parameter of pitching motion for milling tool or exposure light source.
The step of manufacture of semiconductor of Fig. 6 display foundation another embodiment of the present invention.As shown in fig. 6,
After completing the on-line real time monitoring shown in Fig. 4 and step 410~430 of feedback, the first fabrication steps
Process parameter has been adjusted.Afterwards, can as indicated in step 610, according to the process parameter pair after adjustment
Subsequently the first fabrication steps are carried out into another wafer of processing apparatus 110.In this way, it may be such that described
Another wafer can obtain the actual surface pattern closer to expected surface topography after this fabrication steps is carried out,
And reduce not recoverable error.
The step of manufacture of semiconductor of Fig. 7 display foundation further embodiment of this invention.As shown in fig. 7,
Complete Fig. 4 shown in on-line real time monitoring and feedback step 410~430 after or simultaneously, can be such as step
Shown in 710, the second follow-up fabrication steps are carried out to wafer.Here, it can also select with identical side
Method carries out on-line real time monitoring and feedback to the second fabrication steps.That is, as shown in step 720,
After second fabrication steps are completed, the actual surface topographical information according to the wafer obtains second not
Recoverable error information.Also, as indicated by step 730, according to second not recoverable error information adjust
The process parameter of whole second fabrication steps.It is foregoing right that the specific practice of step 720 and step 730 can refer to
In step 420 and the explanation of step 430, repeated no more in this.
In other words, embodiments disclosed herein is a series of several steps enumerated in semiconductor processing steps
Suddenly illustrate.In fact, the fabrication steps for being applicable to the technical scheme of the embodiment of the present invention are not limited to
This.This field those of ordinary skill is after the embodiment of the present invention is considered in light of actual conditions, when optional by the embodiment of the present invention
Technical scheme be applied to specific or even all possible semiconductor processing steps, with Real-time Feedback processing procedure
As a result the process parameter of prior procedures step and is later adjusted, is realized to the whole or specific of manufacture of semiconductor
The on-line real time monitoring of step, improve process rate.
In summary, the embodiment of the present invention is formed by inspection process step crystal column surface pattern obtains
Take not recoverable error information, and will described in not recoverable error feedback of the information to inspection process, to
The process parameter of adjustment fabrication steps in real time.Because the detection for not recoverable error can cover absolutely greatly
Partial crystal column surface, carry out than the known greater area of detection of detection instrument, therefore can provide good
Detection coverage rate.In addition, what the detection for not recoverable error was also carried out than known detection instrument
Detection has more preferable sensitivity and sampling efficiency.
Further, since the embodiment of the present invention is to come between semiconductor processing steps by not recoverable error
Real-time Feedback and adjustment process parameter are carried out, therefore can realize that online (inline) of manufacture of semiconductor is supervised in real time
Survey.Compared to the known detection carried out in processing procedure latter end, need to expend a month even more long time could
Fabrication errors are fed back into fabrication steps, the technical scheme of the embodiment of the present invention can incite somebody to action by real-time monitoring
Fabrication errors rapid feedback can effectively improve process rate to FEOL.
One embodiment of the invention proposes a kind of manufacture of semiconductor, including:The first system is carried out to the first wafer
Journey step;After first fabrication steps are completed, the actual surface pattern according to first wafer is believed
Cease the not recoverable error information of acquisition first;And according to described first not recoverable error information adjust
The process parameter of whole first fabrication steps.
Another embodiment of the present invention proposes a kind of control device of manufacture of semiconductor, and it includes input/output
Unit, storage element and processor.The I/O unit is configured to receive and completes to make in wafer
The actual surface topographical information of the acquired wafer after journey step.The storage element is configured to store up
Deposit the process parameter of the fabrication steps.In addition, the processor be couple to the I/O unit with
And the storage element.The processor is configured to according to the actual surface topographical information with being obtained from
The difference of the expection surface topography information of the process parameter obtains not recoverable error information, and according to
The process parameter of the fabrication steps is adjusted according to the not recoverable error information.
Another embodiment of the present invention proposes a kind of semi-conductor processing equipment, and it includes processing apparatus, detection
Device and control device.The processing apparatus is configured to carry out fabrication steps to wafer.The detection
After device is provided in the completion fabrication steps, the actual surface topographical information of the wafer is obtained.
The control device includes I/O unit, storage element and processor.The I/O unit
It is configured to receive the actual surface topographical information.The storage element is configured to store the processing procedure
The process parameter of step.In addition, the processor couples the I/O unit and the storage is single
Member.The processor is configured to according to the actual surface topographical information and is obtained from the process parameter
The difference of expection surface topography information obtain not recoverable error information, and according to it is described can not school
Positive error information adjusts the process parameter of the fabrication steps.
Foregoing has outlined the feature of several embodiments, those of ordinary skill in the art is better understood upon this hair
The aspect of bright embodiment.It will be recognized by one of ordinary skill in the art that it can be implemented using the present invention easily
Example is as the foundation for designing or changing other processing procedures and structure, to carry out the phase of embodiments described herein
With purpose and/or reach same advantage.Those of ordinary skill in the art should also be understood that this equivalent configuration
Without departing from the spirit and scope of the embodiment of the present invention, and those of ordinary skill in the art are without departing substantially from this hair
Can be to making various changes, displacement and change herein in the case of the spirit and scope of bright embodiment.
Claims (10)
- A kind of 1. manufacture of semiconductor, it is characterised in that including:First fabrication steps are carried out to the first wafer;After first fabrication steps are completed, the actual surface topographical information according to first wafer obtains Take the first not recoverable error information;AndAccording to described first not recoverable error information adjust the process parameter of first fabrication steps.
- 2. manufacture of semiconductor according to claim 1, it is characterised in that also include:Come to carry out first fabrication steps to the second wafer according to the process parameter after adjustment.
- 3. manufacture of semiconductor according to claim 1, it is characterised in that also include:Second fabrication steps are carried out to first wafer;After second fabrication steps are completed, the actual surface topographical information according to first wafer obtains Take the second not recoverable error information;AndAccording to described second not recoverable error information adjust the process parameter of second fabrication steps.
- 4. manufacture of semiconductor according to claim 1, it is characterised in that obtaining described first can not The step of correction error information, includes:First wafer is scanned to obtain the actual surface topographical information of first wafer;AndAccording to the actual surface topographical information and the difference of expected surface topography information, described first is obtained Not recoverable error information.
- 5. manufacture of semiconductor according to claim 4, it is characterised in that the expected surface topography Information is obtained from the process parameter of first fabrication steps.
- 6. manufacture of semiconductor according to claim 5, it is characterised in that the process parameter includes Processing apparatus relative to the wafer scanning setup parameter.
- A kind of 7. control device of manufacture of semiconductor, it is characterised in that including:I/O unit, it is configured to receive the acquired wafer after wafer completes fabrication steps Actual surface topographical information;Storage element, it is configured to store the process parameter of the fabrication steps;AndProcessor, is couple to the I/O unit and the storage element, and the processor is set It is set to according to the actual surface topographical information and the expection surface topography information for being obtained from the process parameter Difference obtain not recoverable error information, and according to the not recoverable error information to adjust State the process parameter of fabrication steps.
- 8. the control device of manufacture of semiconductor according to claim 7, it is characterised in that the control Device processed is couple to processing apparatus, to carry out the fabrication steps, and the processing procedure to the wafer Parameter includes scanning setup parameter of the processing apparatus relative to the wafer.
- A kind of 9. semi-conductor processing equipment, it is characterised in that including:Processing apparatus, it is configured to carry out fabrication steps to wafer;Detection means, it is provided in after completing the fabrication steps, obtains the actual surface of the wafer Topographical information;Control device, including:I/O unit, it is configured to receive the actual surface topographical information;Storage element, it is configured to store the process parameter of the fabrication steps;AndProcessor, couple the I/O unit and the storage element, the processor quilt It is arranged to according to the actual surface topographical information and the expection surface shape for being obtained from the process parameter The difference of looks information is believed to obtain not recoverable error information according to the not recoverable error Cease to adjust the process parameter of the fabrication steps.
- 10. semi-conductor processing equipment according to claim 9, it is characterised in that the processing procedure ginseng Number includes scanning setup parameter of the processing apparatus relative to the wafer.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202110205689.1A CN113013049B (en) | 2016-05-04 | 2016-05-04 | Semiconductor process and its processing equipment and control device |
CN201610289162.0A CN107346749A (en) | 2016-05-04 | 2016-05-04 | Manufacture of semiconductor and its process apparatus and control device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610289162.0A CN107346749A (en) | 2016-05-04 | 2016-05-04 | Manufacture of semiconductor and its process apparatus and control device |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202110205689.1A Division CN113013049B (en) | 2016-05-04 | 2016-05-04 | Semiconductor process and its processing equipment and control device |
Publications (1)
Publication Number | Publication Date |
---|---|
CN107346749A true CN107346749A (en) | 2017-11-14 |
Family
ID=60252992
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610289162.0A Pending CN107346749A (en) | 2016-05-04 | 2016-05-04 | Manufacture of semiconductor and its process apparatus and control device |
CN202110205689.1A Active CN113013049B (en) | 2016-05-04 | 2016-05-04 | Semiconductor process and its processing equipment and control device |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202110205689.1A Active CN113013049B (en) | 2016-05-04 | 2016-05-04 | Semiconductor process and its processing equipment and control device |
Country Status (1)
Country | Link |
---|---|
CN (2) | CN107346749A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110044295A (en) * | 2017-11-30 | 2019-07-23 | 台湾积体电路制造股份有限公司 | The method on scanning and analysis surface, its inspection system and computer-readable media |
CN111190393A (en) * | 2018-11-14 | 2020-05-22 | 长鑫存储技术有限公司 | Semiconductor process automation control method and device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020192966A1 (en) * | 2001-06-19 | 2002-12-19 | Shanmugasundram Arulkumar P. | In situ sensor based control of semiconductor processing procedure |
CN1711632A (en) * | 2002-11-12 | 2005-12-21 | 应用材料股份有限公司 | Method and apparatus employing integrated metrology for improved dielectric etch efficiency |
CN104049468A (en) * | 2013-03-14 | 2014-09-17 | 台湾积体电路制造股份有限公司 | System and method for applying photoetching technology in semiconductor device manufacture |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0163199A3 (en) * | 1984-05-29 | 1988-09-14 | Siemens Aktiengesellschaft | Process and apparatus for determining registration faults of successive structures incorporated in semiconductor substrate |
JP3316829B2 (en) * | 1989-09-22 | 2002-08-19 | 株式会社日立製作所 | Comparative inspection method and device |
JPH07141005A (en) * | 1993-06-21 | 1995-06-02 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device and the device for the same |
US6248602B1 (en) * | 1999-11-01 | 2001-06-19 | Amd, Inc. | Method and apparatus for automated rework within run-to-run control semiconductor manufacturing |
DE10037243C2 (en) * | 2000-07-31 | 2002-06-20 | Infineon Technologies Ag | Control system for photolithographic processes |
TW569085B (en) * | 2002-09-12 | 2004-01-01 | Taiwan Semiconductor Mfg | Adjusting method of semiconductor machine and method of using the same to adjust semiconductor lithography machine |
TWI222663B (en) * | 2003-05-21 | 2004-10-21 | Taiwan Semiconductor Mfg | Method and system for deviation parts predication of semiconductor device and storage medium |
US20060043071A1 (en) * | 2004-09-02 | 2006-03-02 | Liang-Lun Lee | System and method for process control using in-situ thickness measurement |
US20060240651A1 (en) * | 2005-04-26 | 2006-10-26 | Varian Semiconductor Equipment Associates, Inc. | Methods and apparatus for adjusting ion implant parameters for improved process control |
US7144297B2 (en) * | 2005-05-03 | 2006-12-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus to enable accurate wafer prediction |
JP4741408B2 (en) * | 2006-04-27 | 2011-08-03 | 株式会社荏原製作所 | XY coordinate correction apparatus and method in sample pattern inspection apparatus |
JP2011222636A (en) * | 2010-04-07 | 2011-11-04 | Hitachi High-Technologies Corp | Inspection apparatus, inspection method, and defect coordinate correction method |
US20120053723A1 (en) * | 2010-08-30 | 2012-03-01 | Matthias Richter | Method of Controlling a Process and Process Control System |
US9403254B2 (en) * | 2011-08-17 | 2016-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for real-time error detection in CMP processing |
TW201324600A (en) * | 2011-12-09 | 2013-06-16 | United Microelectronics Corp | CMP process and CMP system |
US10576603B2 (en) * | 2014-04-22 | 2020-03-03 | Kla-Tencor Corporation | Patterned wafer geometry measurements for semiconductor process controls |
-
2016
- 2016-05-04 CN CN201610289162.0A patent/CN107346749A/en active Pending
- 2016-05-04 CN CN202110205689.1A patent/CN113013049B/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020192966A1 (en) * | 2001-06-19 | 2002-12-19 | Shanmugasundram Arulkumar P. | In situ sensor based control of semiconductor processing procedure |
CN1711632A (en) * | 2002-11-12 | 2005-12-21 | 应用材料股份有限公司 | Method and apparatus employing integrated metrology for improved dielectric etch efficiency |
CN104049468A (en) * | 2013-03-14 | 2014-09-17 | 台湾积体电路制造股份有限公司 | System and method for applying photoetching technology in semiconductor device manufacture |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110044295A (en) * | 2017-11-30 | 2019-07-23 | 台湾积体电路制造股份有限公司 | The method on scanning and analysis surface, its inspection system and computer-readable media |
CN110044295B (en) * | 2017-11-30 | 2021-12-03 | 台湾积体电路制造股份有限公司 | Method for scanning and analyzing a surface, inspection system and computer readable medium therefor |
CN111190393A (en) * | 2018-11-14 | 2020-05-22 | 长鑫存储技术有限公司 | Semiconductor process automation control method and device |
CN111190393B (en) * | 2018-11-14 | 2021-07-23 | 长鑫存储技术有限公司 | Semiconductor process automation control method and device |
Also Published As
Publication number | Publication date |
---|---|
CN113013049A (en) | 2021-06-22 |
CN113013049B (en) | 2023-04-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6553145B2 (en) | How to determine overlay error | |
CN106062634B (en) | Measurement is related to the procedure parameter of the manufacturing process of photolithography | |
TWI667717B (en) | Outlier detection on pattern of interest image populations | |
US6363168B1 (en) | Measurement position determination on a semiconductor wafer | |
TWI581068B (en) | Lithographic apparatus, device manufacturing method, and method of applying a pattern to a substrate | |
CN1751378B (en) | Detection method for optimum position detection formula, alignment method, exposure method, device production method, and device | |
JP5808347B2 (en) | Method and system for providing correction values for process tools | |
TW201708985A (en) | Recipe selection based on inter-recipe consistency | |
US8571300B2 (en) | Focus finding and alignment using a split linear mask | |
CN109073999A (en) | Method and apparatus for determining the parameter of Patternized technique | |
US10101675B2 (en) | Metrology apparatus, method of measuring a structure and lithographic apparatus | |
US20170031246A1 (en) | Inspection Apparatus, Inspection Method and Manufacturing Method | |
CN105874387A (en) | Method and apparatus for design of a metrology target | |
JPH0760789B2 (en) | How to control photoengraving tools | |
US9971478B2 (en) | Method and apparatus for inspection and metrology | |
JP5916738B2 (en) | Method and system for providing device-induced errors using a subsampling scheme | |
US11181489B2 (en) | Determining tilt angle in patterned arrays of high aspect-ratio structures by small-angle x-ray scattering | |
CN108700816A (en) | Polarization tuning in scatterometry | |
CN106537572A (en) | Treatment method and treatment device for circulating water of wet type coating booth | |
TWI653514B (en) | Method for measuring substrate property, detecting device, lithography system and component manufacturing method | |
CN107346749A (en) | Manufacture of semiconductor and its process apparatus and control device | |
US10754260B2 (en) | Method and system for process control with flexible sampling | |
JPH10173029A (en) | Method of determining measuring positions of wafer | |
TW202141210A (en) | Determining metrology-like information for a specimen using an inspection tool | |
TWI636339B (en) | Method for characterizing distortions in a lithographic process, lithographic apparatus, lithographic cell and computer program |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20171114 |
|
RJ01 | Rejection of invention patent application after publication |